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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-03-19 08:39:58 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-03-19 08:39:58 -0400
commit14b6848bc0134b8838d374c423df3edda9b1490e (patch)
tree724dc912efe84f432d33a798502811c5f5295774 /arch/arm/mach-omap2
parent05d9881bc4c6f172997b7a59e4a1a95910c4ebd7 (diff)
parent4da3782151300237db3abe070f716922889252e0 (diff)
Merge branch 'omap-clks3' into devel
Conflicts: arch/arm/mach-omap2/clock.c
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c2
-rw-r--r--arch/arm/mach-omap2/clock.c499
-rw-r--r--arch/arm/mach-omap2/clock.h24
-rw-r--r--arch/arm/mach-omap2/clock24xx.c377
-rw-r--r--arch/arm/mach-omap2/clock24xx.h525
-rw-r--r--arch/arm/mach-omap2/clock34xx.c582
-rw-r--r--arch/arm/mach-omap2/clock34xx.h1076
-rw-r--r--arch/arm/mach-omap2/clockdomain.c76
-rw-r--r--arch/arm/mach-omap2/clockdomains.h118
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h80
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h121
-rw-r--r--arch/arm/mach-omap2/devices.c5
-rw-r--r--arch/arm/mach-omap2/id.c7
-rw-r--r--arch/arm/mach-omap2/io.c8
-rw-r--r--arch/arm/mach-omap2/mcbsp.c26
-rw-r--r--arch/arm/mach-omap2/memory.h43
-rw-r--r--arch/arm/mach-omap2/pm.c2
-rw-r--r--arch/arm/mach-omap2/powerdomains.h8
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h68
-rw-r--r--arch/arm/mach-omap2/prcm-common.h198
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h9
-rw-r--r--arch/arm/mach-omap2/prm.h24
-rw-r--r--arch/arm/mach-omap2/sdrc.c93
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c (renamed from arch/arm/mach-omap2/memory.c)90
30 files changed, 2350 insertions, 1727 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bbd12bc10fdc..9717afcdbda7 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ 6obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ 7 devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
8 clockdomain.o 8 clockdomain.o
9 9
@@ -14,6 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o 15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
16 16
17# SMS/SDRC
18obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
19# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
20
17# Power Management 21# Power Management
18ifeq ($(CONFIG_PM),y) 22ifeq ($(CONFIG_PM),y)
19obj-y += pm.o 23obj-y += pm.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 83fa37211d77..7b29e1d00f23 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -185,7 +185,7 @@ out:
185 185
186static void __init omap_2430sdp_init_irq(void) 186static void __init omap_2430sdp_init_irq(void)
187{ 187{
188 omap2_init_common_hw(); 188 omap2_init_common_hw(NULL);
189 omap_init_irq(); 189 omap_init_irq();
190 omap_gpio_init(); 190 omap_gpio_init();
191 sdp2430_init_smc91x(); 191 sdp2430_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 0a7b24ba1652..0c911f414d8d 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -249,7 +249,7 @@ out:
249 249
250static void __init omap_apollon_init_irq(void) 250static void __init omap_apollon_init_irq(void)
251{ 251{
252 omap2_init_common_hw(); 252 omap2_init_common_hw(NULL);
253 omap_init_irq(); 253 omap_init_irq();
254 omap_gpio_init(); 254 omap_gpio_init();
255 apollon_init_smc91x(); 255 apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3b34c20d1df4..3492162a65c3 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
33 33
34static void __init omap_generic_init_irq(void) 34static void __init omap_generic_init_irq(void)
35{ 35{
36 omap2_init_common_hw(); 36 omap2_init_common_hw(NULL);
37 omap_init_irq(); 37 omap_init_irq();
38} 38}
39 39
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 5e9b14675b1e..ef55b45ab769 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -363,7 +363,7 @@ static void __init h4_init_flash(void)
363 363
364static void __init omap_h4_init_irq(void) 364static void __init omap_h4_init_irq(void)
365{ 365{
366 omap2_init_common_hw(); 366 omap2_init_common_hw(NULL);
367 omap_init_irq(); 367 omap_init_irq();
368 omap_gpio_init(); 368 omap_gpio_init();
369 h4_init_flash(); 369 h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 6031e179926b..73e3fdb2d20a 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -98,7 +98,7 @@ static inline void __init ldp_init_smc911x(void)
98 98
99static void __init omap_ldp_init_irq(void) 99static void __init omap_ldp_init_irq(void)
100{ 100{
101 omap2_init_common_hw(); 101 omap2_init_common_hw(NULL);
102 omap_init_irq(); 102 omap_init_irq();
103 omap_gpio_init(); 103 omap_gpio_init();
104 ldp_init_smc911x(); 104 ldp_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 38c88fbe658d..ad312ccf2ec5 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -184,7 +184,7 @@ static int __init omap3_beagle_i2c_init(void)
184 184
185static void __init omap3_beagle_init_irq(void) 185static void __init omap3_beagle_init_irq(void)
186{ 186{
187 omap2_init_common_hw(); 187 omap2_init_common_hw(NULL);
188 omap_init_irq(); 188 omap_init_irq();
189 omap_gpio_init(); 189 omap_gpio_init();
190} 190}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ce4d46a4a838..4247a1534411 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,11 +26,10 @@
26 26
27#include <mach/clock.h> 27#include <mach/clock.h>
28#include <mach/clockdomain.h> 28#include <mach/clockdomain.h>
29#include <mach/sram.h>
30#include <mach/cpu.h> 29#include <mach/cpu.h>
31#include <asm/div64.h> 30#include <asm/div64.h>
32 31
33#include "memory.h" 32#include <mach/sdrc.h>
34#include "sdrc.h" 33#include "sdrc.h"
35#include "clock.h" 34#include "clock.h"
36#include "prm.h" 35#include "prm.h"
@@ -46,7 +45,7 @@
46#define DPLL_MIN_DIVIDER 1 45#define DPLL_MIN_DIVIDER 1
47 46
48/* Possible error results from _dpll_test_mult */ 47/* Possible error results from _dpll_test_mult */
49#define DPLL_MULT_UNDERFLOW (1 << 0) 48#define DPLL_MULT_UNDERFLOW -1
50 49
51/* 50/*
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 51 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
@@ -59,6 +58,16 @@
59#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 58#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 59 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
61 60
61/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
62#define DPLL_FINT_BAND1_MIN 750000
63#define DPLL_FINT_BAND1_MAX 2100000
64#define DPLL_FINT_BAND2_MIN 7500000
65#define DPLL_FINT_BAND2_MAX 21000000
66
67/* _dpll_test_fint() return codes */
68#define DPLL_FINT_UNDERFLOW -1
69#define DPLL_FINT_INVALID -2
70
62u8 cpu_mask; 71u8 cpu_mask;
63 72
64/*------------------------------------------------------------------------- 73/*-------------------------------------------------------------------------
@@ -66,6 +75,74 @@ u8 cpu_mask;
66 *-------------------------------------------------------------------------*/ 75 *-------------------------------------------------------------------------*/
67 76
68/** 77/**
78 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
79 * @clk: struct clk *
80 *
81 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
82 * don't take effect until the VALID_CONFIG bit is written, write the
83 * VALID_CONFIG bit and wait for the write to complete. No return value.
84 */
85static void _omap2xxx_clk_commit(struct clk *clk)
86{
87 if (!cpu_is_omap24xx())
88 return;
89
90 if (!(clk->flags & DELAYED_APP))
91 return;
92
93 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
94 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
95 /* OCP barrier */
96 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
97}
98
99/*
100 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
101 * @clk: DPLL struct clk to test
102 * @n: divider value (N) to test
103 *
104 * Tests whether a particular divider @n will result in a valid DPLL
105 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
106 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
107 * (assuming that it is counting N upwards), or -2 if the enclosing loop
108 * should skip to the next iteration (again assuming N is increasing).
109 */
110static int _dpll_test_fint(struct clk *clk, u8 n)
111{
112 struct dpll_data *dd;
113 long fint;
114 int ret = 0;
115
116 dd = clk->dpll_data;
117
118 /* DPLL divider must result in a valid jitter correction val */
119 fint = clk->parent->rate / (n + 1);
120 if (fint < DPLL_FINT_BAND1_MIN) {
121
122 pr_debug("rejecting n=%d due to Fint failure, "
123 "lowering max_divider\n", n);
124 dd->max_divider = n;
125 ret = DPLL_FINT_UNDERFLOW;
126
127 } else if (fint > DPLL_FINT_BAND1_MAX &&
128 fint < DPLL_FINT_BAND2_MIN) {
129
130 pr_debug("rejecting n=%d due to Fint failure\n", n);
131 ret = DPLL_FINT_INVALID;
132
133 } else if (fint > DPLL_FINT_BAND2_MAX) {
134
135 pr_debug("rejecting n=%d due to Fint failure, "
136 "boosting min_divider\n", n);
137 dd->min_divider = n;
138 ret = DPLL_FINT_INVALID;
139
140 }
141
142 return ret;
143}
144
145/**
69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 146 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
70 * @clk: OMAP clock struct ptr to use 147 * @clk: OMAP clock struct ptr to use
71 * 148 *
@@ -120,7 +197,7 @@ void omap2_init_clksel_parent(struct clk *clk)
120 clk->name, clks->parent->name, 197 clk->name, clks->parent->name,
121 ((clk->parent) ? 198 ((clk->parent) ?
122 clk->parent->name : "NULL")); 199 clk->parent->name : "NULL"));
123 clk->parent = clks->parent; 200 clk_reparent(clk, clks->parent);
124 }; 201 };
125 found = 1; 202 found = 1;
126 } 203 }
@@ -134,25 +211,52 @@ void omap2_init_clksel_parent(struct clk *clk)
134 return; 211 return;
135} 212}
136 213
137/* Returns the DPLL rate */ 214/**
215 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
216 * @clk: struct clk * of a DPLL
217 *
218 * DPLLs can be locked or bypassed - basically, enabled or disabled.
219 * When locked, the DPLL output depends on the M and N values. When
220 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
221 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
222 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
223 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
224 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
225 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
226 * if the clock @clk is not a DPLL.
227 */
138u32 omap2_get_dpll_rate(struct clk *clk) 228u32 omap2_get_dpll_rate(struct clk *clk)
139{ 229{
140 long long dpll_clk; 230 long long dpll_clk;
141 u32 dpll_mult, dpll_div, dpll; 231 u32 dpll_mult, dpll_div, v;
142 struct dpll_data *dd; 232 struct dpll_data *dd;
143 233
144 dd = clk->dpll_data; 234 dd = clk->dpll_data;
145 /* REVISIT: What do we return on error? */
146 if (!dd) 235 if (!dd)
147 return 0; 236 return 0;
148 237
149 dpll = __raw_readl(dd->mult_div1_reg); 238 /* Return bypass rate if DPLL is bypassed */
150 dpll_mult = dpll & dd->mult_mask; 239 v = __raw_readl(dd->control_reg);
240 v &= dd->enable_mask;
241 v >>= __ffs(dd->enable_mask);
242
243 if (cpu_is_omap24xx()) {
244 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
245 v == OMAP2XXX_EN_DPLL_FRBYPASS)
246 return dd->clk_bypass->rate;
247 } else if (cpu_is_omap34xx()) {
248 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
249 v == OMAP3XXX_EN_DPLL_FRBYPASS)
250 return dd->clk_bypass->rate;
251 }
252
253 v = __raw_readl(dd->mult_div1_reg);
254 dpll_mult = v & dd->mult_mask;
151 dpll_mult >>= __ffs(dd->mult_mask); 255 dpll_mult >>= __ffs(dd->mult_mask);
152 dpll_div = dpll & dd->div1_mask; 256 dpll_div = v & dd->div1_mask;
153 dpll_div >>= __ffs(dd->div1_mask); 257 dpll_div >>= __ffs(dd->div1_mask);
154 258
155 dpll_clk = (long long)clk->parent->rate * dpll_mult; 259 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
156 do_div(dpll_clk, dpll_div + 1); 260 do_div(dpll_clk, dpll_div + 1);
157 261
158 return dpll_clk; 262 return dpll_clk;
@@ -162,14 +266,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
162 * Used for clocks that have the same value as the parent clock, 266 * Used for clocks that have the same value as the parent clock,
163 * divided by some factor 267 * divided by some factor
164 */ 268 */
165void omap2_fixed_divisor_recalc(struct clk *clk) 269unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
166{ 270{
167 WARN_ON(!clk->fixed_div); 271 WARN_ON(!clk->fixed_div);
168 272
169 clk->rate = clk->parent->rate / clk->fixed_div; 273 return clk->parent->rate / clk->fixed_div;
170
171 if (clk->flags & RATE_PROPAGATES)
172 propagate_rate(clk);
173} 274}
174 275
175/** 276/**
@@ -190,11 +291,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 291 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
191 * 34xx reverses this, just to keep us on our toes 292 * 34xx reverses this, just to keep us on our toes
192 */ 293 */
193 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { 294 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
194 ena = mask; 295 ena = mask;
195 } else if (cpu_mask & RATE_IN_343X) { 296 else if (cpu_mask & RATE_IN_343X)
196 ena = 0; 297 ena = 0;
197 }
198 298
199 /* Wait for lock */ 299 /* Wait for lock */
200 while (((__raw_readl(reg) & mask) != ena) && 300 while (((__raw_readl(reg) & mask) != ena) &&
@@ -228,31 +328,12 @@ static void omap2_clk_wait_ready(struct clk *clk)
228 * it and pull it into struct clk itself somehow. 328 * it and pull it into struct clk itself somehow.
229 */ 329 */
230 reg = clk->enable_reg; 330 reg = clk->enable_reg;
231 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
232 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
233 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
234 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
235 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
236 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
237 else
238 return;
239 331
240 /* REVISIT: What are the appropriate exclusions for 34XX? */ 332 /*
241 /* No check for DSS or cam clocks */ 333 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
242 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ 334 * it's just a matter of XORing the bits.
243 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || 335 */
244 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || 336 other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
245 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
246 return;
247 }
248
249 /* REVISIT: What are the appropriate exclusions for 34XX? */
250 /* OMAP3: ignore DSS-mod clocks */
251 if (cpu_is_omap34xx() &&
252 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
253 ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
254 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
255 return;
256 337
257 /* Check if both functional and interface clocks 338 /* Check if both functional and interface clocks
258 * are running. */ 339 * are running. */
@@ -264,18 +345,9 @@ static void omap2_clk_wait_ready(struct clk *clk)
264 omap2_wait_clock_ready(st_reg, bit, clk->name); 345 omap2_wait_clock_ready(st_reg, bit, clk->name);
265} 346}
266 347
267/* Enables clock without considering parent dependencies or use count 348static int omap2_dflt_clk_enable(struct clk *clk)
268 * REVISIT: Maybe change this to use clk->enable like on omap1?
269 */
270int _omap2_clk_enable(struct clk *clk)
271{ 349{
272 u32 regval32; 350 u32 v;
273
274 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
275 return 0;
276
277 if (clk->enable)
278 return clk->enable(clk);
279 351
280 if (unlikely(clk->enable_reg == NULL)) { 352 if (unlikely(clk->enable_reg == NULL)) {
281 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 353 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
@@ -283,33 +355,38 @@ int _omap2_clk_enable(struct clk *clk)
283 return 0; /* REVISIT: -EINVAL */ 355 return 0; /* REVISIT: -EINVAL */
284 } 356 }
285 357
286 regval32 = __raw_readl(clk->enable_reg); 358 v = __raw_readl(clk->enable_reg);
287 if (clk->flags & INVERT_ENABLE) 359 if (clk->flags & INVERT_ENABLE)
288 regval32 &= ~(1 << clk->enable_bit); 360 v &= ~(1 << clk->enable_bit);
289 else 361 else
290 regval32 |= (1 << clk->enable_bit); 362 v |= (1 << clk->enable_bit);
291 __raw_writel(regval32, clk->enable_reg); 363 __raw_writel(v, clk->enable_reg);
292 wmb(); 364 v = __raw_readl(clk->enable_reg); /* OCP barrier */
293
294 omap2_clk_wait_ready(clk);
295 365
296 return 0; 366 return 0;
297} 367}
298 368
299/* Disables clock without considering parent dependencies or use count */ 369static int omap2_dflt_clk_enable_wait(struct clk *clk)
300void _omap2_clk_disable(struct clk *clk)
301{ 370{
302 u32 regval32; 371 int ret;
303
304 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
305 return;
306 372
307 if (clk->disable) { 373 if (!clk->enable_reg) {
308 clk->disable(clk); 374 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
309 return; 375 clk->name);
376 return 0; /* REVISIT: -EINVAL */
310 } 377 }
311 378
312 if (clk->enable_reg == NULL) { 379 ret = omap2_dflt_clk_enable(clk);
380 if (ret == 0)
381 omap2_clk_wait_ready(clk);
382 return ret;
383}
384
385static void omap2_dflt_clk_disable(struct clk *clk)
386{
387 u32 v;
388
389 if (!clk->enable_reg) {
313 /* 390 /*
314 * 'Independent' here refers to a clock which is not 391 * 'Independent' here refers to a clock which is not
315 * controlled by its parent. 392 * controlled by its parent.
@@ -319,20 +396,44 @@ void _omap2_clk_disable(struct clk *clk)
319 return; 396 return;
320 } 397 }
321 398
322 regval32 = __raw_readl(clk->enable_reg); 399 v = __raw_readl(clk->enable_reg);
323 if (clk->flags & INVERT_ENABLE) 400 if (clk->flags & INVERT_ENABLE)
324 regval32 |= (1 << clk->enable_bit); 401 v |= (1 << clk->enable_bit);
325 else 402 else
326 regval32 &= ~(1 << clk->enable_bit); 403 v &= ~(1 << clk->enable_bit);
327 __raw_writel(regval32, clk->enable_reg); 404 __raw_writel(v, clk->enable_reg);
328 wmb(); 405 /* No OCP barrier needed here since it is a disable operation */
406}
407
408const struct clkops clkops_omap2_dflt_wait = {
409 .enable = omap2_dflt_clk_enable_wait,
410 .disable = omap2_dflt_clk_disable,
411};
412
413const struct clkops clkops_omap2_dflt = {
414 .enable = omap2_dflt_clk_enable,
415 .disable = omap2_dflt_clk_disable,
416};
417
418/* Enables clock without considering parent dependencies or use count
419 * REVISIT: Maybe change this to use clk->enable like on omap1?
420 */
421static int _omap2_clk_enable(struct clk *clk)
422{
423 return clk->ops->enable(clk);
424}
425
426/* Disables clock without considering parent dependencies or use count */
427static void _omap2_clk_disable(struct clk *clk)
428{
429 clk->ops->disable(clk);
329} 430}
330 431
331void omap2_clk_disable(struct clk *clk) 432void omap2_clk_disable(struct clk *clk)
332{ 433{
333 if (clk->usecount > 0 && !(--clk->usecount)) { 434 if (clk->usecount > 0 && !(--clk->usecount)) {
334 _omap2_clk_disable(clk); 435 _omap2_clk_disable(clk);
335 if (likely((u32)clk->parent)) 436 if (clk->parent)
336 omap2_clk_disable(clk->parent); 437 omap2_clk_disable(clk->parent);
337 if (clk->clkdm) 438 if (clk->clkdm)
338 omap2_clkdm_clk_disable(clk->clkdm, clk); 439 omap2_clkdm_clk_disable(clk->clkdm, clk);
@@ -345,30 +446,29 @@ int omap2_clk_enable(struct clk *clk)
345 int ret = 0; 446 int ret = 0;
346 447
347 if (clk->usecount++ == 0) { 448 if (clk->usecount++ == 0) {
348 if (likely((u32)clk->parent))
349 ret = omap2_clk_enable(clk->parent);
350
351 if (unlikely(ret != 0)) {
352 clk->usecount--;
353 return ret;
354 }
355
356 if (clk->clkdm) 449 if (clk->clkdm)
357 omap2_clkdm_clk_enable(clk->clkdm, clk); 450 omap2_clkdm_clk_enable(clk->clkdm, clk);
358 451
359 ret = _omap2_clk_enable(clk); 452 if (clk->parent) {
360 453 ret = omap2_clk_enable(clk->parent);
361 if (unlikely(ret != 0)) { 454 if (ret)
362 if (clk->clkdm) 455 goto err;
363 omap2_clkdm_clk_disable(clk->clkdm, clk); 456 }
364 457
365 if (clk->parent) { 458 ret = _omap2_clk_enable(clk);
459 if (ret) {
460 if (clk->parent)
366 omap2_clk_disable(clk->parent); 461 omap2_clk_disable(clk->parent);
367 clk->usecount--; 462
368 } 463 goto err;
369 } 464 }
370 } 465 }
466 return ret;
371 467
468err:
469 if (clk->clkdm)
470 omap2_clkdm_clk_disable(clk->clkdm, clk);
471 clk->usecount--;
372 return ret; 472 return ret;
373} 473}
374 474
@@ -376,24 +476,22 @@ int omap2_clk_enable(struct clk *clk)
376 * Used for clocks that are part of CLKSEL_xyz governed clocks. 476 * Used for clocks that are part of CLKSEL_xyz governed clocks.
377 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 477 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
378 */ 478 */
379void omap2_clksel_recalc(struct clk *clk) 479unsigned long omap2_clksel_recalc(struct clk *clk)
380{ 480{
481 unsigned long rate;
381 u32 div = 0; 482 u32 div = 0;
382 483
383 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 484 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
384 485
385 div = omap2_clksel_get_divisor(clk); 486 div = omap2_clksel_get_divisor(clk);
386 if (div == 0) 487 if (div == 0)
387 return; 488 return clk->rate;
388 489
389 if (unlikely(clk->rate == clk->parent->rate / div)) 490 rate = clk->parent->rate / div;
390 return;
391 clk->rate = clk->parent->rate / div;
392 491
393 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); 492 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
394 493
395 if (unlikely(clk->flags & RATE_PROPAGATES)) 494 return rate;
396 propagate_rate(clk);
397} 495}
398 496
399/** 497/**
@@ -405,8 +503,8 @@ void omap2_clksel_recalc(struct clk *clk)
405 * the element associated with the supplied parent clock address. 503 * the element associated with the supplied parent clock address.
406 * Returns a pointer to the struct clksel on success or NULL on error. 504 * Returns a pointer to the struct clksel on success or NULL on error.
407 */ 505 */
408const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 506static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
409 struct clk *src_clk) 507 struct clk *src_clk)
410{ 508{
411 const struct clksel *clks; 509 const struct clksel *clks;
412 510
@@ -455,7 +553,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
455 *new_div = 1; 553 *new_div = 1;
456 554
457 clks = omap2_get_clksel_by_parent(clk, clk->parent); 555 clks = omap2_get_clksel_by_parent(clk, clk->parent);
458 if (clks == NULL) 556 if (!clks)
459 return ~0; 557 return ~0;
460 558
461 for (clkr = clks->rates; clkr->div; clkr++) { 559 for (clkr = clks->rates; clkr->div; clkr++) {
@@ -514,7 +612,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
514/* Given a clock and a rate apply a clock specific rounding function */ 612/* Given a clock and a rate apply a clock specific rounding function */
515long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 613long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
516{ 614{
517 if (clk->round_rate != NULL) 615 if (clk->round_rate)
518 return clk->round_rate(clk, rate); 616 return clk->round_rate(clk, rate);
519 617
520 if (clk->flags & RATE_FIXED) 618 if (clk->flags & RATE_FIXED)
@@ -540,7 +638,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
540 const struct clksel_rate *clkr; 638 const struct clksel_rate *clkr;
541 639
542 clks = omap2_get_clksel_by_parent(clk, clk->parent); 640 clks = omap2_get_clksel_by_parent(clk, clk->parent);
543 if (clks == NULL) 641 if (!clks)
544 return 0; 642 return 0;
545 643
546 for (clkr = clks->rates; clkr->div; clkr++) { 644 for (clkr = clks->rates; clkr->div; clkr++) {
@@ -576,7 +674,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
576 WARN_ON(div == 0); 674 WARN_ON(div == 0);
577 675
578 clks = omap2_get_clksel_by_parent(clk, clk->parent); 676 clks = omap2_get_clksel_by_parent(clk, clk->parent);
579 if (clks == NULL) 677 if (!clks)
580 return ~0; 678 return ~0;
581 679
582 for (clkr = clks->rates; clkr->div; clkr++) { 680 for (clkr = clks->rates; clkr->div; clkr++) {
@@ -595,23 +693,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
595} 693}
596 694
597/** 695/**
598 * omap2_get_clksel - find clksel register addr & field mask for a clk
599 * @clk: struct clk to use
600 * @field_mask: ptr to u32 to store the register field mask
601 *
602 * Returns the address of the clksel register upon success or NULL on error.
603 */
604void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
605{
606 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
607 return NULL;
608
609 *field_mask = clk->clksel_mask;
610
611 return clk->clksel_reg;
612}
613
614/**
615 * omap2_clksel_get_divisor - get current divider applied to parent clock. 696 * omap2_clksel_get_divisor - get current divider applied to parent clock.
616 * @clk: OMAP struct clk to use. 697 * @clk: OMAP struct clk to use.
617 * 698 *
@@ -619,49 +700,41 @@ void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
619 */ 700 */
620u32 omap2_clksel_get_divisor(struct clk *clk) 701u32 omap2_clksel_get_divisor(struct clk *clk)
621{ 702{
622 u32 field_mask, field_val; 703 u32 v;
623 void __iomem *div_addr;
624 704
625 div_addr = omap2_get_clksel(clk, &field_mask); 705 if (!clk->clksel_mask)
626 if (div_addr == NULL)
627 return 0; 706 return 0;
628 707
629 field_val = __raw_readl(div_addr) & field_mask; 708 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
630 field_val >>= __ffs(field_mask); 709 v >>= __ffs(clk->clksel_mask);
631 710
632 return omap2_clksel_to_divisor(clk, field_val); 711 return omap2_clksel_to_divisor(clk, v);
633} 712}
634 713
635int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 714int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
636{ 715{
637 u32 field_mask, field_val, reg_val, validrate, new_div = 0; 716 u32 v, field_val, validrate, new_div = 0;
638 void __iomem *div_addr;
639 717
640 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 718 if (!clk->clksel_mask)
641 if (validrate != rate)
642 return -EINVAL; 719 return -EINVAL;
643 720
644 div_addr = omap2_get_clksel(clk, &field_mask); 721 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
645 if (div_addr == NULL) 722 if (validrate != rate)
646 return -EINVAL; 723 return -EINVAL;
647 724
648 field_val = omap2_divisor_to_clksel(clk, new_div); 725 field_val = omap2_divisor_to_clksel(clk, new_div);
649 if (field_val == ~0) 726 if (field_val == ~0)
650 return -EINVAL; 727 return -EINVAL;
651 728
652 reg_val = __raw_readl(div_addr); 729 v = __raw_readl(clk->clksel_reg);
653 reg_val &= ~field_mask; 730 v &= ~clk->clksel_mask;
654 reg_val |= (field_val << __ffs(field_mask)); 731 v |= field_val << __ffs(clk->clksel_mask);
655 __raw_writel(reg_val, div_addr); 732 __raw_writel(v, clk->clksel_reg);
656 wmb(); 733 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
657 734
658 clk->rate = clk->parent->rate / new_div; 735 clk->rate = clk->parent->rate / new_div;
659 736
660 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 737 _omap2xxx_clk_commit(clk);
661 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
662 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
663 wmb();
664 }
665 738
666 return 0; 739 return 0;
667} 740}
@@ -680,31 +753,24 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
680 return -EINVAL; 753 return -EINVAL;
681 754
682 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 755 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
683 if (clk->set_rate != NULL) 756 if (clk->set_rate)
684 ret = clk->set_rate(clk, rate); 757 ret = clk->set_rate(clk, rate);
685 758
686 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
687 propagate_rate(clk);
688
689 return ret; 759 return ret;
690} 760}
691 761
692/* 762/*
693 * Converts encoded control register address into a full address 763 * Converts encoded control register address into a full address
694 * On error, *src_addr will be returned as 0. 764 * On error, the return value (parent_div) will be 0.
695 */ 765 */
696static u32 omap2_clksel_get_src_field(void __iomem **src_addr, 766static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
697 struct clk *src_clk, u32 *field_mask, 767 u32 *field_val)
698 struct clk *clk, u32 *parent_div)
699{ 768{
700 const struct clksel *clks; 769 const struct clksel *clks;
701 const struct clksel_rate *clkr; 770 const struct clksel_rate *clkr;
702 771
703 *parent_div = 0;
704 *src_addr = NULL;
705
706 clks = omap2_get_clksel_by_parent(clk, src_clk); 772 clks = omap2_get_clksel_by_parent(clk, src_clk);
707 if (clks == NULL) 773 if (!clks)
708 return 0; 774 return 0;
709 775
710 for (clkr = clks->rates; clkr->div; clkr++) { 776 for (clkr = clks->rates; clkr->div; clkr++) {
@@ -722,47 +788,35 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
722 /* Should never happen. Add a clksel mask to the struct clk. */ 788 /* Should never happen. Add a clksel mask to the struct clk. */
723 WARN_ON(clk->clksel_mask == 0); 789 WARN_ON(clk->clksel_mask == 0);
724 790
725 *field_mask = clk->clksel_mask; 791 *field_val = clkr->val;
726 *src_addr = clk->clksel_reg;
727 *parent_div = clkr->div;
728 792
729 return clkr->val; 793 return clkr->div;
730} 794}
731 795
732int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 796int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
733{ 797{
734 void __iomem *src_addr; 798 u32 field_val, v, parent_div;
735 u32 field_val, field_mask, reg_val, parent_div;
736 799
737 if (unlikely(clk->flags & CONFIG_PARTICIPANT)) 800 if (clk->flags & CONFIG_PARTICIPANT)
738 return -EINVAL; 801 return -EINVAL;
739 802
740 if (!clk->clksel) 803 if (!clk->clksel)
741 return -EINVAL; 804 return -EINVAL;
742 805
743 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 806 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
744 &field_mask, clk, &parent_div); 807 if (!parent_div)
745 if (src_addr == NULL)
746 return -EINVAL; 808 return -EINVAL;
747 809
748 if (clk->usecount > 0)
749 omap2_clk_disable(clk);
750
751 /* Set new source value (previous dividers if any in effect) */ 810 /* Set new source value (previous dividers if any in effect) */
752 reg_val = __raw_readl(src_addr) & ~field_mask; 811 v = __raw_readl(clk->clksel_reg);
753 reg_val |= (field_val << __ffs(field_mask)); 812 v &= ~clk->clksel_mask;
754 __raw_writel(reg_val, src_addr); 813 v |= field_val << __ffs(clk->clksel_mask);
755 wmb(); 814 __raw_writel(v, clk->clksel_reg);
756 815 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
757 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
758 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
759 wmb();
760 }
761 816
762 clk->parent = new_parent; 817 _omap2xxx_clk_commit(clk);
763 818
764 if (clk->usecount > 0) 819 clk_reparent(clk, new_parent);
765 omap2_clk_enable(clk);
766 820
767 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 821 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
768 clk->rate = new_parent->rate; 822 clk->rate = new_parent->rate;
@@ -773,9 +827,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
773 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 827 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
774 clk->name, clk->parent->name, clk->rate); 828 clk->name, clk->parent->name, clk->rate);
775 829
776 if (unlikely(clk->flags & RATE_PROPAGATES))
777 propagate_rate(clk);
778
779 return 0; 830 return 0;
780} 831}
781 832
@@ -805,7 +856,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
805 return 0; 856 return 0;
806} 857}
807 858
808static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) 859static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
860 unsigned int m, unsigned int n)
809{ 861{
810 unsigned long long num; 862 unsigned long long num;
811 863
@@ -838,7 +890,7 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
838 unsigned long target_rate, 890 unsigned long target_rate,
839 unsigned long parent_rate) 891 unsigned long parent_rate)
840{ 892{
841 int flags = 0, carry = 0; 893 int r = 0, carry = 0;
842 894
843 /* Unscale m and round if necessary */ 895 /* Unscale m and round if necessary */
844 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 896 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
@@ -859,13 +911,13 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
859 if (*m < DPLL_MIN_MULTIPLIER) { 911 if (*m < DPLL_MIN_MULTIPLIER) {
860 *m = DPLL_MIN_MULTIPLIER; 912 *m = DPLL_MIN_MULTIPLIER;
861 *new_rate = 0; 913 *new_rate = 0;
862 flags = DPLL_MULT_UNDERFLOW; 914 r = DPLL_MULT_UNDERFLOW;
863 } 915 }
864 916
865 if (*new_rate == 0) 917 if (*new_rate == 0)
866 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 918 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
867 919
868 return flags; 920 return r;
869} 921}
870 922
871/** 923/**
@@ -889,54 +941,65 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
889 int m, n, r, e, scaled_max_m; 941 int m, n, r, e, scaled_max_m;
890 unsigned long scaled_rt_rp, new_rate; 942 unsigned long scaled_rt_rp, new_rate;
891 int min_e = -1, min_e_m = -1, min_e_n = -1; 943 int min_e = -1, min_e_m = -1, min_e_n = -1;
944 struct dpll_data *dd;
892 945
893 if (!clk || !clk->dpll_data) 946 if (!clk || !clk->dpll_data)
894 return ~0; 947 return ~0;
895 948
949 dd = clk->dpll_data;
950
896 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 951 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
897 "%ld\n", clk->name, target_rate); 952 "%ld\n", clk->name, target_rate);
898 953
899 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); 954 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
900 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; 955 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
901 956
902 clk->dpll_data->last_rounded_rate = 0; 957 dd->last_rounded_rate = 0;
903 958
904 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { 959 for (n = dd->min_divider; n <= dd->max_divider; n++) {
960
961 /* Is the (input clk, divider) pair valid for the DPLL? */
962 r = _dpll_test_fint(clk, n);
963 if (r == DPLL_FINT_UNDERFLOW)
964 break;
965 else if (r == DPLL_FINT_INVALID)
966 continue;
905 967
906 /* Compute the scaled DPLL multiplier, based on the divider */ 968 /* Compute the scaled DPLL multiplier, based on the divider */
907 m = scaled_rt_rp * n; 969 m = scaled_rt_rp * n;
908 970
909 /* 971 /*
910 * Since we're counting n down, a m overflow means we can 972 * Since we're counting n up, a m overflow means we
911 * can immediately skip to the next n 973 * can bail out completely (since as n increases in
974 * the next iteration, there's no way that m can
975 * increase beyond the current m)
912 */ 976 */
913 if (m > scaled_max_m) 977 if (m > scaled_max_m)
914 continue; 978 break;
915 979
916 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 980 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
917 clk->parent->rate); 981 dd->clk_ref->rate);
982
983 /* m can't be set low enough for this n - try with a larger n */
984 if (r == DPLL_MULT_UNDERFLOW)
985 continue;
918 986
919 e = target_rate - new_rate; 987 e = target_rate - new_rate;
920 pr_debug("clock: n = %d: m = %d: rate error is %d " 988 pr_debug("clock: n = %d: m = %d: rate error is %d "
921 "(new_rate = %ld)\n", n, m, e, new_rate); 989 "(new_rate = %ld)\n", n, m, e, new_rate);
922 990
923 if (min_e == -1 || 991 if (min_e == -1 ||
924 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { 992 min_e >= (int)(abs(e) - dd->rate_tolerance)) {
925 min_e = e; 993 min_e = e;
926 min_e_m = m; 994 min_e_m = m;
927 min_e_n = n; 995 min_e_n = n;
928 996
929 pr_debug("clock: found new least error %d\n", min_e); 997 pr_debug("clock: found new least error %d\n", min_e);
930 }
931 998
932 /* 999 /* We found good settings -- bail out now */
933 * Since we're counting n down, a m underflow means we 1000 if (min_e <= dd->rate_tolerance)
934 * can bail out completely (since as n decreases in 1001 break;
935 * the next iteration, there's no way that m can 1002 }
936 * increase beyond the current m)
937 */
938 if (r & DPLL_MULT_UNDERFLOW)
939 break;
940 } 1003 }
941 1004
942 if (min_e < 0) { 1005 if (min_e < 0) {
@@ -944,17 +1007,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
944 return ~0; 1007 return ~0;
945 } 1008 }
946 1009
947 clk->dpll_data->last_rounded_m = min_e_m; 1010 dd->last_rounded_m = min_e_m;
948 clk->dpll_data->last_rounded_n = min_e_n; 1011 dd->last_rounded_n = min_e_n;
949 clk->dpll_data->last_rounded_rate = 1012 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
950 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); 1013 min_e_m, min_e_n);
951 1014
952 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 1015 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
953 min_e, min_e_m, min_e_n); 1016 min_e, min_e_m, min_e_n);
954 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 1017 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
955 clk->dpll_data->last_rounded_rate, target_rate); 1018 dd->last_rounded_rate, target_rate);
956 1019
957 return clk->dpll_data->last_rounded_rate; 1020 return dd->last_rounded_rate;
958} 1021}
959 1022
960/*------------------------------------------------------------------------- 1023/*-------------------------------------------------------------------------
@@ -973,6 +1036,10 @@ void omap2_clk_disable_unused(struct clk *clk)
973 return; 1036 return;
974 1037
975 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 1038 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
976 _omap2_clk_disable(clk); 1039 if (cpu_is_omap34xx()) {
1040 omap2_clk_enable(clk);
1041 omap2_clk_disable(clk);
1042 } else
1043 _omap2_clk_disable(clk);
977} 1044}
978#endif 1045#endif
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 1fb330e0847d..2679ddfa6424 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,13 +21,28 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
25#define CORE_CLK_SRC_32K 0x0
26#define CORE_CLK_SRC_DPLL 0x1
27#define CORE_CLK_SRC_DPLL_X2 0x2
28
29/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
30#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
31#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
32#define OMAP2XXX_EN_DPLL_LOCKED 0x3
33
34/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
35#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38
24int omap2_clk_init(void); 39int omap2_clk_init(void);
25int omap2_clk_enable(struct clk *clk); 40int omap2_clk_enable(struct clk *clk);
26void omap2_clk_disable(struct clk *clk); 41void omap2_clk_disable(struct clk *clk);
27long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 42long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
28int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 43int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
29int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 44int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
30int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance); 45int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
31long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 46long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
32 47
33#ifdef CONFIG_OMAP_RESET_CLOCKS 48#ifdef CONFIG_OMAP_RESET_CLOCKS
@@ -36,7 +51,7 @@ void omap2_clk_disable_unused(struct clk *clk);
36#define omap2_clk_disable_unused NULL 51#define omap2_clk_disable_unused NULL
37#endif 52#endif
38 53
39void omap2_clksel_recalc(struct clk *clk); 54unsigned long omap2_clksel_recalc(struct clk *clk);
40void omap2_init_clk_clkdm(struct clk *clk); 55void omap2_init_clk_clkdm(struct clk *clk);
41void omap2_init_clksel_parent(struct clk *clk); 56void omap2_init_clksel_parent(struct clk *clk);
42u32 omap2_clksel_get_divisor(struct clk *clk); 57u32 omap2_clksel_get_divisor(struct clk *clk);
@@ -44,13 +59,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
44 u32 *new_div); 59 u32 *new_div);
45u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); 60u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
46u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); 61u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
47void omap2_fixed_divisor_recalc(struct clk *clk); 62unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
48long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); 63long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
49int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 64int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
50u32 omap2_get_dpll_rate(struct clk *clk); 65u32 omap2_get_dpll_rate(struct clk *clk);
51int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 66int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
52void omap2_clk_prepare_for_reboot(void); 67void omap2_clk_prepare_for_reboot(void);
53 68
69extern const struct clkops clkops_omap2_dflt_wait;
70extern const struct clkops clkops_omap2_dflt;
71
54extern u8 cpu_mask; 72extern u8 cpu_mask;
55 73
56/* clksel_rate data common to 24xx/343x */ 74/* clksel_rate data common to 24xx/343x */
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index d382eb0184ac..1e839c5a28c5 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -31,15 +31,192 @@
31#include <mach/clock.h> 31#include <mach/clock.h>
32#include <mach/sram.h> 32#include <mach/sram.h>
33#include <asm/div64.h> 33#include <asm/div64.h>
34#include <asm/clkdev.h>
34 35
35#include "memory.h" 36#include <mach/sdrc.h>
36#include "clock.h" 37#include "clock.h"
37#include "clock24xx.h"
38#include "prm.h" 38#include "prm.h"
39#include "prm-regbits-24xx.h" 39#include "prm-regbits-24xx.h"
40#include "cm.h" 40#include "cm.h"
41#include "cm-regbits-24xx.h" 41#include "cm-regbits-24xx.h"
42 42
43static const struct clkops clkops_oscck;
44static const struct clkops clkops_fixed;
45
46#include "clock24xx.h"
47
48struct omap_clk {
49 u32 cpu;
50 struct clk_lookup lk;
51};
52
53#define CLK(dev, con, ck, cp) \
54 { \
55 .cpu = cp, \
56 .lk = { \
57 .dev_id = dev, \
58 .con_id = con, \
59 .clk = ck, \
60 }, \
61 }
62
63#define CK_243X (1 << 0)
64#define CK_242X (1 << 1)
65
66static struct omap_clk omap24xx_clks[] = {
67 /* external root sources */
68 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
69 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
70 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
71 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
72 /* internal analog sources */
73 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
74 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
75 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
76 /* internal prcm root sources */
77 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
78 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
79 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
80 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
81 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
82 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
83 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
84 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
85 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
86 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
87 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
88 /* mpu domain clocks */
89 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
90 /* dsp domain clocks */
91 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
92 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
93 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
94 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
95 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
96 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
97 /* GFX domain clocks */
98 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
99 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
100 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
101 /* Modem domain clocks */
102 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
103 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
104 /* DSS domain clocks */
105 CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X),
106 CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X),
107 CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X),
108 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X),
109 /* L3 domain clocks */
110 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
111 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
112 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
113 /* L4 domain clocks */
114 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
115 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
116 /* virtual meta-group clock */
117 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
118 /* general l4 interface ck, multi-parent functional clk */
119 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
120 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
121 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
122 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
123 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
124 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
125 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
126 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
127 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
128 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
129 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
130 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
131 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
132 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
133 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
134 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
135 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
136 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
137 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
138 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
139 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
140 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
141 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
142 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
143 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
144 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
145 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
146 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
147 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
148 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
149 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
150 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
151 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
152 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
153 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
154 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
155 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
156 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
157 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
158 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
159 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
160 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
161 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
162 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
163 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
164 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
165 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
166 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
167 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
168 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
169 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
170 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
171 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
172 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
173 CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
174 CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
175 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
176 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
177 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
178 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
179 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
180 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
181 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
182 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
183 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
184 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
185 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
186 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
187 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
188 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
189 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
190 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
191 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
192 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
193 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
194 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
195 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
196 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
197 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
198 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
199 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
200 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
201 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
202 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
203 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
204 CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
205 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
206 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
207 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
208 CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
209 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
210 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
211 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
212 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
213 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
214 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
215 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
216 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
217 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
218};
219
43/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ 220/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
44#define EN_APLL_STOPPED 0 221#define EN_APLL_STOPPED 0
45#define EN_APLL_LOCKED 3 222#define EN_APLL_LOCKED 3
@@ -59,19 +236,32 @@ static struct clk *sclk;
59 * Omap24xx specific clock functions 236 * Omap24xx specific clock functions
60 *-------------------------------------------------------------------------*/ 237 *-------------------------------------------------------------------------*/
61 238
62/* This actually returns the rate of core_ck, not dpll_ck. */ 239/**
63static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) 240 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
241 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
242 *
243 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate
244 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
245 * (the latter is unusual). This currently should be called with
246 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
247 * core_ck.
248 */
249static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
64{ 250{
65 long long dpll_clk; 251 long long core_clk;
66 u8 amult; 252 u32 v;
253
254 core_clk = omap2_get_dpll_rate(clk);
67 255
68 dpll_clk = omap2_get_dpll_rate(tclk); 256 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
257 v &= OMAP24XX_CORE_CLK_SRC_MASK;
69 258
70 amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 259 if (v == CORE_CLK_SRC_32K)
71 amult &= OMAP24XX_CORE_CLK_SRC_MASK; 260 core_clk = 32768;
72 dpll_clk *= amult; 261 else
262 core_clk *= v;
73 263
74 return dpll_clk; 264 return core_clk;
75} 265}
76 266
77static int omap2_enable_osc_ck(struct clk *clk) 267static int omap2_enable_osc_ck(struct clk *clk)
@@ -96,6 +286,11 @@ static void omap2_disable_osc_ck(struct clk *clk)
96 OMAP24XX_PRCM_CLKSRC_CTRL); 286 OMAP24XX_PRCM_CLKSRC_CTRL);
97} 287}
98 288
289static const struct clkops clkops_oscck = {
290 .enable = &omap2_enable_osc_ck,
291 .disable = &omap2_disable_osc_ck,
292};
293
99#ifdef OLD_CK 294#ifdef OLD_CK
100/* Recalculate SYST_CLK */ 295/* Recalculate SYST_CLK */
101static void omap2_sys_clk_recalc(struct clk * clk) 296static void omap2_sys_clk_recalc(struct clk * clk)
@@ -149,11 +344,16 @@ static void omap2_clk_fixed_disable(struct clk *clk)
149 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 344 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
150} 345}
151 346
347static const struct clkops clkops_fixed = {
348 .enable = &omap2_clk_fixed_enable,
349 .disable = &omap2_clk_fixed_disable,
350};
351
152/* 352/*
153 * Uses the current prcm set to tell if a rate is valid. 353 * Uses the current prcm set to tell if a rate is valid.
154 * You can go slower, but not faster within a given rate set. 354 * You can go slower, but not faster within a given rate set.
155 */ 355 */
156long omap2_dpllcore_round_rate(unsigned long target_rate) 356static long omap2_dpllcore_round_rate(unsigned long target_rate)
157{ 357{
158 u32 high, low, core_clk_src; 358 u32 high, low, core_clk_src;
159 359
@@ -182,11 +382,9 @@ long omap2_dpllcore_round_rate(unsigned long target_rate)
182 382
183} 383}
184 384
185static void omap2_dpllcore_recalc(struct clk *clk) 385static unsigned long omap2_dpllcore_recalc(struct clk *clk)
186{ 386{
187 clk->rate = omap2_get_dpll_rate_24xx(clk); 387 return omap2xxx_clk_get_core_rate(clk);
188
189 propagate_rate(clk);
190} 388}
191 389
192static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 390static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
@@ -195,22 +393,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
195 u32 bypass = 0; 393 u32 bypass = 0;
196 struct prcm_config tmpset; 394 struct prcm_config tmpset;
197 const struct dpll_data *dd; 395 const struct dpll_data *dd;
198 unsigned long flags;
199 int ret = -EINVAL;
200 396
201 local_irq_save(flags); 397 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
202 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
203 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 398 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
204 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 399 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
205 400
206 if ((rate == (cur_rate / 2)) && (mult == 2)) { 401 if ((rate == (cur_rate / 2)) && (mult == 2)) {
207 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); 402 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
208 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 403 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
209 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 404 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
210 } else if (rate != cur_rate) { 405 } else if (rate != cur_rate) {
211 valid_rate = omap2_dpllcore_round_rate(rate); 406 valid_rate = omap2_dpllcore_round_rate(rate);
212 if (valid_rate != rate) 407 if (valid_rate != rate)
213 goto dpll_exit; 408 return -EINVAL;
214 409
215 if (mult == 1) 410 if (mult == 1)
216 low = curr_prcm_set->dpll_speed; 411 low = curr_prcm_set->dpll_speed;
@@ -219,7 +414,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
219 414
220 dd = clk->dpll_data; 415 dd = clk->dpll_data;
221 if (!dd) 416 if (!dd)
222 goto dpll_exit; 417 return -EINVAL;
223 418
224 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); 419 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
225 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 420 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
@@ -245,22 +440,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
245 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 440 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */
246 bypass = 1; 441 bypass = 1;
247 442
248 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ 443 /* For omap2xxx_sdrc_init_params() */
444 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
249 445
250 /* Force dll lock mode */ 446 /* Force dll lock mode */
251 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 447 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
252 bypass); 448 bypass);
253 449
254 /* Errata: ret dll entry state */ 450 /* Errata: ret dll entry state */
255 omap2_init_memory_params(omap2_dll_force_needed()); 451 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
256 omap2_reprogram_sdrc(done_rate, 0); 452 omap2xxx_sdrc_reprogram(done_rate, 0);
257 } 453 }
258 omap2_dpllcore_recalc(&dpll_ck);
259 ret = 0;
260 454
261dpll_exit: 455 return 0;
262 local_irq_restore(flags);
263 return(ret);
264} 456}
265 457
266/** 458/**
@@ -269,9 +461,9 @@ dpll_exit:
269 * 461 *
270 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. 462 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
271 */ 463 */
272static void omap2_table_mpu_recalc(struct clk *clk) 464static unsigned long omap2_table_mpu_recalc(struct clk *clk)
273{ 465{
274 clk->rate = curr_prcm_set->mpu_speed; 466 return curr_prcm_set->mpu_speed;
275} 467}
276 468
277/* 469/*
@@ -337,12 +529,12 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
337 } 529 }
338 530
339 curr_prcm_set = prcm; 531 curr_prcm_set = prcm;
340 cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); 532 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
341 533
342 if (prcm->dpll_speed == cur_rate / 2) { 534 if (prcm->dpll_speed == cur_rate / 2) {
343 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); 535 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
344 } else if (prcm->dpll_speed == cur_rate * 2) { 536 } else if (prcm->dpll_speed == cur_rate * 2) {
345 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 537 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
346 } else if (prcm->dpll_speed != cur_rate) { 538 } else if (prcm->dpll_speed != cur_rate) {
347 local_irq_save(flags); 539 local_irq_save(flags);
348 540
@@ -366,27 +558,67 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
366 558
367 /* Major subsystem dividers */ 559 /* Major subsystem dividers */
368 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; 560 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
369 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); 561 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
562 CM_CLKSEL1);
563
370 if (cpu_is_omap2430()) 564 if (cpu_is_omap2430())
371 cm_write_mod_reg(prcm->cm_clksel_mdm, 565 cm_write_mod_reg(prcm->cm_clksel_mdm,
372 OMAP2430_MDM_MOD, CM_CLKSEL); 566 OMAP2430_MDM_MOD, CM_CLKSEL);
373 567
374 /* x2 to enter init_mem */ 568 /* x2 to enter omap2xxx_sdrc_init_params() */
375 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 569 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
376 570
377 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, 571 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
378 bypass); 572 bypass);
379 573
380 omap2_init_memory_params(omap2_dll_force_needed()); 574 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
381 omap2_reprogram_sdrc(done_rate, 0); 575 omap2xxx_sdrc_reprogram(done_rate, 0);
382 576
383 local_irq_restore(flags); 577 local_irq_restore(flags);
384 } 578 }
385 omap2_dpllcore_recalc(&dpll_ck);
386 579
387 return 0; 580 return 0;
388} 581}
389 582
583#ifdef CONFIG_CPU_FREQ
584/*
585 * Walk PRCM rate table and fillout cpufreq freq_table
586 */
587static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
588
589void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
590{
591 struct prcm_config *prcm;
592 int i = 0;
593
594 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
595 if (!(prcm->flags & cpu_mask))
596 continue;
597 if (prcm->xtal_speed != sys_ck.rate)
598 continue;
599
600 /* don't put bypass rates in table */
601 if (prcm->dpll_speed == prcm->xtal_speed)
602 continue;
603
604 freq_table[i].index = i;
605 freq_table[i].frequency = prcm->mpu_speed / 1000;
606 i++;
607 }
608
609 if (i == 0) {
610 printk(KERN_WARNING "%s: failed to initialize frequency "
611 "table\n", __func__);
612 return;
613 }
614
615 freq_table[i].index = i;
616 freq_table[i].frequency = CPUFREQ_TABLE_END;
617
618 *table = &freq_table[0];
619}
620#endif
621
390static struct clk_functions omap2_clk_functions = { 622static struct clk_functions omap2_clk_functions = {
391 .clk_enable = omap2_clk_enable, 623 .clk_enable = omap2_clk_enable,
392 .clk_disable = omap2_clk_disable, 624 .clk_disable = omap2_clk_disable,
@@ -394,24 +626,27 @@ static struct clk_functions omap2_clk_functions = {
394 .clk_set_rate = omap2_clk_set_rate, 626 .clk_set_rate = omap2_clk_set_rate,
395 .clk_set_parent = omap2_clk_set_parent, 627 .clk_set_parent = omap2_clk_set_parent,
396 .clk_disable_unused = omap2_clk_disable_unused, 628 .clk_disable_unused = omap2_clk_disable_unused,
629#ifdef CONFIG_CPU_FREQ
630 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
631#endif
397}; 632};
398 633
399static u32 omap2_get_apll_clkin(void) 634static u32 omap2_get_apll_clkin(void)
400{ 635{
401 u32 aplls, sclk = 0; 636 u32 aplls, srate = 0;
402 637
403 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); 638 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
404 aplls &= OMAP24XX_APLLS_CLKIN_MASK; 639 aplls &= OMAP24XX_APLLS_CLKIN_MASK;
405 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; 640 aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
406 641
407 if (aplls == APLLS_CLKIN_19_2MHZ) 642 if (aplls == APLLS_CLKIN_19_2MHZ)
408 sclk = 19200000; 643 srate = 19200000;
409 else if (aplls == APLLS_CLKIN_13MHZ) 644 else if (aplls == APLLS_CLKIN_13MHZ)
410 sclk = 13000000; 645 srate = 13000000;
411 else if (aplls == APLLS_CLKIN_12MHZ) 646 else if (aplls == APLLS_CLKIN_12MHZ)
412 sclk = 12000000; 647 srate = 12000000;
413 648
414 return sclk; 649 return srate;
415} 650}
416 651
417static u32 omap2_get_sysclkdiv(void) 652static u32 omap2_get_sysclkdiv(void)
@@ -425,16 +660,14 @@ static u32 omap2_get_sysclkdiv(void)
425 return div; 660 return div;
426} 661}
427 662
428static void omap2_osc_clk_recalc(struct clk *clk) 663static unsigned long omap2_osc_clk_recalc(struct clk *clk)
429{ 664{
430 clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); 665 return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
431 propagate_rate(clk);
432} 666}
433 667
434static void omap2_sys_clk_recalc(struct clk *clk) 668static unsigned long omap2_sys_clk_recalc(struct clk *clk)
435{ 669{
436 clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); 670 return clk->parent->rate / omap2_get_sysclkdiv();
437 propagate_rate(clk);
438} 671}
439 672
440/* 673/*
@@ -460,7 +693,7 @@ static int __init omap2_clk_arch_init(void)
460 if (!mpurate) 693 if (!mpurate)
461 return -EINVAL; 694 return -EINVAL;
462 695
463 if (omap2_select_table_rate(&virt_prcm_set, mpurate)) 696 if (clk_set_rate(&virt_prcm_set, mpurate))
464 printk(KERN_ERR "Could not find matching MPU rate\n"); 697 printk(KERN_ERR "Could not find matching MPU rate\n");
465 698
466 recalculate_root_clocks(); 699 recalculate_root_clocks();
@@ -477,8 +710,8 @@ arch_initcall(omap2_clk_arch_init);
477int __init omap2_clk_init(void) 710int __init omap2_clk_init(void)
478{ 711{
479 struct prcm_config *prcm; 712 struct prcm_config *prcm;
480 struct clk **clkp; 713 struct omap_clk *c;
481 u32 clkrate; 714 u32 clkrate, cpu_mask;
482 715
483 if (cpu_is_omap242x()) 716 if (cpu_is_omap242x())
484 cpu_mask = RATE_IN_242X; 717 cpu_mask = RATE_IN_242X;
@@ -487,26 +720,28 @@ int __init omap2_clk_init(void)
487 720
488 clk_init(&omap2_clk_functions); 721 clk_init(&omap2_clk_functions);
489 722
490 omap2_osc_clk_recalc(&osc_ck); 723 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
491 omap2_sys_clk_recalc(&sys_ck); 724 propagate_rate(&osc_ck);
725 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
726 propagate_rate(&sys_ck);
492 727
493 for (clkp = onchip_24xx_clks; 728 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
494 clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); 729 clk_init_one(c->lk.clk);
495 clkp++) {
496 730
497 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { 731 cpu_mask = 0;
498 clk_register(*clkp); 732 if (cpu_is_omap2420())
499 continue; 733 cpu_mask |= CK_242X;
500 } 734 if (cpu_is_omap2430())
735 cpu_mask |= CK_243X;
501 736
502 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { 737 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
503 clk_register(*clkp); 738 if (c->cpu & cpu_mask) {
504 continue; 739 clkdev_add(&c->lk);
740 clk_register(c->lk.clk);
505 } 741 }
506 }
507 742
508 /* Check the MPU rate set by bootloader */ 743 /* Check the MPU rate set by bootloader */
509 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); 744 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
510 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 745 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
511 if (!(prcm->flags & cpu_mask)) 746 if (!(prcm->flags & cpu_mask))
512 continue; 747 continue;
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index ad6d98d177c5..33c3e5b14323 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -24,17 +24,13 @@
24#include "cm-regbits-24xx.h" 24#include "cm-regbits-24xx.h"
25#include "sdrc.h" 25#include "sdrc.h"
26 26
27static void omap2_table_mpu_recalc(struct clk *clk); 27static unsigned long omap2_table_mpu_recalc(struct clk *clk);
28static int omap2_select_table_rate(struct clk *clk, unsigned long rate); 28static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); 29static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static unsigned long omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static unsigned long omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static unsigned long omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpllcore_recalc(struct clk *clk); 33static unsigned long omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); 34static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 35
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 36/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
@@ -623,41 +619,35 @@ static struct prcm_config rate_table[] = {
623/* Base external input clocks */ 619/* Base external input clocks */
624static struct clk func_32k_ck = { 620static struct clk func_32k_ck = {
625 .name = "func_32k_ck", 621 .name = "func_32k_ck",
622 .ops = &clkops_null,
626 .rate = 32000, 623 .rate = 32000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 624 .flags = RATE_FIXED,
628 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
629 .clkdm_name = "wkup_clkdm", 625 .clkdm_name = "wkup_clkdm",
630 .recalc = &propagate_rate,
631}; 626};
632 627
633/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ 628/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
634static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ 629static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
635 .name = "osc_ck", 630 .name = "osc_ck",
636 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 631 .ops = &clkops_oscck,
637 RATE_PROPAGATES,
638 .clkdm_name = "wkup_clkdm", 632 .clkdm_name = "wkup_clkdm",
639 .enable = &omap2_enable_osc_ck,
640 .disable = &omap2_disable_osc_ck,
641 .recalc = &omap2_osc_clk_recalc, 633 .recalc = &omap2_osc_clk_recalc,
642}; 634};
643 635
644/* Without modem likely 12MHz, with modem likely 13MHz */ 636/* Without modem likely 12MHz, with modem likely 13MHz */
645static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 637static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
646 .name = "sys_ck", /* ~ ref_clk also */ 638 .name = "sys_ck", /* ~ ref_clk also */
639 .ops = &clkops_null,
647 .parent = &osc_ck, 640 .parent = &osc_ck,
648 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
649 ALWAYS_ENABLED | RATE_PROPAGATES,
650 .clkdm_name = "wkup_clkdm", 641 .clkdm_name = "wkup_clkdm",
651 .recalc = &omap2_sys_clk_recalc, 642 .recalc = &omap2_sys_clk_recalc,
652}; 643};
653 644
654static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 645static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
655 .name = "alt_ck", 646 .name = "alt_ck",
647 .ops = &clkops_null,
656 .rate = 54000000, 648 .rate = 54000000,
657 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 649 .flags = RATE_FIXED,
658 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
659 .clkdm_name = "wkup_clkdm", 650 .clkdm_name = "wkup_clkdm",
660 .recalc = &propagate_rate,
661}; 651};
662 652
663/* 653/*
@@ -673,7 +663,12 @@ static struct dpll_data dpll_dd = {
673 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 663 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
674 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 664 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
675 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 665 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
666 .clk_bypass = &sys_ck,
667 .clk_ref = &sys_ck,
668 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
669 .enable_mask = OMAP24XX_EN_DPLL_MASK,
676 .max_multiplier = 1024, 670 .max_multiplier = 1024,
671 .min_divider = 1,
677 .max_divider = 16, 672 .max_divider = 16,
678 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 673 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
679}; 674};
@@ -684,10 +679,9 @@ static struct dpll_data dpll_dd = {
684 */ 679 */
685static struct clk dpll_ck = { 680static struct clk dpll_ck = {
686 .name = "dpll_ck", 681 .name = "dpll_ck",
682 .ops = &clkops_null,
687 .parent = &sys_ck, /* Can be func_32k also */ 683 .parent = &sys_ck, /* Can be func_32k also */
688 .dpll_data = &dpll_dd, 684 .dpll_data = &dpll_dd,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
690 RATE_PROPAGATES | ALWAYS_ENABLED,
691 .clkdm_name = "wkup_clkdm", 685 .clkdm_name = "wkup_clkdm",
692 .recalc = &omap2_dpllcore_recalc, 686 .recalc = &omap2_dpllcore_recalc,
693 .set_rate = &omap2_reprogram_dpllcore, 687 .set_rate = &omap2_reprogram_dpllcore,
@@ -695,30 +689,24 @@ static struct clk dpll_ck = {
695 689
696static struct clk apll96_ck = { 690static struct clk apll96_ck = {
697 .name = "apll96_ck", 691 .name = "apll96_ck",
692 .ops = &clkops_fixed,
698 .parent = &sys_ck, 693 .parent = &sys_ck,
699 .rate = 96000000, 694 .rate = 96000000,
700 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 695 .flags = RATE_FIXED | ENABLE_ON_INIT,
701 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
702 .clkdm_name = "wkup_clkdm", 696 .clkdm_name = "wkup_clkdm",
703 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
704 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, 698 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
705 .enable = &omap2_clk_fixed_enable,
706 .disable = &omap2_clk_fixed_disable,
707 .recalc = &propagate_rate,
708}; 699};
709 700
710static struct clk apll54_ck = { 701static struct clk apll54_ck = {
711 .name = "apll54_ck", 702 .name = "apll54_ck",
703 .ops = &clkops_fixed,
712 .parent = &sys_ck, 704 .parent = &sys_ck,
713 .rate = 54000000, 705 .rate = 54000000,
714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 706 .flags = RATE_FIXED | ENABLE_ON_INIT,
715 RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
716 .clkdm_name = "wkup_clkdm", 707 .clkdm_name = "wkup_clkdm",
717 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 708 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
718 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, 709 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
719 .enable = &omap2_clk_fixed_enable,
720 .disable = &omap2_clk_fixed_disable,
721 .recalc = &propagate_rate,
722}; 710};
723 711
724/* 712/*
@@ -745,9 +733,8 @@ static const struct clksel func_54m_clksel[] = {
745 733
746static struct clk func_54m_ck = { 734static struct clk func_54m_ck = {
747 .name = "func_54m_ck", 735 .name = "func_54m_ck",
736 .ops = &clkops_null,
748 .parent = &apll54_ck, /* can also be alt_clk */ 737 .parent = &apll54_ck, /* can also be alt_clk */
749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
750 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
751 .clkdm_name = "wkup_clkdm", 738 .clkdm_name = "wkup_clkdm",
752 .init = &omap2_init_clksel_parent, 739 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -758,9 +745,8 @@ static struct clk func_54m_ck = {
758 745
759static struct clk core_ck = { 746static struct clk core_ck = {
760 .name = "core_ck", 747 .name = "core_ck",
748 .ops = &clkops_null,
761 .parent = &dpll_ck, /* can also be 32k */ 749 .parent = &dpll_ck, /* can also be 32k */
762 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
763 ALWAYS_ENABLED | RATE_PROPAGATES,
764 .clkdm_name = "wkup_clkdm", 750 .clkdm_name = "wkup_clkdm",
765 .recalc = &followparent_recalc, 751 .recalc = &followparent_recalc,
766}; 752};
@@ -785,9 +771,8 @@ static const struct clksel func_96m_clksel[] = {
785/* The parent of this clock is not selectable on 2420. */ 771/* The parent of this clock is not selectable on 2420. */
786static struct clk func_96m_ck = { 772static struct clk func_96m_ck = {
787 .name = "func_96m_ck", 773 .name = "func_96m_ck",
774 .ops = &clkops_null,
788 .parent = &apll96_ck, 775 .parent = &apll96_ck,
789 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
790 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
791 .clkdm_name = "wkup_clkdm", 776 .clkdm_name = "wkup_clkdm",
792 .init = &omap2_init_clksel_parent, 777 .init = &omap2_init_clksel_parent,
793 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 778 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -818,9 +803,8 @@ static const struct clksel func_48m_clksel[] = {
818 803
819static struct clk func_48m_ck = { 804static struct clk func_48m_ck = {
820 .name = "func_48m_ck", 805 .name = "func_48m_ck",
806 .ops = &clkops_null,
821 .parent = &apll96_ck, /* 96M or Alt */ 807 .parent = &apll96_ck, /* 96M or Alt */
822 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
823 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
824 .clkdm_name = "wkup_clkdm", 808 .clkdm_name = "wkup_clkdm",
825 .init = &omap2_init_clksel_parent, 809 .init = &omap2_init_clksel_parent,
826 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 810 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -833,10 +817,9 @@ static struct clk func_48m_ck = {
833 817
834static struct clk func_12m_ck = { 818static struct clk func_12m_ck = {
835 .name = "func_12m_ck", 819 .name = "func_12m_ck",
820 .ops = &clkops_null,
836 .parent = &func_48m_ck, 821 .parent = &func_48m_ck,
837 .fixed_div = 4, 822 .fixed_div = 4,
838 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
839 RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
840 .clkdm_name = "wkup_clkdm", 823 .clkdm_name = "wkup_clkdm",
841 .recalc = &omap2_fixed_divisor_recalc, 824 .recalc = &omap2_fixed_divisor_recalc,
842}; 825};
@@ -844,8 +827,8 @@ static struct clk func_12m_ck = {
844/* Secure timer, only available in secure mode */ 827/* Secure timer, only available in secure mode */
845static struct clk wdt1_osc_ck = { 828static struct clk wdt1_osc_ck = {
846 .name = "ck_wdt1_osc", 829 .name = "ck_wdt1_osc",
830 .ops = &clkops_null, /* RMK: missing? */
847 .parent = &osc_ck, 831 .parent = &osc_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
849 .recalc = &followparent_recalc, 832 .recalc = &followparent_recalc,
850}; 833};
851 834
@@ -887,9 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = {
887 870
888static struct clk sys_clkout_src = { 871static struct clk sys_clkout_src = {
889 .name = "sys_clkout_src", 872 .name = "sys_clkout_src",
873 .ops = &clkops_omap2_dflt,
890 .parent = &func_54m_ck, 874 .parent = &func_54m_ck,
891 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
892 RATE_PROPAGATES,
893 .clkdm_name = "wkup_clkdm", 875 .clkdm_name = "wkup_clkdm",
894 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 876 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
895 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, 877 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
@@ -918,9 +900,8 @@ static const struct clksel sys_clkout_clksel[] = {
918 900
919static struct clk sys_clkout = { 901static struct clk sys_clkout = {
920 .name = "sys_clkout", 902 .name = "sys_clkout",
903 .ops = &clkops_null,
921 .parent = &sys_clkout_src, 904 .parent = &sys_clkout_src,
922 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
923 PARENT_CONTROLS_CLOCK,
924 .clkdm_name = "wkup_clkdm", 905 .clkdm_name = "wkup_clkdm",
925 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 906 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
926 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, 907 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
@@ -933,8 +914,8 @@ static struct clk sys_clkout = {
933/* In 2430, new in 2420 ES2 */ 914/* In 2430, new in 2420 ES2 */
934static struct clk sys_clkout2_src = { 915static struct clk sys_clkout2_src = {
935 .name = "sys_clkout2_src", 916 .name = "sys_clkout2_src",
917 .ops = &clkops_omap2_dflt,
936 .parent = &func_54m_ck, 918 .parent = &func_54m_ck,
937 .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES,
938 .clkdm_name = "wkup_clkdm", 919 .clkdm_name = "wkup_clkdm",
939 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 920 .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
940 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, 921 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
@@ -955,8 +936,8 @@ static const struct clksel sys_clkout2_clksel[] = {
955/* In 2430, new in 2420 ES2 */ 936/* In 2430, new in 2420 ES2 */
956static struct clk sys_clkout2 = { 937static struct clk sys_clkout2 = {
957 .name = "sys_clkout2", 938 .name = "sys_clkout2",
939 .ops = &clkops_null,
958 .parent = &sys_clkout2_src, 940 .parent = &sys_clkout2_src,
959 .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK,
960 .clkdm_name = "wkup_clkdm", 941 .clkdm_name = "wkup_clkdm",
961 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, 942 .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL,
962 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, 943 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
@@ -968,8 +949,8 @@ static struct clk sys_clkout2 = {
968 949
969static struct clk emul_ck = { 950static struct clk emul_ck = {
970 .name = "emul_ck", 951 .name = "emul_ck",
952 .ops = &clkops_omap2_dflt,
971 .parent = &func_54m_ck, 953 .parent = &func_54m_ck,
972 .flags = CLOCK_IN_OMAP242X,
973 .clkdm_name = "wkup_clkdm", 954 .clkdm_name = "wkup_clkdm",
974 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, 955 .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL,
975 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, 956 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
@@ -1003,10 +984,9 @@ static const struct clksel mpu_clksel[] = {
1003 984
1004static struct clk mpu_ck = { /* Control cpu */ 985static struct clk mpu_ck = { /* Control cpu */
1005 .name = "mpu_ck", 986 .name = "mpu_ck",
987 .ops = &clkops_null,
1006 .parent = &core_ck, 988 .parent = &core_ck,
1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 989 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1008 ALWAYS_ENABLED | DELAYED_APP |
1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1010 .clkdm_name = "mpu_clkdm", 990 .clkdm_name = "mpu_clkdm",
1011 .init = &omap2_init_clksel_parent, 991 .init = &omap2_init_clksel_parent,
1012 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 992 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -1046,9 +1026,9 @@ static const struct clksel dsp_fck_clksel[] = {
1046 1026
1047static struct clk dsp_fck = { 1027static struct clk dsp_fck = {
1048 .name = "dsp_fck", 1028 .name = "dsp_fck",
1029 .ops = &clkops_omap2_dflt_wait,
1049 .parent = &core_ck, 1030 .parent = &core_ck,
1050 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1031 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1051 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1052 .clkdm_name = "dsp_clkdm", 1032 .clkdm_name = "dsp_clkdm",
1053 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1033 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1034 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -1076,9 +1056,9 @@ static const struct clksel dsp_irate_ick_clksel[] = {
1076/* This clock does not exist as such in the TRM. */ 1056/* This clock does not exist as such in the TRM. */
1077static struct clk dsp_irate_ick = { 1057static struct clk dsp_irate_ick = {
1078 .name = "dsp_irate_ick", 1058 .name = "dsp_irate_ick",
1059 .ops = &clkops_null,
1079 .parent = &dsp_fck, 1060 .parent = &dsp_fck,
1080 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | 1061 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1081 CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK,
1082 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 1062 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1083 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 1063 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
1084 .clksel = dsp_irate_ick_clksel, 1064 .clksel = dsp_irate_ick_clksel,
@@ -1090,8 +1070,9 @@ static struct clk dsp_irate_ick = {
1090/* 2420 only */ 1070/* 2420 only */
1091static struct clk dsp_ick = { 1071static struct clk dsp_ick = {
1092 .name = "dsp_ick", /* apparently ipi and isp */ 1072 .name = "dsp_ick", /* apparently ipi and isp */
1073 .ops = &clkops_omap2_dflt_wait,
1093 .parent = &dsp_irate_ick, 1074 .parent = &dsp_irate_ick,
1094 .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, 1075 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), 1076 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
1096 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ 1077 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
1097}; 1078};
@@ -1099,8 +1080,9 @@ static struct clk dsp_ick = {
1099/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ 1080/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
1100static struct clk iva2_1_ick = { 1081static struct clk iva2_1_ick = {
1101 .name = "iva2_1_ick", 1082 .name = "iva2_1_ick",
1083 .ops = &clkops_omap2_dflt_wait,
1102 .parent = &dsp_irate_ick, 1084 .parent = &dsp_irate_ick,
1103 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1085 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1104 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1086 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1105 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 1087 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
1106}; 1088};
@@ -1112,9 +1094,9 @@ static struct clk iva2_1_ick = {
1112 */ 1094 */
1113static struct clk iva1_ifck = { 1095static struct clk iva1_ifck = {
1114 .name = "iva1_ifck", 1096 .name = "iva1_ifck",
1097 .ops = &clkops_omap2_dflt_wait,
1115 .parent = &core_ck, 1098 .parent = &core_ck,
1116 .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | 1099 .flags = CONFIG_PARTICIPANT | DELAYED_APP,
1117 RATE_PROPAGATES | DELAYED_APP,
1118 .clkdm_name = "iva1_clkdm", 1100 .clkdm_name = "iva1_clkdm",
1119 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1101 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1120 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 1102 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
@@ -1129,8 +1111,8 @@ static struct clk iva1_ifck = {
1129/* IVA1 mpu/int/i/f clocks are /2 of parent */ 1111/* IVA1 mpu/int/i/f clocks are /2 of parent */
1130static struct clk iva1_mpu_int_ifck = { 1112static struct clk iva1_mpu_int_ifck = {
1131 .name = "iva1_mpu_int_ifck", 1113 .name = "iva1_mpu_int_ifck",
1114 .ops = &clkops_omap2_dflt_wait,
1132 .parent = &iva1_ifck, 1115 .parent = &iva1_ifck,
1133 .flags = CLOCK_IN_OMAP242X,
1134 .clkdm_name = "iva1_clkdm", 1116 .clkdm_name = "iva1_clkdm",
1135 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 1117 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1136 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, 1118 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
@@ -1175,10 +1157,9 @@ static const struct clksel core_l3_clksel[] = {
1175 1157
1176static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1158static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1177 .name = "core_l3_ck", 1159 .name = "core_l3_ck",
1160 .ops = &clkops_null,
1178 .parent = &core_ck, 1161 .parent = &core_ck,
1179 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1162 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1180 ALWAYS_ENABLED | DELAYED_APP |
1181 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1182 .clkdm_name = "core_l3_clkdm", 1163 .clkdm_name = "core_l3_clkdm",
1183 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1164 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1184 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 1165 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -1204,9 +1185,9 @@ static const struct clksel usb_l4_ick_clksel[] = {
1204/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 1185/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
1205static struct clk usb_l4_ick = { /* FS-USB interface clock */ 1186static struct clk usb_l4_ick = { /* FS-USB interface clock */
1206 .name = "usb_l4_ick", 1187 .name = "usb_l4_ick",
1188 .ops = &clkops_omap2_dflt_wait,
1207 .parent = &core_l3_ck, 1189 .parent = &core_l3_ck,
1208 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1190 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1209 DELAYED_APP | CONFIG_PARTICIPANT,
1210 .clkdm_name = "core_l4_clkdm", 1191 .clkdm_name = "core_l4_clkdm",
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1212 .enable_bit = OMAP24XX_EN_USB_SHIFT, 1193 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -1238,9 +1219,9 @@ static const struct clksel l4_clksel[] = {
1238 1219
1239static struct clk l4_ck = { /* used both as an ick and fck */ 1220static struct clk l4_ck = { /* used both as an ick and fck */
1240 .name = "l4_ck", 1221 .name = "l4_ck",
1222 .ops = &clkops_null,
1241 .parent = &core_l3_ck, 1223 .parent = &core_l3_ck,
1242 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1224 .flags = DELAYED_APP,
1243 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
1244 .clkdm_name = "core_l4_clkdm", 1225 .clkdm_name = "core_l4_clkdm",
1245 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1226 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1246 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1227 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
@@ -1276,9 +1257,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1276 1257
1277static struct clk ssi_ssr_sst_fck = { 1258static struct clk ssi_ssr_sst_fck = {
1278 .name = "ssi_fck", 1259 .name = "ssi_fck",
1260 .ops = &clkops_omap2_dflt_wait,
1279 .parent = &core_ck, 1261 .parent = &core_ck,
1280 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1262 .flags = DELAYED_APP,
1281 DELAYED_APP,
1282 .clkdm_name = "core_l3_clkdm", 1263 .clkdm_name = "core_l3_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 1265 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -1290,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = {
1290 .set_rate = &omap2_clksel_set_rate 1271 .set_rate = &omap2_clksel_set_rate
1291}; 1272};
1292 1273
1274/*
1275 * Presumably this is the same as SSI_ICLK.
1276 * TRM contradicts itself on what clockdomain SSI_ICLK is in
1277 */
1278static struct clk ssi_l4_ick = {
1279 .name = "ssi_l4_ick",
1280 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &l4_ck,
1282 .clkdm_name = "core_l4_clkdm",
1283 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1284 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1285 .recalc = &followparent_recalc,
1286};
1287
1293 1288
1294/* 1289/*
1295 * GFX clock domain 1290 * GFX clock domain
@@ -1312,8 +1307,8 @@ static const struct clksel gfx_fck_clksel[] = {
1312 1307
1313static struct clk gfx_3d_fck = { 1308static struct clk gfx_3d_fck = {
1314 .name = "gfx_3d_fck", 1309 .name = "gfx_3d_fck",
1310 .ops = &clkops_omap2_dflt_wait,
1315 .parent = &core_l3_ck, 1311 .parent = &core_l3_ck,
1316 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1317 .clkdm_name = "gfx_clkdm", 1312 .clkdm_name = "gfx_clkdm",
1318 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1313 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1319 .enable_bit = OMAP24XX_EN_3D_SHIFT, 1314 .enable_bit = OMAP24XX_EN_3D_SHIFT,
@@ -1327,8 +1322,8 @@ static struct clk gfx_3d_fck = {
1327 1322
1328static struct clk gfx_2d_fck = { 1323static struct clk gfx_2d_fck = {
1329 .name = "gfx_2d_fck", 1324 .name = "gfx_2d_fck",
1325 .ops = &clkops_omap2_dflt_wait,
1330 .parent = &core_l3_ck, 1326 .parent = &core_l3_ck,
1331 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1332 .clkdm_name = "gfx_clkdm", 1327 .clkdm_name = "gfx_clkdm",
1333 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1328 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334 .enable_bit = OMAP24XX_EN_2D_SHIFT, 1329 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -1342,8 +1337,8 @@ static struct clk gfx_2d_fck = {
1342 1337
1343static struct clk gfx_ick = { 1338static struct clk gfx_ick = {
1344 .name = "gfx_ick", /* From l3 */ 1339 .name = "gfx_ick", /* From l3 */
1340 .ops = &clkops_omap2_dflt_wait,
1345 .parent = &core_l3_ck, 1341 .parent = &core_l3_ck,
1346 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1347 .clkdm_name = "gfx_clkdm", 1342 .clkdm_name = "gfx_clkdm",
1348 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1343 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1349 .enable_bit = OMAP_EN_GFX_SHIFT, 1344 .enable_bit = OMAP_EN_GFX_SHIFT,
@@ -1372,8 +1367,9 @@ static const struct clksel mdm_ick_clksel[] = {
1372 1367
1373static struct clk mdm_ick = { /* used both as a ick and fck */ 1368static struct clk mdm_ick = { /* used both as a ick and fck */
1374 .name = "mdm_ick", 1369 .name = "mdm_ick",
1370 .ops = &clkops_omap2_dflt_wait,
1375 .parent = &core_ck, 1371 .parent = &core_ck,
1376 .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, 1372 .flags = DELAYED_APP | CONFIG_PARTICIPANT,
1377 .clkdm_name = "mdm_clkdm", 1373 .clkdm_name = "mdm_clkdm",
1378 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 1374 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1379 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 1375 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -1387,8 +1383,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
1387 1383
1388static struct clk mdm_osc_ck = { 1384static struct clk mdm_osc_ck = {
1389 .name = "mdm_osc_ck", 1385 .name = "mdm_osc_ck",
1386 .ops = &clkops_omap2_dflt_wait,
1390 .parent = &osc_ck, 1387 .parent = &osc_ck,
1391 .flags = CLOCK_IN_OMAP243X,
1392 .clkdm_name = "mdm_clkdm", 1388 .clkdm_name = "mdm_clkdm",
1393 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 1389 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1394 .enable_bit = OMAP2430_EN_OSC_SHIFT, 1390 .enable_bit = OMAP2430_EN_OSC_SHIFT,
@@ -1432,8 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = {
1432 1428
1433static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 1429static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1434 .name = "dss_ick", 1430 .name = "dss_ick",
1431 .ops = &clkops_omap2_dflt,
1435 .parent = &l4_ck, /* really both l3 and l4 */ 1432 .parent = &l4_ck, /* really both l3 and l4 */
1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .clkdm_name = "dss_clkdm", 1433 .clkdm_name = "dss_clkdm",
1438 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1434 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1439 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1435 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1442,9 +1438,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
1442 1438
1443static struct clk dss1_fck = { 1439static struct clk dss1_fck = {
1444 .name = "dss1_fck", 1440 .name = "dss1_fck",
1441 .ops = &clkops_omap2_dflt,
1445 .parent = &core_ck, /* Core or sys */ 1442 .parent = &core_ck, /* Core or sys */
1446 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1443 .flags = DELAYED_APP,
1447 DELAYED_APP,
1448 .clkdm_name = "dss_clkdm", 1444 .clkdm_name = "dss_clkdm",
1449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1445 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1450 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 1446 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -1475,9 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = {
1475 1471
1476static struct clk dss2_fck = { /* Alt clk used in power management */ 1472static struct clk dss2_fck = { /* Alt clk used in power management */
1477 .name = "dss2_fck", 1473 .name = "dss2_fck",
1474 .ops = &clkops_omap2_dflt,
1478 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 1475 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1479 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1476 .flags = DELAYED_APP,
1480 DELAYED_APP,
1481 .clkdm_name = "dss_clkdm", 1477 .clkdm_name = "dss_clkdm",
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 1479 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1490,8 +1486,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
1490 1486
1491static struct clk dss_54m_fck = { /* Alt clk used in power management */ 1487static struct clk dss_54m_fck = { /* Alt clk used in power management */
1492 .name = "dss_54m_fck", /* 54m tv clk */ 1488 .name = "dss_54m_fck", /* 54m tv clk */
1489 .ops = &clkops_omap2_dflt_wait,
1493 .parent = &func_54m_ck, 1490 .parent = &func_54m_ck,
1494 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1495 .clkdm_name = "dss_clkdm", 1491 .clkdm_name = "dss_clkdm",
1496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1497 .enable_bit = OMAP24XX_EN_TV_SHIFT, 1493 .enable_bit = OMAP24XX_EN_TV_SHIFT,
@@ -1518,8 +1514,8 @@ static const struct clksel omap24xx_gpt_clksel[] = {
1518 1514
1519static struct clk gpt1_ick = { 1515static struct clk gpt1_ick = {
1520 .name = "gpt1_ick", 1516 .name = "gpt1_ick",
1517 .ops = &clkops_omap2_dflt_wait,
1521 .parent = &l4_ck, 1518 .parent = &l4_ck,
1522 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1523 .clkdm_name = "core_l4_clkdm", 1519 .clkdm_name = "core_l4_clkdm",
1524 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1520 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1525 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1521 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1528,8 +1524,8 @@ static struct clk gpt1_ick = {
1528 1524
1529static struct clk gpt1_fck = { 1525static struct clk gpt1_fck = {
1530 .name = "gpt1_fck", 1526 .name = "gpt1_fck",
1527 .ops = &clkops_omap2_dflt_wait,
1531 .parent = &func_32k_ck, 1528 .parent = &func_32k_ck,
1532 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1533 .clkdm_name = "core_l4_clkdm", 1529 .clkdm_name = "core_l4_clkdm",
1534 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 1530 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1535 .enable_bit = OMAP24XX_EN_GPT1_SHIFT, 1531 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
@@ -1544,8 +1540,8 @@ static struct clk gpt1_fck = {
1544 1540
1545static struct clk gpt2_ick = { 1541static struct clk gpt2_ick = {
1546 .name = "gpt2_ick", 1542 .name = "gpt2_ick",
1543 .ops = &clkops_omap2_dflt_wait,
1547 .parent = &l4_ck, 1544 .parent = &l4_ck,
1548 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1549 .clkdm_name = "core_l4_clkdm", 1545 .clkdm_name = "core_l4_clkdm",
1550 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1546 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1551 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1547 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1554,8 +1550,8 @@ static struct clk gpt2_ick = {
1554 1550
1555static struct clk gpt2_fck = { 1551static struct clk gpt2_fck = {
1556 .name = "gpt2_fck", 1552 .name = "gpt2_fck",
1553 .ops = &clkops_omap2_dflt_wait,
1557 .parent = &func_32k_ck, 1554 .parent = &func_32k_ck,
1558 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1559 .clkdm_name = "core_l4_clkdm", 1555 .clkdm_name = "core_l4_clkdm",
1560 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1561 .enable_bit = OMAP24XX_EN_GPT2_SHIFT, 1557 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
@@ -1568,8 +1564,8 @@ static struct clk gpt2_fck = {
1568 1564
1569static struct clk gpt3_ick = { 1565static struct clk gpt3_ick = {
1570 .name = "gpt3_ick", 1566 .name = "gpt3_ick",
1567 .ops = &clkops_omap2_dflt_wait,
1571 .parent = &l4_ck, 1568 .parent = &l4_ck,
1572 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1573 .clkdm_name = "core_l4_clkdm", 1569 .clkdm_name = "core_l4_clkdm",
1574 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1575 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1571 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1578,8 +1574,8 @@ static struct clk gpt3_ick = {
1578 1574
1579static struct clk gpt3_fck = { 1575static struct clk gpt3_fck = {
1580 .name = "gpt3_fck", 1576 .name = "gpt3_fck",
1577 .ops = &clkops_omap2_dflt_wait,
1581 .parent = &func_32k_ck, 1578 .parent = &func_32k_ck,
1582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1583 .clkdm_name = "core_l4_clkdm", 1579 .clkdm_name = "core_l4_clkdm",
1584 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1585 .enable_bit = OMAP24XX_EN_GPT3_SHIFT, 1581 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
@@ -1592,8 +1588,8 @@ static struct clk gpt3_fck = {
1592 1588
1593static struct clk gpt4_ick = { 1589static struct clk gpt4_ick = {
1594 .name = "gpt4_ick", 1590 .name = "gpt4_ick",
1591 .ops = &clkops_omap2_dflt_wait,
1595 .parent = &l4_ck, 1592 .parent = &l4_ck,
1596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1597 .clkdm_name = "core_l4_clkdm", 1593 .clkdm_name = "core_l4_clkdm",
1598 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1599 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1595 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1602,8 +1598,8 @@ static struct clk gpt4_ick = {
1602 1598
1603static struct clk gpt4_fck = { 1599static struct clk gpt4_fck = {
1604 .name = "gpt4_fck", 1600 .name = "gpt4_fck",
1601 .ops = &clkops_omap2_dflt_wait,
1605 .parent = &func_32k_ck, 1602 .parent = &func_32k_ck,
1606 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1607 .clkdm_name = "core_l4_clkdm", 1603 .clkdm_name = "core_l4_clkdm",
1608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1604 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1609 .enable_bit = OMAP24XX_EN_GPT4_SHIFT, 1605 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
@@ -1616,8 +1612,8 @@ static struct clk gpt4_fck = {
1616 1612
1617static struct clk gpt5_ick = { 1613static struct clk gpt5_ick = {
1618 .name = "gpt5_ick", 1614 .name = "gpt5_ick",
1615 .ops = &clkops_omap2_dflt_wait,
1619 .parent = &l4_ck, 1616 .parent = &l4_ck,
1620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1621 .clkdm_name = "core_l4_clkdm", 1617 .clkdm_name = "core_l4_clkdm",
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1618 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1623 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1619 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1626,8 +1622,8 @@ static struct clk gpt5_ick = {
1626 1622
1627static struct clk gpt5_fck = { 1623static struct clk gpt5_fck = {
1628 .name = "gpt5_fck", 1624 .name = "gpt5_fck",
1625 .ops = &clkops_omap2_dflt_wait,
1629 .parent = &func_32k_ck, 1626 .parent = &func_32k_ck,
1630 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1631 .clkdm_name = "core_l4_clkdm", 1627 .clkdm_name = "core_l4_clkdm",
1632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1628 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1633 .enable_bit = OMAP24XX_EN_GPT5_SHIFT, 1629 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
@@ -1640,8 +1636,8 @@ static struct clk gpt5_fck = {
1640 1636
1641static struct clk gpt6_ick = { 1637static struct clk gpt6_ick = {
1642 .name = "gpt6_ick", 1638 .name = "gpt6_ick",
1639 .ops = &clkops_omap2_dflt_wait,
1643 .parent = &l4_ck, 1640 .parent = &l4_ck,
1644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1645 .clkdm_name = "core_l4_clkdm", 1641 .clkdm_name = "core_l4_clkdm",
1646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1642 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1647 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1643 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1650,8 +1646,8 @@ static struct clk gpt6_ick = {
1650 1646
1651static struct clk gpt6_fck = { 1647static struct clk gpt6_fck = {
1652 .name = "gpt6_fck", 1648 .name = "gpt6_fck",
1649 .ops = &clkops_omap2_dflt_wait,
1653 .parent = &func_32k_ck, 1650 .parent = &func_32k_ck,
1654 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1655 .clkdm_name = "core_l4_clkdm", 1651 .clkdm_name = "core_l4_clkdm",
1656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1657 .enable_bit = OMAP24XX_EN_GPT6_SHIFT, 1653 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
@@ -1664,8 +1660,8 @@ static struct clk gpt6_fck = {
1664 1660
1665static struct clk gpt7_ick = { 1661static struct clk gpt7_ick = {
1666 .name = "gpt7_ick", 1662 .name = "gpt7_ick",
1663 .ops = &clkops_omap2_dflt_wait,
1667 .parent = &l4_ck, 1664 .parent = &l4_ck,
1668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1669 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1670 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1666 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1671 .recalc = &followparent_recalc, 1667 .recalc = &followparent_recalc,
@@ -1673,8 +1669,8 @@ static struct clk gpt7_ick = {
1673 1669
1674static struct clk gpt7_fck = { 1670static struct clk gpt7_fck = {
1675 .name = "gpt7_fck", 1671 .name = "gpt7_fck",
1672 .ops = &clkops_omap2_dflt_wait,
1676 .parent = &func_32k_ck, 1673 .parent = &func_32k_ck,
1677 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1678 .clkdm_name = "core_l4_clkdm", 1674 .clkdm_name = "core_l4_clkdm",
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1680 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 1676 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1687,8 +1683,8 @@ static struct clk gpt7_fck = {
1687 1683
1688static struct clk gpt8_ick = { 1684static struct clk gpt8_ick = {
1689 .name = "gpt8_ick", 1685 .name = "gpt8_ick",
1686 .ops = &clkops_omap2_dflt_wait,
1690 .parent = &l4_ck, 1687 .parent = &l4_ck,
1691 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1692 .clkdm_name = "core_l4_clkdm", 1688 .clkdm_name = "core_l4_clkdm",
1693 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1694 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1690 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1697,8 +1693,8 @@ static struct clk gpt8_ick = {
1697 1693
1698static struct clk gpt8_fck = { 1694static struct clk gpt8_fck = {
1699 .name = "gpt8_fck", 1695 .name = "gpt8_fck",
1696 .ops = &clkops_omap2_dflt_wait,
1700 .parent = &func_32k_ck, 1697 .parent = &func_32k_ck,
1701 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1702 .clkdm_name = "core_l4_clkdm", 1698 .clkdm_name = "core_l4_clkdm",
1703 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1699 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1704 .enable_bit = OMAP24XX_EN_GPT8_SHIFT, 1700 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
@@ -1711,8 +1707,8 @@ static struct clk gpt8_fck = {
1711 1707
1712static struct clk gpt9_ick = { 1708static struct clk gpt9_ick = {
1713 .name = "gpt9_ick", 1709 .name = "gpt9_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &l4_ck, 1711 .parent = &l4_ck,
1715 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1716 .clkdm_name = "core_l4_clkdm", 1712 .clkdm_name = "core_l4_clkdm",
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1713 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1714 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1721,8 +1717,8 @@ static struct clk gpt9_ick = {
1721 1717
1722static struct clk gpt9_fck = { 1718static struct clk gpt9_fck = {
1723 .name = "gpt9_fck", 1719 .name = "gpt9_fck",
1720 .ops = &clkops_omap2_dflt_wait,
1724 .parent = &func_32k_ck, 1721 .parent = &func_32k_ck,
1725 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1726 .clkdm_name = "core_l4_clkdm", 1722 .clkdm_name = "core_l4_clkdm",
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1723 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1728 .enable_bit = OMAP24XX_EN_GPT9_SHIFT, 1724 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
@@ -1735,8 +1731,8 @@ static struct clk gpt9_fck = {
1735 1731
1736static struct clk gpt10_ick = { 1732static struct clk gpt10_ick = {
1737 .name = "gpt10_ick", 1733 .name = "gpt10_ick",
1734 .ops = &clkops_omap2_dflt_wait,
1738 .parent = &l4_ck, 1735 .parent = &l4_ck,
1739 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1740 .clkdm_name = "core_l4_clkdm", 1736 .clkdm_name = "core_l4_clkdm",
1741 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1742 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1738 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1745,8 +1741,8 @@ static struct clk gpt10_ick = {
1745 1741
1746static struct clk gpt10_fck = { 1742static struct clk gpt10_fck = {
1747 .name = "gpt10_fck", 1743 .name = "gpt10_fck",
1744 .ops = &clkops_omap2_dflt_wait,
1748 .parent = &func_32k_ck, 1745 .parent = &func_32k_ck,
1749 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1750 .clkdm_name = "core_l4_clkdm", 1746 .clkdm_name = "core_l4_clkdm",
1751 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1752 .enable_bit = OMAP24XX_EN_GPT10_SHIFT, 1748 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
@@ -1759,8 +1755,8 @@ static struct clk gpt10_fck = {
1759 1755
1760static struct clk gpt11_ick = { 1756static struct clk gpt11_ick = {
1761 .name = "gpt11_ick", 1757 .name = "gpt11_ick",
1758 .ops = &clkops_omap2_dflt_wait,
1762 .parent = &l4_ck, 1759 .parent = &l4_ck,
1763 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1764 .clkdm_name = "core_l4_clkdm", 1760 .clkdm_name = "core_l4_clkdm",
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1762 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1769,8 +1765,8 @@ static struct clk gpt11_ick = {
1769 1765
1770static struct clk gpt11_fck = { 1766static struct clk gpt11_fck = {
1771 .name = "gpt11_fck", 1767 .name = "gpt11_fck",
1768 .ops = &clkops_omap2_dflt_wait,
1772 .parent = &func_32k_ck, 1769 .parent = &func_32k_ck,
1773 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1774 .clkdm_name = "core_l4_clkdm", 1770 .clkdm_name = "core_l4_clkdm",
1775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1776 .enable_bit = OMAP24XX_EN_GPT11_SHIFT, 1772 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
@@ -1783,8 +1779,8 @@ static struct clk gpt11_fck = {
1783 1779
1784static struct clk gpt12_ick = { 1780static struct clk gpt12_ick = {
1785 .name = "gpt12_ick", 1781 .name = "gpt12_ick",
1782 .ops = &clkops_omap2_dflt_wait,
1786 .parent = &l4_ck, 1783 .parent = &l4_ck,
1787 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1788 .clkdm_name = "core_l4_clkdm", 1784 .clkdm_name = "core_l4_clkdm",
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1790 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1786 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1793,8 +1789,8 @@ static struct clk gpt12_ick = {
1793 1789
1794static struct clk gpt12_fck = { 1790static struct clk gpt12_fck = {
1795 .name = "gpt12_fck", 1791 .name = "gpt12_fck",
1792 .ops = &clkops_omap2_dflt_wait,
1796 .parent = &func_32k_ck, 1793 .parent = &func_32k_ck,
1797 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1798 .clkdm_name = "core_l4_clkdm", 1794 .clkdm_name = "core_l4_clkdm",
1799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1800 .enable_bit = OMAP24XX_EN_GPT12_SHIFT, 1796 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
@@ -1807,9 +1803,9 @@ static struct clk gpt12_fck = {
1807 1803
1808static struct clk mcbsp1_ick = { 1804static struct clk mcbsp1_ick = {
1809 .name = "mcbsp_ick", 1805 .name = "mcbsp_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1810 .id = 1, 1807 .id = 1,
1811 .parent = &l4_ck, 1808 .parent = &l4_ck,
1812 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1813 .clkdm_name = "core_l4_clkdm", 1809 .clkdm_name = "core_l4_clkdm",
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1811 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1818,9 +1814,9 @@ static struct clk mcbsp1_ick = {
1818 1814
1819static struct clk mcbsp1_fck = { 1815static struct clk mcbsp1_fck = {
1820 .name = "mcbsp_fck", 1816 .name = "mcbsp_fck",
1817 .ops = &clkops_omap2_dflt_wait,
1821 .id = 1, 1818 .id = 1,
1822 .parent = &func_96m_ck, 1819 .parent = &func_96m_ck,
1823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1824 .clkdm_name = "core_l4_clkdm", 1820 .clkdm_name = "core_l4_clkdm",
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1826 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, 1822 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
@@ -1829,9 +1825,9 @@ static struct clk mcbsp1_fck = {
1829 1825
1830static struct clk mcbsp2_ick = { 1826static struct clk mcbsp2_ick = {
1831 .name = "mcbsp_ick", 1827 .name = "mcbsp_ick",
1828 .ops = &clkops_omap2_dflt_wait,
1832 .id = 2, 1829 .id = 2,
1833 .parent = &l4_ck, 1830 .parent = &l4_ck,
1834 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1835 .clkdm_name = "core_l4_clkdm", 1831 .clkdm_name = "core_l4_clkdm",
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1833 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1840,9 +1836,9 @@ static struct clk mcbsp2_ick = {
1840 1836
1841static struct clk mcbsp2_fck = { 1837static struct clk mcbsp2_fck = {
1842 .name = "mcbsp_fck", 1838 .name = "mcbsp_fck",
1839 .ops = &clkops_omap2_dflt_wait,
1843 .id = 2, 1840 .id = 2,
1844 .parent = &func_96m_ck, 1841 .parent = &func_96m_ck,
1845 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1846 .clkdm_name = "core_l4_clkdm", 1842 .clkdm_name = "core_l4_clkdm",
1847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1843 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1848 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, 1844 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
@@ -1851,9 +1847,9 @@ static struct clk mcbsp2_fck = {
1851 1847
1852static struct clk mcbsp3_ick = { 1848static struct clk mcbsp3_ick = {
1853 .name = "mcbsp_ick", 1849 .name = "mcbsp_ick",
1850 .ops = &clkops_omap2_dflt_wait,
1854 .id = 3, 1851 .id = 3,
1855 .parent = &l4_ck, 1852 .parent = &l4_ck,
1856 .flags = CLOCK_IN_OMAP243X,
1857 .clkdm_name = "core_l4_clkdm", 1853 .clkdm_name = "core_l4_clkdm",
1858 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1854 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1859 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1855 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1862,9 +1858,9 @@ static struct clk mcbsp3_ick = {
1862 1858
1863static struct clk mcbsp3_fck = { 1859static struct clk mcbsp3_fck = {
1864 .name = "mcbsp_fck", 1860 .name = "mcbsp_fck",
1861 .ops = &clkops_omap2_dflt_wait,
1865 .id = 3, 1862 .id = 3,
1866 .parent = &func_96m_ck, 1863 .parent = &func_96m_ck,
1867 .flags = CLOCK_IN_OMAP243X,
1868 .clkdm_name = "core_l4_clkdm", 1864 .clkdm_name = "core_l4_clkdm",
1869 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1870 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, 1866 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
@@ -1873,9 +1869,9 @@ static struct clk mcbsp3_fck = {
1873 1869
1874static struct clk mcbsp4_ick = { 1870static struct clk mcbsp4_ick = {
1875 .name = "mcbsp_ick", 1871 .name = "mcbsp_ick",
1872 .ops = &clkops_omap2_dflt_wait,
1876 .id = 4, 1873 .id = 4,
1877 .parent = &l4_ck, 1874 .parent = &l4_ck,
1878 .flags = CLOCK_IN_OMAP243X,
1879 .clkdm_name = "core_l4_clkdm", 1875 .clkdm_name = "core_l4_clkdm",
1880 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1881 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1877 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1884,9 +1880,9 @@ static struct clk mcbsp4_ick = {
1884 1880
1885static struct clk mcbsp4_fck = { 1881static struct clk mcbsp4_fck = {
1886 .name = "mcbsp_fck", 1882 .name = "mcbsp_fck",
1883 .ops = &clkops_omap2_dflt_wait,
1887 .id = 4, 1884 .id = 4,
1888 .parent = &func_96m_ck, 1885 .parent = &func_96m_ck,
1889 .flags = CLOCK_IN_OMAP243X,
1890 .clkdm_name = "core_l4_clkdm", 1886 .clkdm_name = "core_l4_clkdm",
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1887 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1892 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, 1888 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
@@ -1895,9 +1891,9 @@ static struct clk mcbsp4_fck = {
1895 1891
1896static struct clk mcbsp5_ick = { 1892static struct clk mcbsp5_ick = {
1897 .name = "mcbsp_ick", 1893 .name = "mcbsp_ick",
1894 .ops = &clkops_omap2_dflt_wait,
1898 .id = 5, 1895 .id = 5,
1899 .parent = &l4_ck, 1896 .parent = &l4_ck,
1900 .flags = CLOCK_IN_OMAP243X,
1901 .clkdm_name = "core_l4_clkdm", 1897 .clkdm_name = "core_l4_clkdm",
1902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1903 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1899 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1906,9 +1902,9 @@ static struct clk mcbsp5_ick = {
1906 1902
1907static struct clk mcbsp5_fck = { 1903static struct clk mcbsp5_fck = {
1908 .name = "mcbsp_fck", 1904 .name = "mcbsp_fck",
1905 .ops = &clkops_omap2_dflt_wait,
1909 .id = 5, 1906 .id = 5,
1910 .parent = &func_96m_ck, 1907 .parent = &func_96m_ck,
1911 .flags = CLOCK_IN_OMAP243X,
1912 .clkdm_name = "core_l4_clkdm", 1908 .clkdm_name = "core_l4_clkdm",
1913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1909 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1914 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, 1910 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
@@ -1917,10 +1913,10 @@ static struct clk mcbsp5_fck = {
1917 1913
1918static struct clk mcspi1_ick = { 1914static struct clk mcspi1_ick = {
1919 .name = "mcspi_ick", 1915 .name = "mcspi_ick",
1916 .ops = &clkops_omap2_dflt_wait,
1920 .id = 1, 1917 .id = 1,
1921 .parent = &l4_ck, 1918 .parent = &l4_ck,
1922 .clkdm_name = "core_l4_clkdm", 1919 .clkdm_name = "core_l4_clkdm",
1923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1924 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1920 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1925 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1921 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1926 .recalc = &followparent_recalc, 1922 .recalc = &followparent_recalc,
@@ -1928,9 +1924,9 @@ static struct clk mcspi1_ick = {
1928 1924
1929static struct clk mcspi1_fck = { 1925static struct clk mcspi1_fck = {
1930 .name = "mcspi_fck", 1926 .name = "mcspi_fck",
1927 .ops = &clkops_omap2_dflt_wait,
1931 .id = 1, 1928 .id = 1,
1932 .parent = &func_48m_ck, 1929 .parent = &func_48m_ck,
1933 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1934 .clkdm_name = "core_l4_clkdm", 1930 .clkdm_name = "core_l4_clkdm",
1935 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1936 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, 1932 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1939,9 +1935,9 @@ static struct clk mcspi1_fck = {
1939 1935
1940static struct clk mcspi2_ick = { 1936static struct clk mcspi2_ick = {
1941 .name = "mcspi_ick", 1937 .name = "mcspi_ick",
1938 .ops = &clkops_omap2_dflt_wait,
1942 .id = 2, 1939 .id = 2,
1943 .parent = &l4_ck, 1940 .parent = &l4_ck,
1944 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1945 .clkdm_name = "core_l4_clkdm", 1941 .clkdm_name = "core_l4_clkdm",
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1942 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1943 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1950,9 +1946,9 @@ static struct clk mcspi2_ick = {
1950 1946
1951static struct clk mcspi2_fck = { 1947static struct clk mcspi2_fck = {
1952 .name = "mcspi_fck", 1948 .name = "mcspi_fck",
1949 .ops = &clkops_omap2_dflt_wait,
1953 .id = 2, 1950 .id = 2,
1954 .parent = &func_48m_ck, 1951 .parent = &func_48m_ck,
1955 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1956 .clkdm_name = "core_l4_clkdm", 1952 .clkdm_name = "core_l4_clkdm",
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1958 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, 1954 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
@@ -1961,9 +1957,9 @@ static struct clk mcspi2_fck = {
1961 1957
1962static struct clk mcspi3_ick = { 1958static struct clk mcspi3_ick = {
1963 .name = "mcspi_ick", 1959 .name = "mcspi_ick",
1960 .ops = &clkops_omap2_dflt_wait,
1964 .id = 3, 1961 .id = 3,
1965 .parent = &l4_ck, 1962 .parent = &l4_ck,
1966 .flags = CLOCK_IN_OMAP243X,
1967 .clkdm_name = "core_l4_clkdm", 1963 .clkdm_name = "core_l4_clkdm",
1968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1969 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1965 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1972,9 +1968,9 @@ static struct clk mcspi3_ick = {
1972 1968
1973static struct clk mcspi3_fck = { 1969static struct clk mcspi3_fck = {
1974 .name = "mcspi_fck", 1970 .name = "mcspi_fck",
1971 .ops = &clkops_omap2_dflt_wait,
1975 .id = 3, 1972 .id = 3,
1976 .parent = &func_48m_ck, 1973 .parent = &func_48m_ck,
1977 .flags = CLOCK_IN_OMAP243X,
1978 .clkdm_name = "core_l4_clkdm", 1974 .clkdm_name = "core_l4_clkdm",
1979 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1975 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1980 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, 1976 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
@@ -1983,8 +1979,8 @@ static struct clk mcspi3_fck = {
1983 1979
1984static struct clk uart1_ick = { 1980static struct clk uart1_ick = {
1985 .name = "uart1_ick", 1981 .name = "uart1_ick",
1982 .ops = &clkops_omap2_dflt_wait,
1986 .parent = &l4_ck, 1983 .parent = &l4_ck,
1987 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1988 .clkdm_name = "core_l4_clkdm", 1984 .clkdm_name = "core_l4_clkdm",
1989 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1986 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -1993,8 +1989,8 @@ static struct clk uart1_ick = {
1993 1989
1994static struct clk uart1_fck = { 1990static struct clk uart1_fck = {
1995 .name = "uart1_fck", 1991 .name = "uart1_fck",
1992 .ops = &clkops_omap2_dflt_wait,
1996 .parent = &func_48m_ck, 1993 .parent = &func_48m_ck,
1997 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1998 .clkdm_name = "core_l4_clkdm", 1994 .clkdm_name = "core_l4_clkdm",
1999 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1995 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2000 .enable_bit = OMAP24XX_EN_UART1_SHIFT, 1996 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
@@ -2003,8 +1999,8 @@ static struct clk uart1_fck = {
2003 1999
2004static struct clk uart2_ick = { 2000static struct clk uart2_ick = {
2005 .name = "uart2_ick", 2001 .name = "uart2_ick",
2002 .ops = &clkops_omap2_dflt_wait,
2006 .parent = &l4_ck, 2003 .parent = &l4_ck,
2007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2008 .clkdm_name = "core_l4_clkdm", 2004 .clkdm_name = "core_l4_clkdm",
2009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2005 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2006 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2013,8 +2009,8 @@ static struct clk uart2_ick = {
2013 2009
2014static struct clk uart2_fck = { 2010static struct clk uart2_fck = {
2015 .name = "uart2_fck", 2011 .name = "uart2_fck",
2012 .ops = &clkops_omap2_dflt_wait,
2016 .parent = &func_48m_ck, 2013 .parent = &func_48m_ck,
2017 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2018 .clkdm_name = "core_l4_clkdm", 2014 .clkdm_name = "core_l4_clkdm",
2019 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2020 .enable_bit = OMAP24XX_EN_UART2_SHIFT, 2016 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
@@ -2023,8 +2019,8 @@ static struct clk uart2_fck = {
2023 2019
2024static struct clk uart3_ick = { 2020static struct clk uart3_ick = {
2025 .name = "uart3_ick", 2021 .name = "uart3_ick",
2022 .ops = &clkops_omap2_dflt_wait,
2026 .parent = &l4_ck, 2023 .parent = &l4_ck,
2027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2028 .clkdm_name = "core_l4_clkdm", 2024 .clkdm_name = "core_l4_clkdm",
2029 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2025 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2030 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2026 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2033,8 +2029,8 @@ static struct clk uart3_ick = {
2033 2029
2034static struct clk uart3_fck = { 2030static struct clk uart3_fck = {
2035 .name = "uart3_fck", 2031 .name = "uart3_fck",
2032 .ops = &clkops_omap2_dflt_wait,
2036 .parent = &func_48m_ck, 2033 .parent = &func_48m_ck,
2037 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2038 .clkdm_name = "core_l4_clkdm", 2034 .clkdm_name = "core_l4_clkdm",
2039 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2035 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2040 .enable_bit = OMAP24XX_EN_UART3_SHIFT, 2036 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
@@ -2043,8 +2039,8 @@ static struct clk uart3_fck = {
2043 2039
2044static struct clk gpios_ick = { 2040static struct clk gpios_ick = {
2045 .name = "gpios_ick", 2041 .name = "gpios_ick",
2042 .ops = &clkops_omap2_dflt_wait,
2046 .parent = &l4_ck, 2043 .parent = &l4_ck,
2047 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2048 .clkdm_name = "core_l4_clkdm", 2044 .clkdm_name = "core_l4_clkdm",
2049 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2045 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2050 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2046 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2053,8 +2049,8 @@ static struct clk gpios_ick = {
2053 2049
2054static struct clk gpios_fck = { 2050static struct clk gpios_fck = {
2055 .name = "gpios_fck", 2051 .name = "gpios_fck",
2052 .ops = &clkops_omap2_dflt_wait,
2056 .parent = &func_32k_ck, 2053 .parent = &func_32k_ck,
2057 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2058 .clkdm_name = "wkup_clkdm", 2054 .clkdm_name = "wkup_clkdm",
2059 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2055 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2060 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, 2056 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
@@ -2063,8 +2059,8 @@ static struct clk gpios_fck = {
2063 2059
2064static struct clk mpu_wdt_ick = { 2060static struct clk mpu_wdt_ick = {
2065 .name = "mpu_wdt_ick", 2061 .name = "mpu_wdt_ick",
2062 .ops = &clkops_omap2_dflt_wait,
2066 .parent = &l4_ck, 2063 .parent = &l4_ck,
2067 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2068 .clkdm_name = "core_l4_clkdm", 2064 .clkdm_name = "core_l4_clkdm",
2069 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2065 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2066 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2073,8 +2069,8 @@ static struct clk mpu_wdt_ick = {
2073 2069
2074static struct clk mpu_wdt_fck = { 2070static struct clk mpu_wdt_fck = {
2075 .name = "mpu_wdt_fck", 2071 .name = "mpu_wdt_fck",
2072 .ops = &clkops_omap2_dflt_wait,
2076 .parent = &func_32k_ck, 2073 .parent = &func_32k_ck,
2077 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2078 .clkdm_name = "wkup_clkdm", 2074 .clkdm_name = "wkup_clkdm",
2079 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2075 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2080 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 2076 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
@@ -2083,9 +2079,9 @@ static struct clk mpu_wdt_fck = {
2083 2079
2084static struct clk sync_32k_ick = { 2080static struct clk sync_32k_ick = {
2085 .name = "sync_32k_ick", 2081 .name = "sync_32k_ick",
2082 .ops = &clkops_omap2_dflt_wait,
2086 .parent = &l4_ck, 2083 .parent = &l4_ck,
2087 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2084 .flags = ENABLE_ON_INIT,
2088 ENABLE_ON_INIT,
2089 .clkdm_name = "core_l4_clkdm", 2085 .clkdm_name = "core_l4_clkdm",
2090 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2086 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2091 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, 2087 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
@@ -2094,8 +2090,8 @@ static struct clk sync_32k_ick = {
2094 2090
2095static struct clk wdt1_ick = { 2091static struct clk wdt1_ick = {
2096 .name = "wdt1_ick", 2092 .name = "wdt1_ick",
2093 .ops = &clkops_omap2_dflt_wait,
2097 .parent = &l4_ck, 2094 .parent = &l4_ck,
2098 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2099 .clkdm_name = "core_l4_clkdm", 2095 .clkdm_name = "core_l4_clkdm",
2100 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2096 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2101 .enable_bit = OMAP24XX_EN_WDT1_SHIFT, 2097 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
@@ -2104,9 +2100,9 @@ static struct clk wdt1_ick = {
2104 2100
2105static struct clk omapctrl_ick = { 2101static struct clk omapctrl_ick = {
2106 .name = "omapctrl_ick", 2102 .name = "omapctrl_ick",
2103 .ops = &clkops_omap2_dflt_wait,
2107 .parent = &l4_ck, 2104 .parent = &l4_ck,
2108 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2105 .flags = ENABLE_ON_INIT,
2109 ENABLE_ON_INIT,
2110 .clkdm_name = "core_l4_clkdm", 2106 .clkdm_name = "core_l4_clkdm",
2111 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2107 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2112 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, 2108 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
@@ -2115,8 +2111,8 @@ static struct clk omapctrl_ick = {
2115 2111
2116static struct clk icr_ick = { 2112static struct clk icr_ick = {
2117 .name = "icr_ick", 2113 .name = "icr_ick",
2114 .ops = &clkops_omap2_dflt_wait,
2118 .parent = &l4_ck, 2115 .parent = &l4_ck,
2119 .flags = CLOCK_IN_OMAP243X,
2120 .clkdm_name = "core_l4_clkdm", 2116 .clkdm_name = "core_l4_clkdm",
2121 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2117 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2122 .enable_bit = OMAP2430_EN_ICR_SHIFT, 2118 .enable_bit = OMAP2430_EN_ICR_SHIFT,
@@ -2125,8 +2121,8 @@ static struct clk icr_ick = {
2125 2121
2126static struct clk cam_ick = { 2122static struct clk cam_ick = {
2127 .name = "cam_ick", 2123 .name = "cam_ick",
2124 .ops = &clkops_omap2_dflt,
2128 .parent = &l4_ck, 2125 .parent = &l4_ck,
2129 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2130 .clkdm_name = "core_l4_clkdm", 2126 .clkdm_name = "core_l4_clkdm",
2131 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2127 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2132 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2128 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2140,8 +2136,8 @@ static struct clk cam_ick = {
2140 */ 2136 */
2141static struct clk cam_fck = { 2137static struct clk cam_fck = {
2142 .name = "cam_fck", 2138 .name = "cam_fck",
2139 .ops = &clkops_omap2_dflt,
2143 .parent = &func_96m_ck, 2140 .parent = &func_96m_ck,
2144 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2145 .clkdm_name = "core_l3_clkdm", 2141 .clkdm_name = "core_l3_clkdm",
2146 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2142 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2147 .enable_bit = OMAP24XX_EN_CAM_SHIFT, 2143 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
@@ -2150,8 +2146,8 @@ static struct clk cam_fck = {
2150 2146
2151static struct clk mailboxes_ick = { 2147static struct clk mailboxes_ick = {
2152 .name = "mailboxes_ick", 2148 .name = "mailboxes_ick",
2149 .ops = &clkops_omap2_dflt_wait,
2153 .parent = &l4_ck, 2150 .parent = &l4_ck,
2154 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2155 .clkdm_name = "core_l4_clkdm", 2151 .clkdm_name = "core_l4_clkdm",
2156 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2152 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2157 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 2153 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
@@ -2160,8 +2156,8 @@ static struct clk mailboxes_ick = {
2160 2156
2161static struct clk wdt4_ick = { 2157static struct clk wdt4_ick = {
2162 .name = "wdt4_ick", 2158 .name = "wdt4_ick",
2159 .ops = &clkops_omap2_dflt_wait,
2163 .parent = &l4_ck, 2160 .parent = &l4_ck,
2164 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2165 .clkdm_name = "core_l4_clkdm", 2161 .clkdm_name = "core_l4_clkdm",
2166 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2162 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2167 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2163 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2170,8 +2166,8 @@ static struct clk wdt4_ick = {
2170 2166
2171static struct clk wdt4_fck = { 2167static struct clk wdt4_fck = {
2172 .name = "wdt4_fck", 2168 .name = "wdt4_fck",
2169 .ops = &clkops_omap2_dflt_wait,
2173 .parent = &func_32k_ck, 2170 .parent = &func_32k_ck,
2174 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2175 .clkdm_name = "core_l4_clkdm", 2171 .clkdm_name = "core_l4_clkdm",
2176 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2177 .enable_bit = OMAP24XX_EN_WDT4_SHIFT, 2173 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
@@ -2180,8 +2176,8 @@ static struct clk wdt4_fck = {
2180 2176
2181static struct clk wdt3_ick = { 2177static struct clk wdt3_ick = {
2182 .name = "wdt3_ick", 2178 .name = "wdt3_ick",
2179 .ops = &clkops_omap2_dflt_wait,
2183 .parent = &l4_ck, 2180 .parent = &l4_ck,
2184 .flags = CLOCK_IN_OMAP242X,
2185 .clkdm_name = "core_l4_clkdm", 2181 .clkdm_name = "core_l4_clkdm",
2186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2182 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2187 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2183 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2190,8 +2186,8 @@ static struct clk wdt3_ick = {
2190 2186
2191static struct clk wdt3_fck = { 2187static struct clk wdt3_fck = {
2192 .name = "wdt3_fck", 2188 .name = "wdt3_fck",
2189 .ops = &clkops_omap2_dflt_wait,
2193 .parent = &func_32k_ck, 2190 .parent = &func_32k_ck,
2194 .flags = CLOCK_IN_OMAP242X,
2195 .clkdm_name = "core_l4_clkdm", 2191 .clkdm_name = "core_l4_clkdm",
2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2197 .enable_bit = OMAP2420_EN_WDT3_SHIFT, 2193 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
@@ -2200,8 +2196,8 @@ static struct clk wdt3_fck = {
2200 2196
2201static struct clk mspro_ick = { 2197static struct clk mspro_ick = {
2202 .name = "mspro_ick", 2198 .name = "mspro_ick",
2199 .ops = &clkops_omap2_dflt_wait,
2203 .parent = &l4_ck, 2200 .parent = &l4_ck,
2204 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2205 .clkdm_name = "core_l4_clkdm", 2201 .clkdm_name = "core_l4_clkdm",
2206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2202 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2207 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2203 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2210,8 +2206,8 @@ static struct clk mspro_ick = {
2210 2206
2211static struct clk mspro_fck = { 2207static struct clk mspro_fck = {
2212 .name = "mspro_fck", 2208 .name = "mspro_fck",
2209 .ops = &clkops_omap2_dflt_wait,
2213 .parent = &func_96m_ck, 2210 .parent = &func_96m_ck,
2214 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2215 .clkdm_name = "core_l4_clkdm", 2211 .clkdm_name = "core_l4_clkdm",
2216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2212 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2217 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, 2213 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
@@ -2220,8 +2216,8 @@ static struct clk mspro_fck = {
2220 2216
2221static struct clk mmc_ick = { 2217static struct clk mmc_ick = {
2222 .name = "mmc_ick", 2218 .name = "mmc_ick",
2219 .ops = &clkops_omap2_dflt_wait,
2223 .parent = &l4_ck, 2220 .parent = &l4_ck,
2224 .flags = CLOCK_IN_OMAP242X,
2225 .clkdm_name = "core_l4_clkdm", 2221 .clkdm_name = "core_l4_clkdm",
2226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2222 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2227 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2223 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2230,8 +2226,8 @@ static struct clk mmc_ick = {
2230 2226
2231static struct clk mmc_fck = { 2227static struct clk mmc_fck = {
2232 .name = "mmc_fck", 2228 .name = "mmc_fck",
2229 .ops = &clkops_omap2_dflt_wait,
2233 .parent = &func_96m_ck, 2230 .parent = &func_96m_ck,
2234 .flags = CLOCK_IN_OMAP242X,
2235 .clkdm_name = "core_l4_clkdm", 2231 .clkdm_name = "core_l4_clkdm",
2236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2232 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2237 .enable_bit = OMAP2420_EN_MMC_SHIFT, 2233 .enable_bit = OMAP2420_EN_MMC_SHIFT,
@@ -2240,8 +2236,8 @@ static struct clk mmc_fck = {
2240 2236
2241static struct clk fac_ick = { 2237static struct clk fac_ick = {
2242 .name = "fac_ick", 2238 .name = "fac_ick",
2239 .ops = &clkops_omap2_dflt_wait,
2243 .parent = &l4_ck, 2240 .parent = &l4_ck,
2244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2245 .clkdm_name = "core_l4_clkdm", 2241 .clkdm_name = "core_l4_clkdm",
2246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2247 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2243 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2250,8 +2246,8 @@ static struct clk fac_ick = {
2250 2246
2251static struct clk fac_fck = { 2247static struct clk fac_fck = {
2252 .name = "fac_fck", 2248 .name = "fac_fck",
2249 .ops = &clkops_omap2_dflt_wait,
2253 .parent = &func_12m_ck, 2250 .parent = &func_12m_ck,
2254 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2255 .clkdm_name = "core_l4_clkdm", 2251 .clkdm_name = "core_l4_clkdm",
2256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2257 .enable_bit = OMAP24XX_EN_FAC_SHIFT, 2253 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
@@ -2260,8 +2256,8 @@ static struct clk fac_fck = {
2260 2256
2261static struct clk eac_ick = { 2257static struct clk eac_ick = {
2262 .name = "eac_ick", 2258 .name = "eac_ick",
2259 .ops = &clkops_omap2_dflt_wait,
2263 .parent = &l4_ck, 2260 .parent = &l4_ck,
2264 .flags = CLOCK_IN_OMAP242X,
2265 .clkdm_name = "core_l4_clkdm", 2261 .clkdm_name = "core_l4_clkdm",
2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2262 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2267 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2263 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2270,8 +2266,8 @@ static struct clk eac_ick = {
2270 2266
2271static struct clk eac_fck = { 2267static struct clk eac_fck = {
2272 .name = "eac_fck", 2268 .name = "eac_fck",
2269 .ops = &clkops_omap2_dflt_wait,
2273 .parent = &func_96m_ck, 2270 .parent = &func_96m_ck,
2274 .flags = CLOCK_IN_OMAP242X,
2275 .clkdm_name = "core_l4_clkdm", 2271 .clkdm_name = "core_l4_clkdm",
2276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2277 .enable_bit = OMAP2420_EN_EAC_SHIFT, 2273 .enable_bit = OMAP2420_EN_EAC_SHIFT,
@@ -2280,8 +2276,8 @@ static struct clk eac_fck = {
2280 2276
2281static struct clk hdq_ick = { 2277static struct clk hdq_ick = {
2282 .name = "hdq_ick", 2278 .name = "hdq_ick",
2279 .ops = &clkops_omap2_dflt_wait,
2283 .parent = &l4_ck, 2280 .parent = &l4_ck,
2284 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2285 .clkdm_name = "core_l4_clkdm", 2281 .clkdm_name = "core_l4_clkdm",
2286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2282 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2287 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2283 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2290,8 +2286,8 @@ static struct clk hdq_ick = {
2290 2286
2291static struct clk hdq_fck = { 2287static struct clk hdq_fck = {
2292 .name = "hdq_fck", 2288 .name = "hdq_fck",
2289 .ops = &clkops_omap2_dflt_wait,
2293 .parent = &func_12m_ck, 2290 .parent = &func_12m_ck,
2294 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2295 .clkdm_name = "core_l4_clkdm", 2291 .clkdm_name = "core_l4_clkdm",
2296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2297 .enable_bit = OMAP24XX_EN_HDQ_SHIFT, 2293 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
@@ -2300,9 +2296,9 @@ static struct clk hdq_fck = {
2300 2296
2301static struct clk i2c2_ick = { 2297static struct clk i2c2_ick = {
2302 .name = "i2c_ick", 2298 .name = "i2c_ick",
2299 .ops = &clkops_omap2_dflt_wait,
2303 .id = 2, 2300 .id = 2,
2304 .parent = &l4_ck, 2301 .parent = &l4_ck,
2305 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2306 .clkdm_name = "core_l4_clkdm", 2302 .clkdm_name = "core_l4_clkdm",
2307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2303 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2308 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2304 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2311,9 +2307,9 @@ static struct clk i2c2_ick = {
2311 2307
2312static struct clk i2c2_fck = { 2308static struct clk i2c2_fck = {
2313 .name = "i2c_fck", 2309 .name = "i2c_fck",
2310 .ops = &clkops_omap2_dflt_wait,
2314 .id = 2, 2311 .id = 2,
2315 .parent = &func_12m_ck, 2312 .parent = &func_12m_ck,
2316 .flags = CLOCK_IN_OMAP242X,
2317 .clkdm_name = "core_l4_clkdm", 2313 .clkdm_name = "core_l4_clkdm",
2318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2314 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2319 .enable_bit = OMAP2420_EN_I2C2_SHIFT, 2315 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
@@ -2322,9 +2318,9 @@ static struct clk i2c2_fck = {
2322 2318
2323static struct clk i2chs2_fck = { 2319static struct clk i2chs2_fck = {
2324 .name = "i2c_fck", 2320 .name = "i2c_fck",
2321 .ops = &clkops_omap2_dflt_wait,
2325 .id = 2, 2322 .id = 2,
2326 .parent = &func_96m_ck, 2323 .parent = &func_96m_ck,
2327 .flags = CLOCK_IN_OMAP243X,
2328 .clkdm_name = "core_l4_clkdm", 2324 .clkdm_name = "core_l4_clkdm",
2329 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2325 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2330 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, 2326 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
@@ -2333,9 +2329,9 @@ static struct clk i2chs2_fck = {
2333 2329
2334static struct clk i2c1_ick = { 2330static struct clk i2c1_ick = {
2335 .name = "i2c_ick", 2331 .name = "i2c_ick",
2332 .ops = &clkops_omap2_dflt_wait,
2336 .id = 1, 2333 .id = 1,
2337 .parent = &l4_ck, 2334 .parent = &l4_ck,
2338 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2339 .clkdm_name = "core_l4_clkdm", 2335 .clkdm_name = "core_l4_clkdm",
2340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2341 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2337 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2344,9 +2340,9 @@ static struct clk i2c1_ick = {
2344 2340
2345static struct clk i2c1_fck = { 2341static struct clk i2c1_fck = {
2346 .name = "i2c_fck", 2342 .name = "i2c_fck",
2343 .ops = &clkops_omap2_dflt_wait,
2347 .id = 1, 2344 .id = 1,
2348 .parent = &func_12m_ck, 2345 .parent = &func_12m_ck,
2349 .flags = CLOCK_IN_OMAP242X,
2350 .clkdm_name = "core_l4_clkdm", 2346 .clkdm_name = "core_l4_clkdm",
2351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2347 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2352 .enable_bit = OMAP2420_EN_I2C1_SHIFT, 2348 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
@@ -2355,9 +2351,9 @@ static struct clk i2c1_fck = {
2355 2351
2356static struct clk i2chs1_fck = { 2352static struct clk i2chs1_fck = {
2357 .name = "i2c_fck", 2353 .name = "i2c_fck",
2354 .ops = &clkops_omap2_dflt_wait,
2358 .id = 1, 2355 .id = 1,
2359 .parent = &func_96m_ck, 2356 .parent = &func_96m_ck,
2360 .flags = CLOCK_IN_OMAP243X,
2361 .clkdm_name = "core_l4_clkdm", 2357 .clkdm_name = "core_l4_clkdm",
2362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2363 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, 2359 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
@@ -2366,33 +2362,33 @@ static struct clk i2chs1_fck = {
2366 2362
2367static struct clk gpmc_fck = { 2363static struct clk gpmc_fck = {
2368 .name = "gpmc_fck", 2364 .name = "gpmc_fck",
2365 .ops = &clkops_null, /* RMK: missing? */
2369 .parent = &core_l3_ck, 2366 .parent = &core_l3_ck,
2370 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2367 .flags = ENABLE_ON_INIT,
2371 ENABLE_ON_INIT,
2372 .clkdm_name = "core_l3_clkdm", 2368 .clkdm_name = "core_l3_clkdm",
2373 .recalc = &followparent_recalc, 2369 .recalc = &followparent_recalc,
2374}; 2370};
2375 2371
2376static struct clk sdma_fck = { 2372static struct clk sdma_fck = {
2377 .name = "sdma_fck", 2373 .name = "sdma_fck",
2374 .ops = &clkops_null, /* RMK: missing? */
2378 .parent = &core_l3_ck, 2375 .parent = &core_l3_ck,
2379 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2380 .clkdm_name = "core_l3_clkdm", 2376 .clkdm_name = "core_l3_clkdm",
2381 .recalc = &followparent_recalc, 2377 .recalc = &followparent_recalc,
2382}; 2378};
2383 2379
2384static struct clk sdma_ick = { 2380static struct clk sdma_ick = {
2385 .name = "sdma_ick", 2381 .name = "sdma_ick",
2382 .ops = &clkops_null, /* RMK: missing? */
2386 .parent = &l4_ck, 2383 .parent = &l4_ck,
2387 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2388 .clkdm_name = "core_l3_clkdm", 2384 .clkdm_name = "core_l3_clkdm",
2389 .recalc = &followparent_recalc, 2385 .recalc = &followparent_recalc,
2390}; 2386};
2391 2387
2392static struct clk vlynq_ick = { 2388static struct clk vlynq_ick = {
2393 .name = "vlynq_ick", 2389 .name = "vlynq_ick",
2390 .ops = &clkops_omap2_dflt_wait,
2394 .parent = &core_l3_ck, 2391 .parent = &core_l3_ck,
2395 .flags = CLOCK_IN_OMAP242X,
2396 .clkdm_name = "core_l3_clkdm", 2392 .clkdm_name = "core_l3_clkdm",
2397 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2398 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2394 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2426,8 +2422,9 @@ static const struct clksel vlynq_fck_clksel[] = {
2426 2422
2427static struct clk vlynq_fck = { 2423static struct clk vlynq_fck = {
2428 .name = "vlynq_fck", 2424 .name = "vlynq_fck",
2425 .ops = &clkops_omap2_dflt_wait,
2429 .parent = &func_96m_ck, 2426 .parent = &func_96m_ck,
2430 .flags = CLOCK_IN_OMAP242X | DELAYED_APP, 2427 .flags = DELAYED_APP,
2431 .clkdm_name = "core_l3_clkdm", 2428 .clkdm_name = "core_l3_clkdm",
2432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 2429 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2433 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 2430 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -2442,8 +2439,9 @@ static struct clk vlynq_fck = {
2442 2439
2443static struct clk sdrc_ick = { 2440static struct clk sdrc_ick = {
2444 .name = "sdrc_ick", 2441 .name = "sdrc_ick",
2442 .ops = &clkops_omap2_dflt_wait,
2445 .parent = &l4_ck, 2443 .parent = &l4_ck,
2446 .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, 2444 .flags = ENABLE_ON_INIT,
2447 .clkdm_name = "core_l4_clkdm", 2445 .clkdm_name = "core_l4_clkdm",
2448 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 2446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
2449 .enable_bit = OMAP2430_EN_SDRC_SHIFT, 2447 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
@@ -2452,8 +2450,8 @@ static struct clk sdrc_ick = {
2452 2450
2453static struct clk des_ick = { 2451static struct clk des_ick = {
2454 .name = "des_ick", 2452 .name = "des_ick",
2453 .ops = &clkops_omap2_dflt_wait,
2455 .parent = &l4_ck, 2454 .parent = &l4_ck,
2456 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2457 .clkdm_name = "core_l4_clkdm", 2455 .clkdm_name = "core_l4_clkdm",
2458 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2456 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2459 .enable_bit = OMAP24XX_EN_DES_SHIFT, 2457 .enable_bit = OMAP24XX_EN_DES_SHIFT,
@@ -2462,8 +2460,8 @@ static struct clk des_ick = {
2462 2460
2463static struct clk sha_ick = { 2461static struct clk sha_ick = {
2464 .name = "sha_ick", 2462 .name = "sha_ick",
2463 .ops = &clkops_omap2_dflt_wait,
2465 .parent = &l4_ck, 2464 .parent = &l4_ck,
2466 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2467 .clkdm_name = "core_l4_clkdm", 2465 .clkdm_name = "core_l4_clkdm",
2468 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2469 .enable_bit = OMAP24XX_EN_SHA_SHIFT, 2467 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
@@ -2472,8 +2470,8 @@ static struct clk sha_ick = {
2472 2470
2473static struct clk rng_ick = { 2471static struct clk rng_ick = {
2474 .name = "rng_ick", 2472 .name = "rng_ick",
2473 .ops = &clkops_omap2_dflt_wait,
2475 .parent = &l4_ck, 2474 .parent = &l4_ck,
2476 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2477 .clkdm_name = "core_l4_clkdm", 2475 .clkdm_name = "core_l4_clkdm",
2478 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2476 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2479 .enable_bit = OMAP24XX_EN_RNG_SHIFT, 2477 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
@@ -2482,8 +2480,8 @@ static struct clk rng_ick = {
2482 2480
2483static struct clk aes_ick = { 2481static struct clk aes_ick = {
2484 .name = "aes_ick", 2482 .name = "aes_ick",
2483 .ops = &clkops_omap2_dflt_wait,
2485 .parent = &l4_ck, 2484 .parent = &l4_ck,
2486 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2487 .clkdm_name = "core_l4_clkdm", 2485 .clkdm_name = "core_l4_clkdm",
2488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2486 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2489 .enable_bit = OMAP24XX_EN_AES_SHIFT, 2487 .enable_bit = OMAP24XX_EN_AES_SHIFT,
@@ -2492,8 +2490,8 @@ static struct clk aes_ick = {
2492 2490
2493static struct clk pka_ick = { 2491static struct clk pka_ick = {
2494 .name = "pka_ick", 2492 .name = "pka_ick",
2493 .ops = &clkops_omap2_dflt_wait,
2495 .parent = &l4_ck, 2494 .parent = &l4_ck,
2496 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2497 .clkdm_name = "core_l4_clkdm", 2495 .clkdm_name = "core_l4_clkdm",
2498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 2496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
2499 .enable_bit = OMAP24XX_EN_PKA_SHIFT, 2497 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
@@ -2502,8 +2500,8 @@ static struct clk pka_ick = {
2502 2500
2503static struct clk usb_fck = { 2501static struct clk usb_fck = {
2504 .name = "usb_fck", 2502 .name = "usb_fck",
2503 .ops = &clkops_omap2_dflt_wait,
2505 .parent = &func_48m_ck, 2504 .parent = &func_48m_ck,
2506 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
2507 .clkdm_name = "core_l3_clkdm", 2505 .clkdm_name = "core_l3_clkdm",
2508 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2506 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2509 .enable_bit = OMAP24XX_EN_USB_SHIFT, 2507 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -2512,8 +2510,8 @@ static struct clk usb_fck = {
2512 2510
2513static struct clk usbhs_ick = { 2511static struct clk usbhs_ick = {
2514 .name = "usbhs_ick", 2512 .name = "usbhs_ick",
2513 .ops = &clkops_omap2_dflt_wait,
2515 .parent = &core_l3_ck, 2514 .parent = &core_l3_ck,
2516 .flags = CLOCK_IN_OMAP243X,
2517 .clkdm_name = "core_l3_clkdm", 2515 .clkdm_name = "core_l3_clkdm",
2518 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2519 .enable_bit = OMAP2430_EN_USBHS_SHIFT, 2517 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
@@ -2522,8 +2520,8 @@ static struct clk usbhs_ick = {
2522 2520
2523static struct clk mmchs1_ick = { 2521static struct clk mmchs1_ick = {
2524 .name = "mmchs_ick", 2522 .name = "mmchs_ick",
2523 .ops = &clkops_omap2_dflt_wait,
2525 .parent = &l4_ck, 2524 .parent = &l4_ck,
2526 .flags = CLOCK_IN_OMAP243X,
2527 .clkdm_name = "core_l4_clkdm", 2525 .clkdm_name = "core_l4_clkdm",
2528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2526 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2529 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2527 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2532,8 +2530,8 @@ static struct clk mmchs1_ick = {
2532 2530
2533static struct clk mmchs1_fck = { 2531static struct clk mmchs1_fck = {
2534 .name = "mmchs_fck", 2532 .name = "mmchs_fck",
2533 .ops = &clkops_omap2_dflt_wait,
2535 .parent = &func_96m_ck, 2534 .parent = &func_96m_ck,
2536 .flags = CLOCK_IN_OMAP243X,
2537 .clkdm_name = "core_l3_clkdm", 2535 .clkdm_name = "core_l3_clkdm",
2538 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2539 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, 2537 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
@@ -2542,9 +2540,9 @@ static struct clk mmchs1_fck = {
2542 2540
2543static struct clk mmchs2_ick = { 2541static struct clk mmchs2_ick = {
2544 .name = "mmchs_ick", 2542 .name = "mmchs_ick",
2543 .ops = &clkops_omap2_dflt_wait,
2545 .id = 1, 2544 .id = 1,
2546 .parent = &l4_ck, 2545 .parent = &l4_ck,
2547 .flags = CLOCK_IN_OMAP243X,
2548 .clkdm_name = "core_l4_clkdm", 2546 .clkdm_name = "core_l4_clkdm",
2549 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2547 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2550 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2548 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
@@ -2553,9 +2551,9 @@ static struct clk mmchs2_ick = {
2553 2551
2554static struct clk mmchs2_fck = { 2552static struct clk mmchs2_fck = {
2555 .name = "mmchs_fck", 2553 .name = "mmchs_fck",
2554 .ops = &clkops_omap2_dflt_wait,
2556 .id = 1, 2555 .id = 1,
2557 .parent = &func_96m_ck, 2556 .parent = &func_96m_ck,
2558 .flags = CLOCK_IN_OMAP243X,
2559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2560 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, 2558 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
2561 .recalc = &followparent_recalc, 2559 .recalc = &followparent_recalc,
@@ -2563,8 +2561,8 @@ static struct clk mmchs2_fck = {
2563 2561
2564static struct clk gpio5_ick = { 2562static struct clk gpio5_ick = {
2565 .name = "gpio5_ick", 2563 .name = "gpio5_ick",
2564 .ops = &clkops_omap2_dflt_wait,
2566 .parent = &l4_ck, 2565 .parent = &l4_ck,
2567 .flags = CLOCK_IN_OMAP243X,
2568 .clkdm_name = "core_l4_clkdm", 2566 .clkdm_name = "core_l4_clkdm",
2569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2568 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2573,8 +2571,8 @@ static struct clk gpio5_ick = {
2573 2571
2574static struct clk gpio5_fck = { 2572static struct clk gpio5_fck = {
2575 .name = "gpio5_fck", 2573 .name = "gpio5_fck",
2574 .ops = &clkops_omap2_dflt_wait,
2576 .parent = &func_32k_ck, 2575 .parent = &func_32k_ck,
2577 .flags = CLOCK_IN_OMAP243X,
2578 .clkdm_name = "core_l4_clkdm", 2576 .clkdm_name = "core_l4_clkdm",
2579 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2580 .enable_bit = OMAP2430_EN_GPIO5_SHIFT, 2578 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
@@ -2583,8 +2581,8 @@ static struct clk gpio5_fck = {
2583 2581
2584static struct clk mdm_intc_ick = { 2582static struct clk mdm_intc_ick = {
2585 .name = "mdm_intc_ick", 2583 .name = "mdm_intc_ick",
2584 .ops = &clkops_omap2_dflt_wait,
2586 .parent = &l4_ck, 2585 .parent = &l4_ck,
2587 .flags = CLOCK_IN_OMAP243X,
2588 .clkdm_name = "core_l4_clkdm", 2586 .clkdm_name = "core_l4_clkdm",
2589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2590 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, 2588 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
@@ -2593,8 +2591,8 @@ static struct clk mdm_intc_ick = {
2593 2591
2594static struct clk mmchsdb1_fck = { 2592static struct clk mmchsdb1_fck = {
2595 .name = "mmchsdb_fck", 2593 .name = "mmchsdb_fck",
2594 .ops = &clkops_omap2_dflt_wait,
2596 .parent = &func_32k_ck, 2595 .parent = &func_32k_ck,
2597 .flags = CLOCK_IN_OMAP243X,
2598 .clkdm_name = "core_l4_clkdm", 2596 .clkdm_name = "core_l4_clkdm",
2599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2597 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2600 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, 2598 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
@@ -2603,9 +2601,9 @@ static struct clk mmchsdb1_fck = {
2603 2601
2604static struct clk mmchsdb2_fck = { 2602static struct clk mmchsdb2_fck = {
2605 .name = "mmchsdb_fck", 2603 .name = "mmchsdb_fck",
2604 .ops = &clkops_omap2_dflt_wait,
2606 .id = 1, 2605 .id = 1,
2607 .parent = &func_32k_ck, 2606 .parent = &func_32k_ck,
2608 .flags = CLOCK_IN_OMAP243X,
2609 .clkdm_name = "core_l4_clkdm", 2607 .clkdm_name = "core_l4_clkdm",
2610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 2608 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
2611 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, 2609 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
@@ -2628,166 +2626,13 @@ static struct clk mmchsdb2_fck = {
2628 */ 2626 */
2629static struct clk virt_prcm_set = { 2627static struct clk virt_prcm_set = {
2630 .name = "virt_prcm_set", 2628 .name = "virt_prcm_set",
2631 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2629 .ops = &clkops_null,
2632 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, 2630 .flags = DELAYED_APP,
2633 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2631 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2634 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2632 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2635 .set_rate = &omap2_select_table_rate, 2633 .set_rate = &omap2_select_table_rate,
2636 .round_rate = &omap2_round_to_table_rate, 2634 .round_rate = &omap2_round_to_table_rate,
2637}; 2635};
2638 2636
2639static struct clk *onchip_24xx_clks[] __initdata = {
2640 /* external root sources */
2641 &func_32k_ck,
2642 &osc_ck,
2643 &sys_ck,
2644 &alt_ck,
2645 /* internal analog sources */
2646 &dpll_ck,
2647 &apll96_ck,
2648 &apll54_ck,
2649 /* internal prcm root sources */
2650 &func_54m_ck,
2651 &core_ck,
2652 &func_96m_ck,
2653 &func_48m_ck,
2654 &func_12m_ck,
2655 &wdt1_osc_ck,
2656 &sys_clkout_src,
2657 &sys_clkout,
2658 &sys_clkout2_src,
2659 &sys_clkout2,
2660 &emul_ck,
2661 /* mpu domain clocks */
2662 &mpu_ck,
2663 /* dsp domain clocks */
2664 &dsp_fck,
2665 &dsp_irate_ick,
2666 &dsp_ick, /* 242x */
2667 &iva2_1_ick, /* 243x */
2668 &iva1_ifck, /* 242x */
2669 &iva1_mpu_int_ifck, /* 242x */
2670 /* GFX domain clocks */
2671 &gfx_3d_fck,
2672 &gfx_2d_fck,
2673 &gfx_ick,
2674 /* Modem domain clocks */
2675 &mdm_ick,
2676 &mdm_osc_ck,
2677 /* DSS domain clocks */
2678 &dss_ick,
2679 &dss1_fck,
2680 &dss2_fck,
2681 &dss_54m_fck,
2682 /* L3 domain clocks */
2683 &core_l3_ck,
2684 &ssi_ssr_sst_fck,
2685 &usb_l4_ick,
2686 /* L4 domain clocks */
2687 &l4_ck, /* used as both core_l4 and wu_l4 */
2688 /* virtual meta-group clock */
2689 &virt_prcm_set,
2690 /* general l4 interface ck, multi-parent functional clk */
2691 &gpt1_ick,
2692 &gpt1_fck,
2693 &gpt2_ick,
2694 &gpt2_fck,
2695 &gpt3_ick,
2696 &gpt3_fck,
2697 &gpt4_ick,
2698 &gpt4_fck,
2699 &gpt5_ick,
2700 &gpt5_fck,
2701 &gpt6_ick,
2702 &gpt6_fck,
2703 &gpt7_ick,
2704 &gpt7_fck,
2705 &gpt8_ick,
2706 &gpt8_fck,
2707 &gpt9_ick,
2708 &gpt9_fck,
2709 &gpt10_ick,
2710 &gpt10_fck,
2711 &gpt11_ick,
2712 &gpt11_fck,
2713 &gpt12_ick,
2714 &gpt12_fck,
2715 &mcbsp1_ick,
2716 &mcbsp1_fck,
2717 &mcbsp2_ick,
2718 &mcbsp2_fck,
2719 &mcbsp3_ick,
2720 &mcbsp3_fck,
2721 &mcbsp4_ick,
2722 &mcbsp4_fck,
2723 &mcbsp5_ick,
2724 &mcbsp5_fck,
2725 &mcspi1_ick,
2726 &mcspi1_fck,
2727 &mcspi2_ick,
2728 &mcspi2_fck,
2729 &mcspi3_ick,
2730 &mcspi3_fck,
2731 &uart1_ick,
2732 &uart1_fck,
2733 &uart2_ick,
2734 &uart2_fck,
2735 &uart3_ick,
2736 &uart3_fck,
2737 &gpios_ick,
2738 &gpios_fck,
2739 &mpu_wdt_ick,
2740 &mpu_wdt_fck,
2741 &sync_32k_ick,
2742 &wdt1_ick,
2743 &omapctrl_ick,
2744 &icr_ick,
2745 &cam_fck,
2746 &cam_ick,
2747 &mailboxes_ick,
2748 &wdt4_ick,
2749 &wdt4_fck,
2750 &wdt3_ick,
2751 &wdt3_fck,
2752 &mspro_ick,
2753 &mspro_fck,
2754 &mmc_ick,
2755 &mmc_fck,
2756 &fac_ick,
2757 &fac_fck,
2758 &eac_ick,
2759 &eac_fck,
2760 &hdq_ick,
2761 &hdq_fck,
2762 &i2c1_ick,
2763 &i2c1_fck,
2764 &i2chs1_fck,
2765 &i2c2_ick,
2766 &i2c2_fck,
2767 &i2chs2_fck,
2768 &gpmc_fck,
2769 &sdma_fck,
2770 &sdma_ick,
2771 &vlynq_ick,
2772 &vlynq_fck,
2773 &sdrc_ick,
2774 &des_ick,
2775 &sha_ick,
2776 &rng_ick,
2777 &aes_ick,
2778 &pka_ick,
2779 &usb_fck,
2780 &usbhs_ick,
2781 &mmchs1_ick,
2782 &mmchs1_fck,
2783 &mmchs2_ick,
2784 &mmchs2_fck,
2785 &gpio5_ick,
2786 &gpio5_fck,
2787 &mdm_intc_ick,
2788 &mmchsdb1_fck,
2789 &mmchsdb2_fck,
2790};
2791
2792#endif 2637#endif
2793 2638
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 31bb7010bd48..0a14dca31e30 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,15 +30,251 @@
30#include <mach/clock.h> 30#include <mach/clock.h>
31#include <mach/sram.h> 31#include <mach/sram.h>
32#include <asm/div64.h> 32#include <asm/div64.h>
33#include <asm/clkdev.h>
33 34
34#include "memory.h" 35#include <mach/sdrc.h>
35#include "clock.h" 36#include "clock.h"
36#include "clock34xx.h"
37#include "prm.h" 37#include "prm.h"
38#include "prm-regbits-34xx.h" 38#include "prm-regbits-34xx.h"
39#include "cm.h" 39#include "cm.h"
40#include "cm-regbits-34xx.h" 40#include "cm-regbits-34xx.h"
41 41
42static const struct clkops clkops_noncore_dpll_ops;
43
44#include "clock34xx.h"
45
46struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49};
50
51#define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61#define CK_343X (1 << 0)
62#define CK_3430ES1 (1 << 1)
63#define CK_3430ES2 (1 << 2)
64
65static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
98 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
99 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
100 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
101 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
102 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
103 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
104 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
105 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
106 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
107 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
108 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
109 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
110 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
111 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
112 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
113 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
114 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
115 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
116 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
117 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
118 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
119 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
120 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
121 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
122 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
123 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
124 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
125 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
126 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
127 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
128 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
129 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
130 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
131 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
132 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
133 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
134 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
135 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
136 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
137 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
138 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
139 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
140 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
141 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
142 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
143 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
144 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
145 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
146 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
147 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
148 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
149 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
150 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
151 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
152 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
153 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
154 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
155 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
156 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
157 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
158 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
159 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
160 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
161 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
162 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
163 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
164 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
165 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
166 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
167 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
168 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
169 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
170 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
171 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
172 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
173 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
174 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
175 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
176 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
177 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
178 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
179 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
180 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
181 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
182 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
183 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
184 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
185 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
186 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
187 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
188 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
189 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
190 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
191 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
192 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
193 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
194 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
195 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
196 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
197 CLK("omap_rng", "ick", &rng_ick, CK_343X),
198 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
199 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
200 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
201 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
202 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
203 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
204 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
205 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
206 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
207 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
208 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
209 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
211 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
212 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
213 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
214 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
215 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
216 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
217 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
218 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
219 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
220 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
221 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
222 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
223 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
224 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
225 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
226 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
227 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
228 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
229 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
230 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
231 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
232 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
233 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
234 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
235 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
236 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
237 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
238 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
239 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
240 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
241 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
242 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
243 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
244 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
245 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
246 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
247 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
248 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
249 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
250 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
251 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
252 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
253 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
254 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
255 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
256 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
257 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
258 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
259 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
260 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
261 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
262 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
263 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
264 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
265 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
266 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
267 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
268 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
269 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
270 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
271 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
272 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
273 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
274 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
275 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
276};
277
42/* CM_AUTOIDLE_PLL*.AUTO_* bit values */ 278/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
43#define DPLL_AUTOIDLE_DISABLE 0x0 279#define DPLL_AUTOIDLE_DISABLE 0x0
44#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 280#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
@@ -51,11 +287,9 @@
51 * 287 *
52 * Recalculate and propagate the DPLL rate. 288 * Recalculate and propagate the DPLL rate.
53 */ 289 */
54static void omap3_dpll_recalc(struct clk *clk) 290static unsigned long omap3_dpll_recalc(struct clk *clk)
55{ 291{
56 clk->rate = omap2_get_dpll_rate(clk); 292 return omap2_get_dpll_rate(clk);
57
58 propagate_rate(clk);
59} 293}
60 294
61/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ 295/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
@@ -78,14 +312,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
78 const struct dpll_data *dd; 312 const struct dpll_data *dd;
79 int i = 0; 313 int i = 0;
80 int ret = -EINVAL; 314 int ret = -EINVAL;
81 u32 idlest_mask;
82 315
83 dd = clk->dpll_data; 316 dd = clk->dpll_data;
84 317
85 state <<= dd->idlest_bit; 318 state <<= __ffs(dd->idlest_mask);
86 idlest_mask = 1 << dd->idlest_bit;
87 319
88 while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && 320 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
89 i < MAX_DPLL_WAIT_TRIES) { 321 i < MAX_DPLL_WAIT_TRIES) {
90 i++; 322 i++;
91 udelay(1); 323 udelay(1);
@@ -104,6 +336,42 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
104 return ret; 336 return ret;
105} 337}
106 338
339/* From 3430 TRM ES2 4.7.6.2 */
340static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
341{
342 unsigned long fint;
343 u16 f = 0;
344
345 fint = clk->dpll_data->clk_ref->rate / (n + 1);
346
347 pr_debug("clock: fint is %lu\n", fint);
348
349 if (fint >= 750000 && fint <= 1000000)
350 f = 0x3;
351 else if (fint > 1000000 && fint <= 1250000)
352 f = 0x4;
353 else if (fint > 1250000 && fint <= 1500000)
354 f = 0x5;
355 else if (fint > 1500000 && fint <= 1750000)
356 f = 0x6;
357 else if (fint > 1750000 && fint <= 2100000)
358 f = 0x7;
359 else if (fint > 7500000 && fint <= 10000000)
360 f = 0xB;
361 else if (fint > 10000000 && fint <= 12500000)
362 f = 0xC;
363 else if (fint > 12500000 && fint <= 15000000)
364 f = 0xD;
365 else if (fint > 15000000 && fint <= 17500000)
366 f = 0xE;
367 else if (fint > 17500000 && fint <= 21000000)
368 f = 0xF;
369 else
370 pr_debug("clock: unknown freqsel setting for %d\n", n);
371
372 return f;
373}
374
107/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ 375/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
108 376
109/* 377/*
@@ -128,25 +396,20 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
128 396
129 ai = omap3_dpll_autoidle_read(clk); 397 ai = omap3_dpll_autoidle_read(clk);
130 398
399 omap3_dpll_deny_idle(clk);
400
131 _omap3_dpll_write_clken(clk, DPLL_LOCKED); 401 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
132 402
133 if (ai) { 403 r = _omap3_wait_dpll_status(clk, 1);
134 /* 404
135 * If no downstream clocks are enabled, CM_IDLEST bit 405 if (ai)
136 * may never become active, so don't wait for DPLL to lock.
137 */
138 r = 0;
139 omap3_dpll_allow_idle(clk); 406 omap3_dpll_allow_idle(clk);
140 } else {
141 r = _omap3_wait_dpll_status(clk, 1);
142 omap3_dpll_deny_idle(clk);
143 };
144 407
145 return r; 408 return r;
146} 409}
147 410
148/* 411/*
149 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness 412 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
150 * @clk: pointer to a DPLL struct clk 413 * @clk: pointer to a DPLL struct clk
151 * 414 *
152 * Instructs a non-CORE DPLL to enter low-power bypass mode. In 415 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
@@ -236,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
236static int omap3_noncore_dpll_enable(struct clk *clk) 499static int omap3_noncore_dpll_enable(struct clk *clk)
237{ 500{
238 int r; 501 int r;
502 struct dpll_data *dd;
239 503
240 if (clk == &dpll3_ck) 504 if (clk == &dpll3_ck)
241 return -EINVAL; 505 return -EINVAL;
242 506
243 if (clk->parent->rate == clk_get_rate(clk)) 507 dd = clk->dpll_data;
508 if (!dd)
509 return -EINVAL;
510
511 if (clk->rate == dd->clk_bypass->rate) {
512 WARN_ON(clk->parent != dd->clk_bypass);
244 r = _omap3_noncore_dpll_bypass(clk); 513 r = _omap3_noncore_dpll_bypass(clk);
245 else 514 } else {
515 WARN_ON(clk->parent != dd->clk_ref);
246 r = _omap3_noncore_dpll_lock(clk); 516 r = _omap3_noncore_dpll_lock(clk);
517 }
518 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
519 if (!r)
520 clk->rate = omap2_get_dpll_rate(clk);
247 521
248 return r; 522 return r;
249} 523}
@@ -270,6 +544,215 @@ static void omap3_noncore_dpll_disable(struct clk *clk)
270 _omap3_noncore_dpll_stop(clk); 544 _omap3_noncore_dpll_stop(clk);
271} 545}
272 546
547
548/* Non-CORE DPLL rate set code */
549
550/*
551 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
552 * @clk: struct clk * of DPLL to set
553 * @m: DPLL multiplier to set
554 * @n: DPLL divider to set
555 * @freqsel: FREQSEL value to set
556 *
557 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
558 * lock.. Returns -EINVAL upon error, or 0 upon success.
559 */
560static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
561{
562 struct dpll_data *dd = clk->dpll_data;
563 u32 v;
564
565 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
566 _omap3_noncore_dpll_bypass(clk);
567
568 /* Set jitter correction */
569 v = __raw_readl(dd->control_reg);
570 v &= ~dd->freqsel_mask;
571 v |= freqsel << __ffs(dd->freqsel_mask);
572 __raw_writel(v, dd->control_reg);
573
574 /* Set DPLL multiplier, divider */
575 v = __raw_readl(dd->mult_div1_reg);
576 v &= ~(dd->mult_mask | dd->div1_mask);
577 v |= m << __ffs(dd->mult_mask);
578 v |= (n - 1) << __ffs(dd->div1_mask);
579 __raw_writel(v, dd->mult_div1_reg);
580
581 /* We let the clock framework set the other output dividers later */
582
583 /* REVISIT: Set ramp-up delay? */
584
585 _omap3_noncore_dpll_lock(clk);
586
587 return 0;
588}
589
590/**
591 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
592 * @clk: struct clk * of DPLL to set
593 * @rate: rounded target rate
594 *
595 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
596 * low-power bypass, and the target rate is the bypass source clock
597 * rate, then configure the DPLL for bypass. Otherwise, round the
598 * target rate if it hasn't been done already, then program and lock
599 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
600 */
601static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
602{
603 struct clk *new_parent = NULL;
604 u16 freqsel;
605 struct dpll_data *dd;
606 int ret;
607
608 if (!clk || !rate)
609 return -EINVAL;
610
611 dd = clk->dpll_data;
612 if (!dd)
613 return -EINVAL;
614
615 if (rate == omap2_get_dpll_rate(clk))
616 return 0;
617
618 /*
619 * Ensure both the bypass and ref clocks are enabled prior to
620 * doing anything; we need the bypass clock running to reprogram
621 * the DPLL.
622 */
623 omap2_clk_enable(dd->clk_bypass);
624 omap2_clk_enable(dd->clk_ref);
625
626 if (dd->clk_bypass->rate == rate &&
627 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
628 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
629
630 ret = _omap3_noncore_dpll_bypass(clk);
631 if (!ret)
632 new_parent = dd->clk_bypass;
633 } else {
634 if (dd->last_rounded_rate != rate)
635 omap2_dpll_round_rate(clk, rate);
636
637 if (dd->last_rounded_rate == 0)
638 return -EINVAL;
639
640 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
641 if (!freqsel)
642 WARN_ON(1);
643
644 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
645 clk->name, rate);
646
647 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
648 dd->last_rounded_n, freqsel);
649 if (!ret)
650 new_parent = dd->clk_ref;
651 }
652 if (!ret) {
653 /*
654 * Switch the parent clock in the heirarchy, and make sure
655 * that the new parent's usecount is correct. Note: we
656 * enable the new parent before disabling the old to avoid
657 * any unnecessary hardware disable->enable transitions.
658 */
659 if (clk->usecount) {
660 omap2_clk_enable(new_parent);
661 omap2_clk_disable(clk->parent);
662 }
663 clk_reparent(clk, new_parent);
664 clk->rate = rate;
665 }
666 omap2_clk_disable(dd->clk_ref);
667 omap2_clk_disable(dd->clk_bypass);
668
669 return 0;
670}
671
672static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
673{
674 /*
675 * According to the 12-5 CDP code from TI, "Limitation 2.5"
676 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
677 * on DPLL4.
678 */
679 if (omap_rev() == OMAP3430_REV_ES1_0) {
680 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
681 "silicon 'Limitation 2.5' on 3430ES1.\n");
682 return -EINVAL;
683 }
684 return omap3_noncore_dpll_set_rate(clk, rate);
685}
686
687
688/*
689 * CORE DPLL (DPLL3) rate programming functions
690 *
691 * These call into SRAM code to do the actual CM writes, since the SDRAM
692 * is clocked from DPLL3.
693 */
694
695/**
696 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
697 * @clk: struct clk * of DPLL to set
698 * @rate: rounded target rate
699 *
700 * Program the DPLL M2 divider with the rounded target rate. Returns
701 * -EINVAL upon error, or 0 upon success.
702 */
703static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
704{
705 u32 new_div = 0;
706 unsigned long validrate, sdrcrate;
707 struct omap_sdrc_params *sp;
708
709 if (!clk || !rate)
710 return -EINVAL;
711
712 if (clk != &dpll3_m2_ck)
713 return -EINVAL;
714
715 if (rate == clk->rate)
716 return 0;
717
718 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
719 if (validrate != rate)
720 return -EINVAL;
721
722 sdrcrate = sdrc_ick.rate;
723 if (rate > clk->rate)
724 sdrcrate <<= ((rate / clk->rate) - 1);
725 else
726 sdrcrate >>= ((clk->rate / rate) - 1);
727
728 sp = omap2_sdrc_get_params(sdrcrate);
729 if (!sp)
730 return -EINVAL;
731
732 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
733 validrate);
734 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
735 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
736
737 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
738 WARN_ON(new_div != 1 && new_div != 2);
739
740 /* REVISIT: Add SDRC_MR changing to this code also */
741 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
742 sp->actim_ctrlb, new_div);
743
744 return 0;
745}
746
747
748static const struct clkops clkops_noncore_dpll_ops = {
749 .enable = &omap3_noncore_dpll_enable,
750 .disable = &omap3_noncore_dpll_disable,
751};
752
753/* DPLL autoidle read/set code */
754
755
273/** 756/**
274 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits 757 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
275 * @clk: struct clk * of the DPLL to read 758 * @clk: struct clk * of the DPLL to read
@@ -356,9 +839,10 @@ static void omap3_dpll_deny_idle(struct clk *clk)
356 * Using parent clock DPLL data, look up DPLL state. If locked, set our 839 * Using parent clock DPLL data, look up DPLL state. If locked, set our
357 * rate to the dpll_clk * 2; otherwise, just use dpll_clk. 840 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
358 */ 841 */
359static void omap3_clkoutx2_recalc(struct clk *clk) 842static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
360{ 843{
361 const struct dpll_data *dd; 844 const struct dpll_data *dd;
845 unsigned long rate;
362 u32 v; 846 u32 v;
363 struct clk *pclk; 847 struct clk *pclk;
364 848
@@ -372,17 +856,15 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
372 856
373 dd = pclk->dpll_data; 857 dd = pclk->dpll_data;
374 858
375 WARN_ON(!dd->control_reg || !dd->enable_mask); 859 WARN_ON(!dd->enable_mask);
376 860
377 v = __raw_readl(dd->control_reg) & dd->enable_mask; 861 v = __raw_readl(dd->control_reg) & dd->enable_mask;
378 v >>= __ffs(dd->enable_mask); 862 v >>= __ffs(dd->enable_mask);
379 if (v != DPLL_LOCKED) 863 if (v != OMAP3XXX_EN_DPLL_LOCKED)
380 clk->rate = clk->parent->rate; 864 rate = clk->parent->rate;
381 else 865 else
382 clk->rate = clk->parent->rate * 2; 866 rate = clk->parent->rate * 2;
383 867 return rate;
384 if (clk->flags & RATE_PROPAGATES)
385 propagate_rate(clk);
386} 868}
387 869
388/* Common clock code */ 870/* Common clock code */
@@ -432,7 +914,7 @@ static int __init omap2_clk_arch_init(void)
432 914
433 /* REVISIT: not yet ready for 343x */ 915 /* REVISIT: not yet ready for 343x */
434#if 0 916#if 0
435 if (omap2_select_table_rate(&virt_prcm_set, mpurate)) 917 if (clk_set_rate(&virt_prcm_set, mpurate))
436 printk(KERN_ERR "Could not find matching MPU rate\n"); 918 printk(KERN_ERR "Could not find matching MPU rate\n");
437#endif 919#endif
438 920
@@ -450,26 +932,13 @@ arch_initcall(omap2_clk_arch_init);
450int __init omap2_clk_init(void) 932int __init omap2_clk_init(void)
451{ 933{
452 /* struct prcm_config *prcm; */ 934 /* struct prcm_config *prcm; */
453 struct clk **clkp; 935 struct omap_clk *c;
454 /* u32 clkrate; */ 936 /* u32 clkrate; */
455 u32 cpu_clkflg; 937 u32 cpu_clkflg;
456 938
457 /* REVISIT: Ultimately this will be used for multiboot */
458#if 0
459 if (cpu_is_omap242x()) {
460 cpu_mask = RATE_IN_242X;
461 cpu_clkflg = CLOCK_IN_OMAP242X;
462 clkp = onchip_24xx_clks;
463 } else if (cpu_is_omap2430()) {
464 cpu_mask = RATE_IN_243X;
465 cpu_clkflg = CLOCK_IN_OMAP243X;
466 clkp = onchip_24xx_clks;
467 }
468#endif
469 if (cpu_is_omap34xx()) { 939 if (cpu_is_omap34xx()) {
470 cpu_mask = RATE_IN_343X; 940 cpu_mask = RATE_IN_343X;
471 cpu_clkflg = CLOCK_IN_OMAP343X; 941 cpu_clkflg = CK_343X;
472 clkp = onchip_34xx_clks;
473 942
474 /* 943 /*
475 * Update this if there are further clock changes between ES2 944 * Update this if there are further clock changes between ES2
@@ -477,23 +946,24 @@ int __init omap2_clk_init(void)
477 */ 946 */
478 if (omap_rev() == OMAP3430_REV_ES1_0) { 947 if (omap_rev() == OMAP3430_REV_ES1_0) {
479 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 948 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
480 cpu_clkflg |= CLOCK_IN_OMAP3430ES1; 949 cpu_clkflg |= CK_3430ES1;
481 } else { 950 } else {
482 cpu_mask |= RATE_IN_3430ES2; 951 cpu_mask |= RATE_IN_3430ES2;
483 cpu_clkflg |= CLOCK_IN_OMAP3430ES2; 952 cpu_clkflg |= CK_3430ES2;
484 } 953 }
485 } 954 }
486 955
487 clk_init(&omap2_clk_functions); 956 clk_init(&omap2_clk_functions);
488 957
489 for (clkp = onchip_34xx_clks; 958 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
490 clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); 959 clk_init_one(c->lk.clk);
491 clkp++) { 960
492 if ((*clkp)->flags & cpu_clkflg) { 961 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
493 clk_register(*clkp); 962 if (c->cpu & cpu_clkflg) {
494 omap2_init_clk_clkdm(*clkp); 963 clkdev_add(&c->lk);
964 clk_register(c->lk.clk);
965 omap2_init_clk_clkdm(c->lk.clk);
495 } 966 }
496 }
497 967
498 /* REVISIT: Not yet ready for OMAP3 */ 968 /* REVISIT: Not yet ready for OMAP3 */
499#if 0 969#if 0
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index a826094d89b5..70ec10deb654 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -27,13 +27,14 @@
27#include "prm.h" 27#include "prm.h"
28#include "prm-regbits-34xx.h" 28#include "prm-regbits-34xx.h"
29 29
30static void omap3_dpll_recalc(struct clk *clk); 30static unsigned long omap3_dpll_recalc(struct clk *clk);
31static void omap3_clkoutx2_recalc(struct clk *clk); 31static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
32static void omap3_dpll_allow_idle(struct clk *clk); 32static void omap3_dpll_allow_idle(struct clk *clk);
33static void omap3_dpll_deny_idle(struct clk *clk); 33static void omap3_dpll_deny_idle(struct clk *clk);
34static u32 omap3_dpll_autoidle_read(struct clk *clk); 34static u32 omap3_dpll_autoidle_read(struct clk *clk);
35static int omap3_noncore_dpll_enable(struct clk *clk); 35static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36static void omap3_noncore_dpll_disable(struct clk *clk); 36static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
37static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
37 38
38/* Maximum DPLL multiplier, divider values for OMAP3 */ 39/* Maximum DPLL multiplier, divider values for OMAP3 */
39#define OMAP3_MAX_DPLL_MULT 2048 40#define OMAP3_MAX_DPLL_MULT 2048
@@ -47,6 +48,10 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 48 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
48 */ 49 */
49 50
51/* Forward declarations for DPLL bypass clocks */
52static struct clk dpll1_fck;
53static struct clk dpll2_fck;
54
50/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 55/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51#define DPLL_LOW_POWER_STOP 0x1 56#define DPLL_LOW_POWER_STOP 0x1
52#define DPLL_LOW_POWER_BYPASS 0x5 57#define DPLL_LOW_POWER_BYPASS 0x5
@@ -57,67 +62,59 @@ static void omap3_noncore_dpll_disable(struct clk *clk);
57/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
58static struct clk omap_32k_fck = { 63static struct clk omap_32k_fck = {
59 .name = "omap_32k_fck", 64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
60 .rate = 32768, 66 .rate = 32768,
61 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 67 .flags = RATE_FIXED,
62 ALWAYS_ENABLED,
63 .recalc = &propagate_rate,
64}; 68};
65 69
66static struct clk secure_32k_fck = { 70static struct clk secure_32k_fck = {
67 .name = "secure_32k_fck", 71 .name = "secure_32k_fck",
72 .ops = &clkops_null,
68 .rate = 32768, 73 .rate = 32768,
69 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 74 .flags = RATE_FIXED,
70 ALWAYS_ENABLED,
71 .recalc = &propagate_rate,
72}; 75};
73 76
74/* Virtual source clocks for osc_sys_ck */ 77/* Virtual source clocks for osc_sys_ck */
75static struct clk virt_12m_ck = { 78static struct clk virt_12m_ck = {
76 .name = "virt_12m_ck", 79 .name = "virt_12m_ck",
80 .ops = &clkops_null,
77 .rate = 12000000, 81 .rate = 12000000,
78 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 82 .flags = RATE_FIXED,
79 ALWAYS_ENABLED,
80 .recalc = &propagate_rate,
81}; 83};
82 84
83static struct clk virt_13m_ck = { 85static struct clk virt_13m_ck = {
84 .name = "virt_13m_ck", 86 .name = "virt_13m_ck",
87 .ops = &clkops_null,
85 .rate = 13000000, 88 .rate = 13000000,
86 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 89 .flags = RATE_FIXED,
87 ALWAYS_ENABLED,
88 .recalc = &propagate_rate,
89}; 90};
90 91
91static struct clk virt_16_8m_ck = { 92static struct clk virt_16_8m_ck = {
92 .name = "virt_16_8m_ck", 93 .name = "virt_16_8m_ck",
94 .ops = &clkops_null,
93 .rate = 16800000, 95 .rate = 16800000,
94 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | 96 .flags = RATE_FIXED,
95 ALWAYS_ENABLED,
96 .recalc = &propagate_rate,
97}; 97};
98 98
99static struct clk virt_19_2m_ck = { 99static struct clk virt_19_2m_ck = {
100 .name = "virt_19_2m_ck", 100 .name = "virt_19_2m_ck",
101 .ops = &clkops_null,
101 .rate = 19200000, 102 .rate = 19200000,
102 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 103 .flags = RATE_FIXED,
103 ALWAYS_ENABLED,
104 .recalc = &propagate_rate,
105}; 104};
106 105
107static struct clk virt_26m_ck = { 106static struct clk virt_26m_ck = {
108 .name = "virt_26m_ck", 107 .name = "virt_26m_ck",
108 .ops = &clkops_null,
109 .rate = 26000000, 109 .rate = 26000000,
110 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 110 .flags = RATE_FIXED,
111 ALWAYS_ENABLED,
112 .recalc = &propagate_rate,
113}; 111};
114 112
115static struct clk virt_38_4m_ck = { 113static struct clk virt_38_4m_ck = {
116 .name = "virt_38_4m_ck", 114 .name = "virt_38_4m_ck",
115 .ops = &clkops_null,
117 .rate = 38400000, 116 .rate = 38400000,
118 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 117 .flags = RATE_FIXED,
119 ALWAYS_ENABLED,
120 .recalc = &propagate_rate,
121}; 118};
122 119
123static const struct clksel_rate osc_sys_12m_rates[] = { 120static const struct clksel_rate osc_sys_12m_rates[] = {
@@ -164,13 +161,13 @@ static const struct clksel osc_sys_clksel[] = {
164/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ 161/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
165static struct clk osc_sys_ck = { 162static struct clk osc_sys_ck = {
166 .name = "osc_sys_ck", 163 .name = "osc_sys_ck",
164 .ops = &clkops_null,
167 .init = &omap2_init_clksel_parent, 165 .init = &omap2_init_clksel_parent,
168 .clksel_reg = OMAP3430_PRM_CLKSEL, 166 .clksel_reg = OMAP3430_PRM_CLKSEL,
169 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
170 .clksel = osc_sys_clksel, 168 .clksel = osc_sys_clksel,
171 /* REVISIT: deal with autoextclkmode? */ 169 /* REVISIT: deal with autoextclkmode? */
172 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 170 .flags = RATE_FIXED,
173 ALWAYS_ENABLED,
174 .recalc = &omap2_clksel_recalc, 171 .recalc = &omap2_clksel_recalc,
175}; 172};
176 173
@@ -189,36 +186,34 @@ static const struct clksel sys_clksel[] = {
189/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ 186/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
190static struct clk sys_ck = { 187static struct clk sys_ck = {
191 .name = "sys_ck", 188 .name = "sys_ck",
189 .ops = &clkops_null,
192 .parent = &osc_sys_ck, 190 .parent = &osc_sys_ck,
193 .init = &omap2_init_clksel_parent, 191 .init = &omap2_init_clksel_parent,
194 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
195 .clksel_mask = OMAP_SYSCLKDIV_MASK, 193 .clksel_mask = OMAP_SYSCLKDIV_MASK,
196 .clksel = sys_clksel, 194 .clksel = sys_clksel,
197 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
198 .recalc = &omap2_clksel_recalc, 195 .recalc = &omap2_clksel_recalc,
199}; 196};
200 197
201static struct clk sys_altclk = { 198static struct clk sys_altclk = {
202 .name = "sys_altclk", 199 .name = "sys_altclk",
203 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 200 .ops = &clkops_null,
204 .recalc = &propagate_rate,
205}; 201};
206 202
207/* Optional external clock input for some McBSPs */ 203/* Optional external clock input for some McBSPs */
208static struct clk mcbsp_clks = { 204static struct clk mcbsp_clks = {
209 .name = "mcbsp_clks", 205 .name = "mcbsp_clks",
210 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 206 .ops = &clkops_null,
211 .recalc = &propagate_rate,
212}; 207};
213 208
214/* PRM EXTERNAL CLOCK OUTPUT */ 209/* PRM EXTERNAL CLOCK OUTPUT */
215 210
216static struct clk sys_clkout1 = { 211static struct clk sys_clkout1 = {
217 .name = "sys_clkout1", 212 .name = "sys_clkout1",
213 .ops = &clkops_omap2_dflt,
218 .parent = &osc_sys_ck, 214 .parent = &osc_sys_ck,
219 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, 215 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
220 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, 216 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
221 .flags = CLOCK_IN_OMAP343X,
222 .recalc = &followparent_recalc, 217 .recalc = &followparent_recalc,
223}; 218};
224 219
@@ -226,16 +221,6 @@ static struct clk sys_clkout1 = {
226 221
227/* CM CLOCKS */ 222/* CM CLOCKS */
228 223
229static const struct clksel_rate dpll_bypass_rates[] = {
230 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
231 { .div = 0 }
232};
233
234static const struct clksel_rate dpll_locked_rates[] = {
235 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
236 { .div = 0 }
237};
238
239static const struct clksel_rate div16_dpll_rates[] = { 224static const struct clksel_rate div16_dpll_rates[] = {
240 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, 225 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
241 { .div = 2, .val = 2, .flags = RATE_IN_343X }, 226 { .div = 2, .val = 2, .flags = RATE_IN_343X },
@@ -263,6 +248,9 @@ static struct dpll_data dpll1_dd = {
263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 248 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 249 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 250 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
251 .clk_bypass = &dpll1_fck,
252 .clk_ref = &sys_ck,
253 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
266 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 254 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 255 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 256 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -272,18 +260,21 @@ static struct dpll_data dpll1_dd = {
272 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), 260 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, 261 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
274 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 262 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
275 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, 263 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
276 .max_multiplier = OMAP3_MAX_DPLL_MULT, 264 .max_multiplier = OMAP3_MAX_DPLL_MULT,
265 .min_divider = 1,
277 .max_divider = OMAP3_MAX_DPLL_DIV, 266 .max_divider = OMAP3_MAX_DPLL_DIV,
278 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 267 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
279}; 268};
280 269
281static struct clk dpll1_ck = { 270static struct clk dpll1_ck = {
282 .name = "dpll1_ck", 271 .name = "dpll1_ck",
272 .ops = &clkops_null,
283 .parent = &sys_ck, 273 .parent = &sys_ck,
284 .dpll_data = &dpll1_dd, 274 .dpll_data = &dpll1_dd,
285 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
286 .round_rate = &omap2_dpll_round_rate, 275 .round_rate = &omap2_dpll_round_rate,
276 .set_rate = &omap3_noncore_dpll_set_rate,
277 .clkdm_name = "dpll1_clkdm",
287 .recalc = &omap3_dpll_recalc, 278 .recalc = &omap3_dpll_recalc,
288}; 279};
289 280
@@ -293,9 +284,9 @@ static struct clk dpll1_ck = {
293 */ 284 */
294static struct clk dpll1_x2_ck = { 285static struct clk dpll1_x2_ck = {
295 .name = "dpll1_x2_ck", 286 .name = "dpll1_x2_ck",
287 .ops = &clkops_null,
296 .parent = &dpll1_ck, 288 .parent = &dpll1_ck,
297 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 289 .clkdm_name = "dpll1_clkdm",
298 PARENT_CONTROLS_CLOCK,
299 .recalc = &omap3_clkoutx2_recalc, 290 .recalc = &omap3_clkoutx2_recalc,
300}; 291};
301 292
@@ -311,13 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = {
311 */ 302 */
312static struct clk dpll1_x2m2_ck = { 303static struct clk dpll1_x2m2_ck = {
313 .name = "dpll1_x2m2_ck", 304 .name = "dpll1_x2m2_ck",
305 .ops = &clkops_null,
314 .parent = &dpll1_x2_ck, 306 .parent = &dpll1_x2_ck,
315 .init = &omap2_init_clksel_parent, 307 .init = &omap2_init_clksel_parent,
316 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), 308 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
317 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, 309 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
318 .clksel = div16_dpll1_x2m2_clksel, 310 .clksel = div16_dpll1_x2m2_clksel,
319 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 311 .clkdm_name = "dpll1_clkdm",
320 PARENT_CONTROLS_CLOCK,
321 .recalc = &omap2_clksel_recalc, 312 .recalc = &omap2_clksel_recalc,
322}; 313};
323 314
@@ -329,6 +320,9 @@ static struct dpll_data dpll2_dd = {
329 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 320 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
330 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 321 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
331 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 322 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
323 .clk_bypass = &dpll2_fck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 326 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 327 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | 328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
@@ -339,20 +333,21 @@ static struct dpll_data dpll2_dd = {
339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), 333 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, 334 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), 335 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
342 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, 336 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
343 .max_multiplier = OMAP3_MAX_DPLL_MULT, 337 .max_multiplier = OMAP3_MAX_DPLL_MULT,
338 .min_divider = 1,
344 .max_divider = OMAP3_MAX_DPLL_DIV, 339 .max_divider = OMAP3_MAX_DPLL_DIV,
345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 340 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
346}; 341};
347 342
348static struct clk dpll2_ck = { 343static struct clk dpll2_ck = {
349 .name = "dpll2_ck", 344 .name = "dpll2_ck",
345 .ops = &clkops_noncore_dpll_ops,
350 .parent = &sys_ck, 346 .parent = &sys_ck,
351 .dpll_data = &dpll2_dd, 347 .dpll_data = &dpll2_dd,
352 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
353 .enable = &omap3_noncore_dpll_enable,
354 .disable = &omap3_noncore_dpll_disable,
355 .round_rate = &omap2_dpll_round_rate, 348 .round_rate = &omap2_dpll_round_rate,
349 .set_rate = &omap3_noncore_dpll_set_rate,
350 .clkdm_name = "dpll2_clkdm",
356 .recalc = &omap3_dpll_recalc, 351 .recalc = &omap3_dpll_recalc,
357}; 352};
358 353
@@ -367,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = {
367 */ 362 */
368static struct clk dpll2_m2_ck = { 363static struct clk dpll2_m2_ck = {
369 .name = "dpll2_m2_ck", 364 .name = "dpll2_m2_ck",
365 .ops = &clkops_null,
370 .parent = &dpll2_ck, 366 .parent = &dpll2_ck,
371 .init = &omap2_init_clksel_parent, 367 .init = &omap2_init_clksel_parent,
372 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 368 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
373 OMAP3430_CM_CLKSEL2_PLL), 369 OMAP3430_CM_CLKSEL2_PLL),
374 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, 370 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
375 .clksel = div16_dpll2_m2x2_clksel, 371 .clksel = div16_dpll2_m2x2_clksel,
376 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 372 .clkdm_name = "dpll2_clkdm",
377 PARENT_CONTROLS_CLOCK,
378 .recalc = &omap2_clksel_recalc, 373 .recalc = &omap2_clksel_recalc,
379}; 374};
380 375
@@ -387,6 +382,9 @@ static struct dpll_data dpll3_dd = {
387 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 382 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
388 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 383 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
389 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 384 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
385 .clk_bypass = &sys_ck,
386 .clk_ref = &sys_ck,
387 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
390 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 388 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
391 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, 389 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
392 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 390 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
@@ -394,17 +392,21 @@ static struct dpll_data dpll3_dd = {
394 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 392 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
395 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 393 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
396 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, 394 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
395 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
396 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
397 .max_multiplier = OMAP3_MAX_DPLL_MULT, 397 .max_multiplier = OMAP3_MAX_DPLL_MULT,
398 .min_divider = 1,
398 .max_divider = OMAP3_MAX_DPLL_DIV, 399 .max_divider = OMAP3_MAX_DPLL_DIV,
399 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 400 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
400}; 401};
401 402
402static struct clk dpll3_ck = { 403static struct clk dpll3_ck = {
403 .name = "dpll3_ck", 404 .name = "dpll3_ck",
405 .ops = &clkops_null,
404 .parent = &sys_ck, 406 .parent = &sys_ck,
405 .dpll_data = &dpll3_dd, 407 .dpll_data = &dpll3_dd,
406 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
407 .round_rate = &omap2_dpll_round_rate, 408 .round_rate = &omap2_dpll_round_rate,
409 .clkdm_name = "dpll3_clkdm",
408 .recalc = &omap3_dpll_recalc, 410 .recalc = &omap3_dpll_recalc,
409}; 411};
410 412
@@ -414,9 +416,9 @@ static struct clk dpll3_ck = {
414 */ 416 */
415static struct clk dpll3_x2_ck = { 417static struct clk dpll3_x2_ck = {
416 .name = "dpll3_x2_ck", 418 .name = "dpll3_x2_ck",
419 .ops = &clkops_null,
417 .parent = &dpll3_ck, 420 .parent = &dpll3_ck,
418 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 421 .clkdm_name = "dpll3_clkdm",
419 PARENT_CONTROLS_CLOCK,
420 .recalc = &omap3_clkoutx2_recalc, 422 .recalc = &omap3_clkoutx2_recalc,
421}; 423};
422 424
@@ -460,55 +462,34 @@ static const struct clksel div31_dpll3m2_clksel[] = {
460 { .parent = NULL } 462 { .parent = NULL }
461}; 463};
462 464
463/* 465/* DPLL3 output M2 - primary control point for CORE speed */
464 * DPLL3 output M2
465 * REVISIT: This DPLL output divider must be changed in SRAM, so until
466 * that code is ready, this should remain a 'read-only' clksel clock.
467 */
468static struct clk dpll3_m2_ck = { 466static struct clk dpll3_m2_ck = {
469 .name = "dpll3_m2_ck", 467 .name = "dpll3_m2_ck",
468 .ops = &clkops_null,
470 .parent = &dpll3_ck, 469 .parent = &dpll3_ck,
471 .init = &omap2_init_clksel_parent, 470 .init = &omap2_init_clksel_parent,
472 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 471 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
473 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, 472 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
474 .clksel = div31_dpll3m2_clksel, 473 .clksel = div31_dpll3m2_clksel,
475 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 474 .clkdm_name = "dpll3_clkdm",
476 PARENT_CONTROLS_CLOCK, 475 .round_rate = &omap2_clksel_round_rate,
476 .set_rate = &omap3_core_dpll_m2_set_rate,
477 .recalc = &omap2_clksel_recalc, 477 .recalc = &omap2_clksel_recalc,
478}; 478};
479 479
480static const struct clksel core_ck_clksel[] = {
481 { .parent = &sys_ck, .rates = dpll_bypass_rates },
482 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
483 { .parent = NULL }
484};
485
486static struct clk core_ck = { 480static struct clk core_ck = {
487 .name = "core_ck", 481 .name = "core_ck",
488 .init = &omap2_init_clksel_parent, 482 .ops = &clkops_null,
489 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 483 .parent = &dpll3_m2_ck,
490 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 484 .recalc = &followparent_recalc,
491 .clksel = core_ck_clksel,
492 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
493 PARENT_CONTROLS_CLOCK,
494 .recalc = &omap2_clksel_recalc,
495};
496
497static const struct clksel dpll3_m2x2_ck_clksel[] = {
498 { .parent = &sys_ck, .rates = dpll_bypass_rates },
499 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
500 { .parent = NULL }
501}; 485};
502 486
503static struct clk dpll3_m2x2_ck = { 487static struct clk dpll3_m2x2_ck = {
504 .name = "dpll3_m2x2_ck", 488 .name = "dpll3_m2x2_ck",
505 .init = &omap2_init_clksel_parent, 489 .ops = &clkops_null,
506 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 490 .parent = &dpll3_x2_ck,
507 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, 491 .clkdm_name = "dpll3_clkdm",
508 .clksel = dpll3_m2x2_ck_clksel, 492 .recalc = &followparent_recalc,
509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
510 PARENT_CONTROLS_CLOCK,
511 .recalc = &omap2_clksel_recalc,
512}; 493};
513 494
514/* The PWRDN bit is apparently only available on 3430ES2 and above */ 495/* The PWRDN bit is apparently only available on 3430ES2 and above */
@@ -520,42 +501,34 @@ static const struct clksel div16_dpll3_clksel[] = {
520/* This virtual clock is the source for dpll3_m3x2_ck */ 501/* This virtual clock is the source for dpll3_m3x2_ck */
521static struct clk dpll3_m3_ck = { 502static struct clk dpll3_m3_ck = {
522 .name = "dpll3_m3_ck", 503 .name = "dpll3_m3_ck",
504 .ops = &clkops_null,
523 .parent = &dpll3_ck, 505 .parent = &dpll3_ck,
524 .init = &omap2_init_clksel_parent, 506 .init = &omap2_init_clksel_parent,
525 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
526 .clksel_mask = OMAP3430_DIV_DPLL3_MASK, 508 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
527 .clksel = div16_dpll3_clksel, 509 .clksel = div16_dpll3_clksel,
528 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 510 .clkdm_name = "dpll3_clkdm",
529 PARENT_CONTROLS_CLOCK,
530 .recalc = &omap2_clksel_recalc, 511 .recalc = &omap2_clksel_recalc,
531}; 512};
532 513
533/* The PWRDN bit is apparently only available on 3430ES2 and above */ 514/* The PWRDN bit is apparently only available on 3430ES2 and above */
534static struct clk dpll3_m3x2_ck = { 515static struct clk dpll3_m3x2_ck = {
535 .name = "dpll3_m3x2_ck", 516 .name = "dpll3_m3x2_ck",
517 .ops = &clkops_omap2_dflt_wait,
536 .parent = &dpll3_m3_ck, 518 .parent = &dpll3_m3_ck,
537 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 519 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
538 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, 520 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
539 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 521 .flags = INVERT_ENABLE,
522 .clkdm_name = "dpll3_clkdm",
540 .recalc = &omap3_clkoutx2_recalc, 523 .recalc = &omap3_clkoutx2_recalc,
541}; 524};
542 525
543static const struct clksel emu_core_alwon_ck_clksel[] = {
544 { .parent = &sys_ck, .rates = dpll_bypass_rates },
545 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
546 { .parent = NULL }
547};
548
549static struct clk emu_core_alwon_ck = { 526static struct clk emu_core_alwon_ck = {
550 .name = "emu_core_alwon_ck", 527 .name = "emu_core_alwon_ck",
528 .ops = &clkops_null,
551 .parent = &dpll3_m3x2_ck, 529 .parent = &dpll3_m3x2_ck,
552 .init = &omap2_init_clksel_parent, 530 .clkdm_name = "dpll3_clkdm",
553 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 531 .recalc = &followparent_recalc,
554 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
555 .clksel = emu_core_alwon_ck_clksel,
556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
557 PARENT_CONTROLS_CLOCK,
558 .recalc = &omap2_clksel_recalc,
559}; 532};
560 533
561/* DPLL4 */ 534/* DPLL4 */
@@ -565,6 +538,9 @@ static struct dpll_data dpll4_dd = {
565 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 538 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
566 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 539 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
567 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 540 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
541 .clk_bypass = &sys_ck,
542 .clk_ref = &sys_ck,
543 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
568 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 544 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
569 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 545 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
570 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 546 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -574,20 +550,21 @@ static struct dpll_data dpll4_dd = {
574 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), 550 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
575 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 551 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
576 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 552 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
577 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, 553 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
578 .max_multiplier = OMAP3_MAX_DPLL_MULT, 554 .max_multiplier = OMAP3_MAX_DPLL_MULT,
555 .min_divider = 1,
579 .max_divider = OMAP3_MAX_DPLL_DIV, 556 .max_divider = OMAP3_MAX_DPLL_DIV,
580 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 557 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
581}; 558};
582 559
583static struct clk dpll4_ck = { 560static struct clk dpll4_ck = {
584 .name = "dpll4_ck", 561 .name = "dpll4_ck",
562 .ops = &clkops_noncore_dpll_ops,
585 .parent = &sys_ck, 563 .parent = &sys_ck,
586 .dpll_data = &dpll4_dd, 564 .dpll_data = &dpll4_dd,
587 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
588 .enable = &omap3_noncore_dpll_enable,
589 .disable = &omap3_noncore_dpll_disable,
590 .round_rate = &omap2_dpll_round_rate, 565 .round_rate = &omap2_dpll_round_rate,
566 .set_rate = &omap3_dpll4_set_rate,
567 .clkdm_name = "dpll4_clkdm",
591 .recalc = &omap3_dpll_recalc, 568 .recalc = &omap3_dpll_recalc,
592}; 569};
593 570
@@ -598,9 +575,9 @@ static struct clk dpll4_ck = {
598 */ 575 */
599static struct clk dpll4_x2_ck = { 576static struct clk dpll4_x2_ck = {
600 .name = "dpll4_x2_ck", 577 .name = "dpll4_x2_ck",
578 .ops = &clkops_null,
601 .parent = &dpll4_ck, 579 .parent = &dpll4_ck,
602 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 580 .clkdm_name = "dpll4_clkdm",
603 PARENT_CONTROLS_CLOCK,
604 .recalc = &omap3_clkoutx2_recalc, 581 .recalc = &omap3_clkoutx2_recalc,
605}; 582};
606 583
@@ -612,112 +589,101 @@ static const struct clksel div16_dpll4_clksel[] = {
612/* This virtual clock is the source for dpll4_m2x2_ck */ 589/* This virtual clock is the source for dpll4_m2x2_ck */
613static struct clk dpll4_m2_ck = { 590static struct clk dpll4_m2_ck = {
614 .name = "dpll4_m2_ck", 591 .name = "dpll4_m2_ck",
592 .ops = &clkops_null,
615 .parent = &dpll4_ck, 593 .parent = &dpll4_ck,
616 .init = &omap2_init_clksel_parent, 594 .init = &omap2_init_clksel_parent,
617 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), 595 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
618 .clksel_mask = OMAP3430_DIV_96M_MASK, 596 .clksel_mask = OMAP3430_DIV_96M_MASK,
619 .clksel = div16_dpll4_clksel, 597 .clksel = div16_dpll4_clksel,
620 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 598 .clkdm_name = "dpll4_clkdm",
621 PARENT_CONTROLS_CLOCK,
622 .recalc = &omap2_clksel_recalc, 599 .recalc = &omap2_clksel_recalc,
623}; 600};
624 601
625/* The PWRDN bit is apparently only available on 3430ES2 and above */ 602/* The PWRDN bit is apparently only available on 3430ES2 and above */
626static struct clk dpll4_m2x2_ck = { 603static struct clk dpll4_m2x2_ck = {
627 .name = "dpll4_m2x2_ck", 604 .name = "dpll4_m2x2_ck",
605 .ops = &clkops_omap2_dflt_wait,
628 .parent = &dpll4_m2_ck, 606 .parent = &dpll4_m2_ck,
629 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 607 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
630 .enable_bit = OMAP3430_PWRDN_96M_SHIFT, 608 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
631 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 609 .flags = INVERT_ENABLE,
610 .clkdm_name = "dpll4_clkdm",
632 .recalc = &omap3_clkoutx2_recalc, 611 .recalc = &omap3_clkoutx2_recalc,
633}; 612};
634 613
635static const struct clksel omap_96m_alwon_fck_clksel[] = { 614/*
636 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 615 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
637 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 616 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
638 { .parent = NULL } 617 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
639}; 618 * CM_96K_(F)CLK.
640 619 */
641static struct clk omap_96m_alwon_fck = { 620static struct clk omap_96m_alwon_fck = {
642 .name = "omap_96m_alwon_fck", 621 .name = "omap_96m_alwon_fck",
622 .ops = &clkops_null,
643 .parent = &dpll4_m2x2_ck, 623 .parent = &dpll4_m2x2_ck,
644 .init = &omap2_init_clksel_parent, 624 .recalc = &followparent_recalc,
645 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
646 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
647 .clksel = omap_96m_alwon_fck_clksel,
648 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
649 PARENT_CONTROLS_CLOCK,
650 .recalc = &omap2_clksel_recalc,
651}; 625};
652 626
653static struct clk omap_96m_fck = { 627static struct clk cm_96m_fck = {
654 .name = "omap_96m_fck", 628 .name = "cm_96m_fck",
629 .ops = &clkops_null,
655 .parent = &omap_96m_alwon_fck, 630 .parent = &omap_96m_alwon_fck,
656 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
657 PARENT_CONTROLS_CLOCK,
658 .recalc = &followparent_recalc, 631 .recalc = &followparent_recalc,
659}; 632};
660 633
661static const struct clksel cm_96m_fck_clksel[] = { 634static const struct clksel_rate omap_96m_dpll_rates[] = {
662 { .parent = &sys_ck, .rates = dpll_bypass_rates }, 635 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
663 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, 636 { .div = 0 }
637};
638
639static const struct clksel_rate omap_96m_sys_rates[] = {
640 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
641 { .div = 0 }
642};
643
644static const struct clksel omap_96m_fck_clksel[] = {
645 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
646 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
664 { .parent = NULL } 647 { .parent = NULL }
665}; 648};
666 649
667static struct clk cm_96m_fck = { 650static struct clk omap_96m_fck = {
668 .name = "cm_96m_fck", 651 .name = "omap_96m_fck",
669 .parent = &dpll4_m2x2_ck, 652 .ops = &clkops_null,
653 .parent = &sys_ck,
670 .init = &omap2_init_clksel_parent, 654 .init = &omap2_init_clksel_parent,
671 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 655 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
672 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, 656 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
673 .clksel = cm_96m_fck_clksel, 657 .clksel = omap_96m_fck_clksel,
674 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
675 PARENT_CONTROLS_CLOCK,
676 .recalc = &omap2_clksel_recalc, 658 .recalc = &omap2_clksel_recalc,
677}; 659};
678 660
679/* This virtual clock is the source for dpll4_m3x2_ck */ 661/* This virtual clock is the source for dpll4_m3x2_ck */
680static struct clk dpll4_m3_ck = { 662static struct clk dpll4_m3_ck = {
681 .name = "dpll4_m3_ck", 663 .name = "dpll4_m3_ck",
664 .ops = &clkops_null,
682 .parent = &dpll4_ck, 665 .parent = &dpll4_ck,
683 .init = &omap2_init_clksel_parent, 666 .init = &omap2_init_clksel_parent,
684 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 667 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
685 .clksel_mask = OMAP3430_CLKSEL_TV_MASK, 668 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
686 .clksel = div16_dpll4_clksel, 669 .clksel = div16_dpll4_clksel,
687 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 670 .clkdm_name = "dpll4_clkdm",
688 PARENT_CONTROLS_CLOCK,
689 .recalc = &omap2_clksel_recalc, 671 .recalc = &omap2_clksel_recalc,
690}; 672};
691 673
692/* The PWRDN bit is apparently only available on 3430ES2 and above */ 674/* The PWRDN bit is apparently only available on 3430ES2 and above */
693static struct clk dpll4_m3x2_ck = { 675static struct clk dpll4_m3x2_ck = {
694 .name = "dpll4_m3x2_ck", 676 .name = "dpll4_m3x2_ck",
677 .ops = &clkops_omap2_dflt_wait,
695 .parent = &dpll4_m3_ck, 678 .parent = &dpll4_m3_ck,
696 .init = &omap2_init_clksel_parent, 679 .init = &omap2_init_clksel_parent,
697 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 680 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
698 .enable_bit = OMAP3430_PWRDN_TV_SHIFT, 681 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
699 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 682 .flags = INVERT_ENABLE,
683 .clkdm_name = "dpll4_clkdm",
700 .recalc = &omap3_clkoutx2_recalc, 684 .recalc = &omap3_clkoutx2_recalc,
701}; 685};
702 686
703static const struct clksel virt_omap_54m_fck_clksel[] = {
704 { .parent = &sys_ck, .rates = dpll_bypass_rates },
705 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
706 { .parent = NULL }
707};
708
709static struct clk virt_omap_54m_fck = {
710 .name = "virt_omap_54m_fck",
711 .parent = &dpll4_m3x2_ck,
712 .init = &omap2_init_clksel_parent,
713 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
714 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
715 .clksel = virt_omap_54m_fck_clksel,
716 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
717 PARENT_CONTROLS_CLOCK,
718 .recalc = &omap2_clksel_recalc,
719};
720
721static const struct clksel_rate omap_54m_d4m3x2_rates[] = { 687static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
722 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 688 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
723 { .div = 0 } 689 { .div = 0 }
@@ -729,23 +695,22 @@ static const struct clksel_rate omap_54m_alt_rates[] = {
729}; 695};
730 696
731static const struct clksel omap_54m_clksel[] = { 697static const struct clksel omap_54m_clksel[] = {
732 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, 698 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
733 { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, 699 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
734 { .parent = NULL } 700 { .parent = NULL }
735}; 701};
736 702
737static struct clk omap_54m_fck = { 703static struct clk omap_54m_fck = {
738 .name = "omap_54m_fck", 704 .name = "omap_54m_fck",
705 .ops = &clkops_null,
739 .init = &omap2_init_clksel_parent, 706 .init = &omap2_init_clksel_parent,
740 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 707 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
741 .clksel_mask = OMAP3430_SOURCE_54M, 708 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
742 .clksel = omap_54m_clksel, 709 .clksel = omap_54m_clksel,
743 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
744 PARENT_CONTROLS_CLOCK,
745 .recalc = &omap2_clksel_recalc, 710 .recalc = &omap2_clksel_recalc,
746}; 711};
747 712
748static const struct clksel_rate omap_48m_96md2_rates[] = { 713static const struct clksel_rate omap_48m_cm96m_rates[] = {
749 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, 714 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
750 { .div = 0 } 715 { .div = 0 }
751}; 716};
@@ -756,106 +721,112 @@ static const struct clksel_rate omap_48m_alt_rates[] = {
756}; 721};
757 722
758static const struct clksel omap_48m_clksel[] = { 723static const struct clksel omap_48m_clksel[] = {
759 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, 724 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
760 { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, 725 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
761 { .parent = NULL } 726 { .parent = NULL }
762}; 727};
763 728
764static struct clk omap_48m_fck = { 729static struct clk omap_48m_fck = {
765 .name = "omap_48m_fck", 730 .name = "omap_48m_fck",
731 .ops = &clkops_null,
766 .init = &omap2_init_clksel_parent, 732 .init = &omap2_init_clksel_parent,
767 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 733 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
768 .clksel_mask = OMAP3430_SOURCE_48M, 734 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
769 .clksel = omap_48m_clksel, 735 .clksel = omap_48m_clksel,
770 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
771 PARENT_CONTROLS_CLOCK,
772 .recalc = &omap2_clksel_recalc, 736 .recalc = &omap2_clksel_recalc,
773}; 737};
774 738
775static struct clk omap_12m_fck = { 739static struct clk omap_12m_fck = {
776 .name = "omap_12m_fck", 740 .name = "omap_12m_fck",
741 .ops = &clkops_null,
777 .parent = &omap_48m_fck, 742 .parent = &omap_48m_fck,
778 .fixed_div = 4, 743 .fixed_div = 4,
779 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
780 PARENT_CONTROLS_CLOCK,
781 .recalc = &omap2_fixed_divisor_recalc, 744 .recalc = &omap2_fixed_divisor_recalc,
782}; 745};
783 746
784/* This virstual clock is the source for dpll4_m4x2_ck */ 747/* This virstual clock is the source for dpll4_m4x2_ck */
785static struct clk dpll4_m4_ck = { 748static struct clk dpll4_m4_ck = {
786 .name = "dpll4_m4_ck", 749 .name = "dpll4_m4_ck",
750 .ops = &clkops_null,
787 .parent = &dpll4_ck, 751 .parent = &dpll4_ck,
788 .init = &omap2_init_clksel_parent, 752 .init = &omap2_init_clksel_parent,
789 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), 753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
790 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, 754 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
791 .clksel = div16_dpll4_clksel, 755 .clksel = div16_dpll4_clksel,
792 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 756 .clkdm_name = "dpll4_clkdm",
793 PARENT_CONTROLS_CLOCK,
794 .recalc = &omap2_clksel_recalc, 757 .recalc = &omap2_clksel_recalc,
758 .set_rate = &omap2_clksel_set_rate,
759 .round_rate = &omap2_clksel_round_rate,
795}; 760};
796 761
797/* The PWRDN bit is apparently only available on 3430ES2 and above */ 762/* The PWRDN bit is apparently only available on 3430ES2 and above */
798static struct clk dpll4_m4x2_ck = { 763static struct clk dpll4_m4x2_ck = {
799 .name = "dpll4_m4x2_ck", 764 .name = "dpll4_m4x2_ck",
765 .ops = &clkops_omap2_dflt_wait,
800 .parent = &dpll4_m4_ck, 766 .parent = &dpll4_m4_ck,
801 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 767 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
802 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 768 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
803 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 769 .flags = INVERT_ENABLE,
770 .clkdm_name = "dpll4_clkdm",
804 .recalc = &omap3_clkoutx2_recalc, 771 .recalc = &omap3_clkoutx2_recalc,
805}; 772};
806 773
807/* This virtual clock is the source for dpll4_m5x2_ck */ 774/* This virtual clock is the source for dpll4_m5x2_ck */
808static struct clk dpll4_m5_ck = { 775static struct clk dpll4_m5_ck = {
809 .name = "dpll4_m5_ck", 776 .name = "dpll4_m5_ck",
777 .ops = &clkops_null,
810 .parent = &dpll4_ck, 778 .parent = &dpll4_ck,
811 .init = &omap2_init_clksel_parent, 779 .init = &omap2_init_clksel_parent,
812 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), 780 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
813 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, 781 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
814 .clksel = div16_dpll4_clksel, 782 .clksel = div16_dpll4_clksel,
815 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 783 .clkdm_name = "dpll4_clkdm",
816 PARENT_CONTROLS_CLOCK,
817 .recalc = &omap2_clksel_recalc, 784 .recalc = &omap2_clksel_recalc,
818}; 785};
819 786
820/* The PWRDN bit is apparently only available on 3430ES2 and above */ 787/* The PWRDN bit is apparently only available on 3430ES2 and above */
821static struct clk dpll4_m5x2_ck = { 788static struct clk dpll4_m5x2_ck = {
822 .name = "dpll4_m5x2_ck", 789 .name = "dpll4_m5x2_ck",
790 .ops = &clkops_omap2_dflt_wait,
823 .parent = &dpll4_m5_ck, 791 .parent = &dpll4_m5_ck,
824 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 792 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
825 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 793 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
826 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 794 .flags = INVERT_ENABLE,
795 .clkdm_name = "dpll4_clkdm",
827 .recalc = &omap3_clkoutx2_recalc, 796 .recalc = &omap3_clkoutx2_recalc,
828}; 797};
829 798
830/* This virtual clock is the source for dpll4_m6x2_ck */ 799/* This virtual clock is the source for dpll4_m6x2_ck */
831static struct clk dpll4_m6_ck = { 800static struct clk dpll4_m6_ck = {
832 .name = "dpll4_m6_ck", 801 .name = "dpll4_m6_ck",
802 .ops = &clkops_null,
833 .parent = &dpll4_ck, 803 .parent = &dpll4_ck,
834 .init = &omap2_init_clksel_parent, 804 .init = &omap2_init_clksel_parent,
835 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 805 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
836 .clksel_mask = OMAP3430_DIV_DPLL4_MASK, 806 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
837 .clksel = div16_dpll4_clksel, 807 .clksel = div16_dpll4_clksel,
838 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 808 .clkdm_name = "dpll4_clkdm",
839 PARENT_CONTROLS_CLOCK,
840 .recalc = &omap2_clksel_recalc, 809 .recalc = &omap2_clksel_recalc,
841}; 810};
842 811
843/* The PWRDN bit is apparently only available on 3430ES2 and above */ 812/* The PWRDN bit is apparently only available on 3430ES2 and above */
844static struct clk dpll4_m6x2_ck = { 813static struct clk dpll4_m6x2_ck = {
845 .name = "dpll4_m6x2_ck", 814 .name = "dpll4_m6x2_ck",
815 .ops = &clkops_omap2_dflt_wait,
846 .parent = &dpll4_m6_ck, 816 .parent = &dpll4_m6_ck,
847 .init = &omap2_init_clksel_parent, 817 .init = &omap2_init_clksel_parent,
848 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 818 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
849 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, 819 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
850 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, 820 .flags = INVERT_ENABLE,
821 .clkdm_name = "dpll4_clkdm",
851 .recalc = &omap3_clkoutx2_recalc, 822 .recalc = &omap3_clkoutx2_recalc,
852}; 823};
853 824
854static struct clk emu_per_alwon_ck = { 825static struct clk emu_per_alwon_ck = {
855 .name = "emu_per_alwon_ck", 826 .name = "emu_per_alwon_ck",
827 .ops = &clkops_null,
856 .parent = &dpll4_m6x2_ck, 828 .parent = &dpll4_m6x2_ck,
857 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 829 .clkdm_name = "dpll4_clkdm",
858 PARENT_CONTROLS_CLOCK,
859 .recalc = &followparent_recalc, 830 .recalc = &followparent_recalc,
860}; 831};
861 832
@@ -867,6 +838,9 @@ static struct dpll_data dpll5_dd = {
867 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), 838 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
868 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, 839 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
869 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 840 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
841 .clk_bypass = &sys_ck,
842 .clk_ref = &sys_ck,
843 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
870 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 844 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
871 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 845 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
872 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), 846 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
@@ -876,20 +850,21 @@ static struct dpll_data dpll5_dd = {
876 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), 850 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
877 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, 851 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
878 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), 852 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
879 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, 853 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
880 .max_multiplier = OMAP3_MAX_DPLL_MULT, 854 .max_multiplier = OMAP3_MAX_DPLL_MULT,
855 .min_divider = 1,
881 .max_divider = OMAP3_MAX_DPLL_DIV, 856 .max_divider = OMAP3_MAX_DPLL_DIV,
882 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE 857 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
883}; 858};
884 859
885static struct clk dpll5_ck = { 860static struct clk dpll5_ck = {
886 .name = "dpll5_ck", 861 .name = "dpll5_ck",
862 .ops = &clkops_noncore_dpll_ops,
887 .parent = &sys_ck, 863 .parent = &sys_ck,
888 .dpll_data = &dpll5_dd, 864 .dpll_data = &dpll5_dd,
889 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
890 .enable = &omap3_noncore_dpll_enable,
891 .disable = &omap3_noncore_dpll_disable,
892 .round_rate = &omap2_dpll_round_rate, 865 .round_rate = &omap2_dpll_round_rate,
866 .set_rate = &omap3_noncore_dpll_set_rate,
867 .clkdm_name = "dpll5_clkdm",
893 .recalc = &omap3_dpll_recalc, 868 .recalc = &omap3_dpll_recalc,
894}; 869};
895 870
@@ -900,31 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = {
900 875
901static struct clk dpll5_m2_ck = { 876static struct clk dpll5_m2_ck = {
902 .name = "dpll5_m2_ck", 877 .name = "dpll5_m2_ck",
878 .ops = &clkops_null,
903 .parent = &dpll5_ck, 879 .parent = &dpll5_ck,
904 .init = &omap2_init_clksel_parent, 880 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 881 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
906 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 882 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
907 .clksel = div16_dpll5_clksel, 883 .clksel = div16_dpll5_clksel,
908 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 884 .clkdm_name = "dpll5_clkdm",
909 PARENT_CONTROLS_CLOCK,
910 .recalc = &omap2_clksel_recalc,
911};
912
913static const struct clksel omap_120m_fck_clksel[] = {
914 { .parent = &sys_ck, .rates = dpll_bypass_rates },
915 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
916 { .parent = NULL }
917};
918
919static struct clk omap_120m_fck = {
920 .name = "omap_120m_fck",
921 .parent = &dpll5_m2_ck,
922 .init = &omap2_init_clksel_parent,
923 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .clksel = omap_120m_fck_clksel,
926 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
927 PARENT_CONTROLS_CLOCK,
928 .recalc = &omap2_clksel_recalc, 885 .recalc = &omap2_clksel_recalc,
929}; 886};
930 887
@@ -951,22 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
951}; 908};
952 909
953static const struct clksel clkout2_src_clksel[] = { 910static const struct clksel clkout2_src_clksel[] = {
954 { .parent = &core_ck, .rates = clkout2_src_core_rates }, 911 { .parent = &core_ck, .rates = clkout2_src_core_rates },
955 { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, 912 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
956 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, 913 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
957 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, 914 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
958 { .parent = NULL } 915 { .parent = NULL }
959}; 916};
960 917
961static struct clk clkout2_src_ck = { 918static struct clk clkout2_src_ck = {
962 .name = "clkout2_src_ck", 919 .name = "clkout2_src_ck",
920 .ops = &clkops_omap2_dflt,
963 .init = &omap2_init_clksel_parent, 921 .init = &omap2_init_clksel_parent,
964 .enable_reg = OMAP3430_CM_CLKOUT_CTRL, 922 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
965 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, 923 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
966 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 924 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
967 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, 925 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
968 .clksel = clkout2_src_clksel, 926 .clksel = clkout2_src_clksel,
969 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 927 .clkdm_name = "core_clkdm",
970 .recalc = &omap2_clksel_recalc, 928 .recalc = &omap2_clksel_recalc,
971}; 929};
972 930
@@ -986,11 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = {
986 944
987static struct clk sys_clkout2 = { 945static struct clk sys_clkout2 = {
988 .name = "sys_clkout2", 946 .name = "sys_clkout2",
947 .ops = &clkops_null,
989 .init = &omap2_init_clksel_parent, 948 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, 949 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
991 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, 950 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
992 .clksel = sys_clkout2_clksel, 951 .clksel = sys_clkout2_clksel,
993 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
994 .recalc = &omap2_clksel_recalc, 952 .recalc = &omap2_clksel_recalc,
995}; 953};
996 954
@@ -998,16 +956,22 @@ static struct clk sys_clkout2 = {
998 956
999static struct clk corex2_fck = { 957static struct clk corex2_fck = {
1000 .name = "corex2_fck", 958 .name = "corex2_fck",
959 .ops = &clkops_null,
1001 .parent = &dpll3_m2x2_ck, 960 .parent = &dpll3_m2x2_ck,
1002 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1003 PARENT_CONTROLS_CLOCK,
1004 .recalc = &followparent_recalc, 961 .recalc = &followparent_recalc,
1005}; 962};
1006 963
1007/* DPLL power domain clock controls */ 964/* DPLL power domain clock controls */
1008 965
1009static const struct clksel div2_core_clksel[] = { 966static const struct clksel_rate div4_rates[] = {
1010 { .parent = &core_ck, .rates = div2_rates }, 967 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_343X },
969 { .div = 4, .val = 4, .flags = RATE_IN_343X },
970 { .div = 0 }
971};
972
973static const struct clksel div4_core_clksel[] = {
974 { .parent = &core_ck, .rates = div4_rates },
1011 { .parent = NULL } 975 { .parent = NULL }
1012}; 976};
1013 977
@@ -1017,39 +981,21 @@ static const struct clksel div2_core_clksel[] = {
1017 */ 981 */
1018static struct clk dpll1_fck = { 982static struct clk dpll1_fck = {
1019 .name = "dpll1_fck", 983 .name = "dpll1_fck",
984 .ops = &clkops_null,
1020 .parent = &core_ck, 985 .parent = &core_ck,
1021 .init = &omap2_init_clksel_parent, 986 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1023 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, 988 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1024 .clksel = div2_core_clksel, 989 .clksel = div4_core_clksel,
1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026 PARENT_CONTROLS_CLOCK,
1027 .recalc = &omap2_clksel_recalc, 990 .recalc = &omap2_clksel_recalc,
1028}; 991};
1029 992
1030/*
1031 * MPU clksel:
1032 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1033 * derives from the high-frequency bypass clock originating from DPLL3,
1034 * called 'dpll1_fck'
1035 */
1036static const struct clksel mpu_clksel[] = {
1037 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1038 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1039 { .parent = NULL }
1040};
1041
1042static struct clk mpu_ck = { 993static struct clk mpu_ck = {
1043 .name = "mpu_ck", 994 .name = "mpu_ck",
995 .ops = &clkops_null,
1044 .parent = &dpll1_x2m2_ck, 996 .parent = &dpll1_x2m2_ck,
1045 .init = &omap2_init_clksel_parent,
1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1048 .clksel = mpu_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050 PARENT_CONTROLS_CLOCK,
1051 .clkdm_name = "mpu_clkdm", 997 .clkdm_name = "mpu_clkdm",
1052 .recalc = &omap2_clksel_recalc, 998 .recalc = &followparent_recalc,
1053}; 999};
1054 1000
1055/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ 1001/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
@@ -1066,13 +1012,12 @@ static const struct clksel arm_fck_clksel[] = {
1066 1012
1067static struct clk arm_fck = { 1013static struct clk arm_fck = {
1068 .name = "arm_fck", 1014 .name = "arm_fck",
1015 .ops = &clkops_null,
1069 .parent = &mpu_ck, 1016 .parent = &mpu_ck,
1070 .init = &omap2_init_clksel_parent, 1017 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), 1018 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1072 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, 1019 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1073 .clksel = arm_fck_clksel, 1020 .clksel = arm_fck_clksel,
1074 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1075 PARENT_CONTROLS_CLOCK,
1076 .recalc = &omap2_clksel_recalc, 1021 .recalc = &omap2_clksel_recalc,
1077}; 1022};
1078 1023
@@ -1084,63 +1029,48 @@ static struct clk arm_fck = {
1084 */ 1029 */
1085static struct clk emu_mpu_alwon_ck = { 1030static struct clk emu_mpu_alwon_ck = {
1086 .name = "emu_mpu_alwon_ck", 1031 .name = "emu_mpu_alwon_ck",
1032 .ops = &clkops_null,
1087 .parent = &mpu_ck, 1033 .parent = &mpu_ck,
1088 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1089 PARENT_CONTROLS_CLOCK,
1090 .recalc = &followparent_recalc, 1034 .recalc = &followparent_recalc,
1091}; 1035};
1092 1036
1093static struct clk dpll2_fck = { 1037static struct clk dpll2_fck = {
1094 .name = "dpll2_fck", 1038 .name = "dpll2_fck",
1039 .ops = &clkops_null,
1095 .parent = &core_ck, 1040 .parent = &core_ck,
1096 .init = &omap2_init_clksel_parent, 1041 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 1042 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1098 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, 1043 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1099 .clksel = div2_core_clksel, 1044 .clksel = div4_core_clksel,
1100 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1101 PARENT_CONTROLS_CLOCK,
1102 .recalc = &omap2_clksel_recalc, 1045 .recalc = &omap2_clksel_recalc,
1103}; 1046};
1104 1047
1105/*
1106 * IVA2 clksel:
1107 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1108 * derives from the high-frequency bypass clock originating from DPLL3,
1109 * called 'dpll2_fck'
1110 */
1111
1112static const struct clksel iva2_clksel[] = {
1113 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1114 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1115 { .parent = NULL }
1116};
1117
1118static struct clk iva2_ck = { 1048static struct clk iva2_ck = {
1119 .name = "iva2_ck", 1049 .name = "iva2_ck",
1050 .ops = &clkops_omap2_dflt_wait,
1120 .parent = &dpll2_m2_ck, 1051 .parent = &dpll2_m2_ck,
1121 .init = &omap2_init_clksel_parent, 1052 .init = &omap2_init_clksel_parent,
1122 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), 1053 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1123 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 1054 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1124 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1125 OMAP3430_CM_IDLEST_PLL),
1126 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1127 .clksel = iva2_clksel,
1128 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1129 .clkdm_name = "iva2_clkdm", 1055 .clkdm_name = "iva2_clkdm",
1130 .recalc = &omap2_clksel_recalc, 1056 .recalc = &followparent_recalc,
1131}; 1057};
1132 1058
1133/* Common interface clocks */ 1059/* Common interface clocks */
1134 1060
1061static const struct clksel div2_core_clksel[] = {
1062 { .parent = &core_ck, .rates = div2_rates },
1063 { .parent = NULL }
1064};
1065
1135static struct clk l3_ick = { 1066static struct clk l3_ick = {
1136 .name = "l3_ick", 1067 .name = "l3_ick",
1068 .ops = &clkops_null,
1137 .parent = &core_ck, 1069 .parent = &core_ck,
1138 .init = &omap2_init_clksel_parent, 1070 .init = &omap2_init_clksel_parent,
1139 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1071 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1140 .clksel_mask = OMAP3430_CLKSEL_L3_MASK, 1072 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1141 .clksel = div2_core_clksel, 1073 .clksel = div2_core_clksel,
1142 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1143 PARENT_CONTROLS_CLOCK,
1144 .clkdm_name = "core_l3_clkdm", 1074 .clkdm_name = "core_l3_clkdm",
1145 .recalc = &omap2_clksel_recalc, 1075 .recalc = &omap2_clksel_recalc,
1146}; 1076};
@@ -1152,13 +1082,12 @@ static const struct clksel div2_l3_clksel[] = {
1152 1082
1153static struct clk l4_ick = { 1083static struct clk l4_ick = {
1154 .name = "l4_ick", 1084 .name = "l4_ick",
1085 .ops = &clkops_null,
1155 .parent = &l3_ick, 1086 .parent = &l3_ick,
1156 .init = &omap2_init_clksel_parent, 1087 .init = &omap2_init_clksel_parent,
1157 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1088 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1158 .clksel_mask = OMAP3430_CLKSEL_L4_MASK, 1089 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1159 .clksel = div2_l3_clksel, 1090 .clksel = div2_l3_clksel,
1160 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1161 PARENT_CONTROLS_CLOCK,
1162 .clkdm_name = "core_l4_clkdm", 1091 .clkdm_name = "core_l4_clkdm",
1163 .recalc = &omap2_clksel_recalc, 1092 .recalc = &omap2_clksel_recalc,
1164 1093
@@ -1171,12 +1100,12 @@ static const struct clksel div2_l4_clksel[] = {
1171 1100
1172static struct clk rm_ick = { 1101static struct clk rm_ick = {
1173 .name = "rm_ick", 1102 .name = "rm_ick",
1103 .ops = &clkops_null,
1174 .parent = &l4_ick, 1104 .parent = &l4_ick,
1175 .init = &omap2_init_clksel_parent, 1105 .init = &omap2_init_clksel_parent,
1176 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 1106 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1177 .clksel_mask = OMAP3430_CLKSEL_RM_MASK, 1107 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1178 .clksel = div2_l4_clksel, 1108 .clksel = div2_l4_clksel,
1179 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1180 .recalc = &omap2_clksel_recalc, 1109 .recalc = &omap2_clksel_recalc,
1181}; 1110};
1182 1111
@@ -1192,53 +1121,52 @@ static const struct clksel gfx_l3_clksel[] = {
1192/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1121/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1193static struct clk gfx_l3_ck = { 1122static struct clk gfx_l3_ck = {
1194 .name = "gfx_l3_ck", 1123 .name = "gfx_l3_ck",
1124 .ops = &clkops_omap2_dflt_wait,
1195 .parent = &l3_ick, 1125 .parent = &l3_ick,
1196 .init = &omap2_init_clksel_parent, 1126 .init = &omap2_init_clksel_parent,
1197 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), 1127 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1198 .enable_bit = OMAP_EN_GFX_SHIFT, 1128 .enable_bit = OMAP_EN_GFX_SHIFT,
1199 .flags = CLOCK_IN_OMAP3430ES1,
1200 .recalc = &followparent_recalc, 1129 .recalc = &followparent_recalc,
1201}; 1130};
1202 1131
1203static struct clk gfx_l3_fck = { 1132static struct clk gfx_l3_fck = {
1204 .name = "gfx_l3_fck", 1133 .name = "gfx_l3_fck",
1134 .ops = &clkops_null,
1205 .parent = &gfx_l3_ck, 1135 .parent = &gfx_l3_ck,
1206 .init = &omap2_init_clksel_parent, 1136 .init = &omap2_init_clksel_parent,
1207 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), 1137 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1208 .clksel_mask = OMAP_CLKSEL_GFX_MASK, 1138 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1209 .clksel = gfx_l3_clksel, 1139 .clksel = gfx_l3_clksel,
1210 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
1211 PARENT_CONTROLS_CLOCK,
1212 .clkdm_name = "gfx_3430es1_clkdm", 1140 .clkdm_name = "gfx_3430es1_clkdm",
1213 .recalc = &omap2_clksel_recalc, 1141 .recalc = &omap2_clksel_recalc,
1214}; 1142};
1215 1143
1216static struct clk gfx_l3_ick = { 1144static struct clk gfx_l3_ick = {
1217 .name = "gfx_l3_ick", 1145 .name = "gfx_l3_ick",
1146 .ops = &clkops_null,
1218 .parent = &gfx_l3_ck, 1147 .parent = &gfx_l3_ck,
1219 .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
1220 .clkdm_name = "gfx_3430es1_clkdm", 1148 .clkdm_name = "gfx_3430es1_clkdm",
1221 .recalc = &followparent_recalc, 1149 .recalc = &followparent_recalc,
1222}; 1150};
1223 1151
1224static struct clk gfx_cg1_ck = { 1152static struct clk gfx_cg1_ck = {
1225 .name = "gfx_cg1_ck", 1153 .name = "gfx_cg1_ck",
1154 .ops = &clkops_omap2_dflt_wait,
1226 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1155 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1227 .init = &omap2_init_clk_clkdm, 1156 .init = &omap2_init_clk_clkdm,
1228 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1157 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1229 .enable_bit = OMAP3430ES1_EN_2D_SHIFT, 1158 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1230 .flags = CLOCK_IN_OMAP3430ES1,
1231 .clkdm_name = "gfx_3430es1_clkdm", 1159 .clkdm_name = "gfx_3430es1_clkdm",
1232 .recalc = &followparent_recalc, 1160 .recalc = &followparent_recalc,
1233}; 1161};
1234 1162
1235static struct clk gfx_cg2_ck = { 1163static struct clk gfx_cg2_ck = {
1236 .name = "gfx_cg2_ck", 1164 .name = "gfx_cg2_ck",
1165 .ops = &clkops_omap2_dflt_wait,
1237 .parent = &gfx_l3_fck, /* REVISIT: correct? */ 1166 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1238 .init = &omap2_init_clk_clkdm, 1167 .init = &omap2_init_clk_clkdm,
1239 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 1168 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1240 .enable_bit = OMAP3430ES1_EN_3D_SHIFT, 1169 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1241 .flags = CLOCK_IN_OMAP3430ES1,
1242 .clkdm_name = "gfx_3430es1_clkdm", 1170 .clkdm_name = "gfx_3430es1_clkdm",
1243 .recalc = &followparent_recalc, 1171 .recalc = &followparent_recalc,
1244}; 1172};
@@ -1265,24 +1193,24 @@ static const struct clksel sgx_clksel[] = {
1265 1193
1266static struct clk sgx_fck = { 1194static struct clk sgx_fck = {
1267 .name = "sgx_fck", 1195 .name = "sgx_fck",
1196 .ops = &clkops_omap2_dflt_wait,
1268 .init = &omap2_init_clksel_parent, 1197 .init = &omap2_init_clksel_parent,
1269 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), 1198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1270 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1199 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1271 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), 1200 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1272 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, 1201 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1273 .clksel = sgx_clksel, 1202 .clksel = sgx_clksel,
1274 .flags = CLOCK_IN_OMAP3430ES2,
1275 .clkdm_name = "sgx_clkdm", 1203 .clkdm_name = "sgx_clkdm",
1276 .recalc = &omap2_clksel_recalc, 1204 .recalc = &omap2_clksel_recalc,
1277}; 1205};
1278 1206
1279static struct clk sgx_ick = { 1207static struct clk sgx_ick = {
1280 .name = "sgx_ick", 1208 .name = "sgx_ick",
1209 .ops = &clkops_omap2_dflt_wait,
1281 .parent = &l3_ick, 1210 .parent = &l3_ick,
1282 .init = &omap2_init_clk_clkdm, 1211 .init = &omap2_init_clk_clkdm,
1283 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), 1212 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1284 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, 1213 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1285 .flags = CLOCK_IN_OMAP3430ES2,
1286 .clkdm_name = "sgx_clkdm", 1214 .clkdm_name = "sgx_clkdm",
1287 .recalc = &followparent_recalc, 1215 .recalc = &followparent_recalc,
1288}; 1216};
@@ -1291,11 +1219,11 @@ static struct clk sgx_ick = {
1291 1219
1292static struct clk d2d_26m_fck = { 1220static struct clk d2d_26m_fck = {
1293 .name = "d2d_26m_fck", 1221 .name = "d2d_26m_fck",
1222 .ops = &clkops_omap2_dflt_wait,
1294 .parent = &sys_ck, 1223 .parent = &sys_ck,
1295 .init = &omap2_init_clk_clkdm, 1224 .init = &omap2_init_clk_clkdm,
1296 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1297 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, 1226 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1298 .flags = CLOCK_IN_OMAP3430ES1,
1299 .clkdm_name = "d2d_clkdm", 1227 .clkdm_name = "d2d_clkdm",
1300 .recalc = &followparent_recalc, 1228 .recalc = &followparent_recalc,
1301}; 1229};
@@ -1308,6 +1236,7 @@ static const struct clksel omap343x_gpt_clksel[] = {
1308 1236
1309static struct clk gpt10_fck = { 1237static struct clk gpt10_fck = {
1310 .name = "gpt10_fck", 1238 .name = "gpt10_fck",
1239 .ops = &clkops_omap2_dflt_wait,
1311 .parent = &sys_ck, 1240 .parent = &sys_ck,
1312 .init = &omap2_init_clksel_parent, 1241 .init = &omap2_init_clksel_parent,
1313 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1315,13 +1244,13 @@ static struct clk gpt10_fck = {
1315 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1244 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1316 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, 1245 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1317 .clksel = omap343x_gpt_clksel, 1246 .clksel = omap343x_gpt_clksel,
1318 .flags = CLOCK_IN_OMAP343X,
1319 .clkdm_name = "core_l4_clkdm", 1247 .clkdm_name = "core_l4_clkdm",
1320 .recalc = &omap2_clksel_recalc, 1248 .recalc = &omap2_clksel_recalc,
1321}; 1249};
1322 1250
1323static struct clk gpt11_fck = { 1251static struct clk gpt11_fck = {
1324 .name = "gpt11_fck", 1252 .name = "gpt11_fck",
1253 .ops = &clkops_omap2_dflt_wait,
1325 .parent = &sys_ck, 1254 .parent = &sys_ck,
1326 .init = &omap2_init_clksel_parent, 1255 .init = &omap2_init_clksel_parent,
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1329,35 +1258,34 @@ static struct clk gpt11_fck = {
1329 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1258 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1330 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, 1259 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1331 .clksel = omap343x_gpt_clksel, 1260 .clksel = omap343x_gpt_clksel,
1332 .flags = CLOCK_IN_OMAP343X,
1333 .clkdm_name = "core_l4_clkdm", 1261 .clkdm_name = "core_l4_clkdm",
1334 .recalc = &omap2_clksel_recalc, 1262 .recalc = &omap2_clksel_recalc,
1335}; 1263};
1336 1264
1337static struct clk cpefuse_fck = { 1265static struct clk cpefuse_fck = {
1338 .name = "cpefuse_fck", 1266 .name = "cpefuse_fck",
1267 .ops = &clkops_omap2_dflt,
1339 .parent = &sys_ck, 1268 .parent = &sys_ck,
1340 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1341 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, 1270 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1342 .flags = CLOCK_IN_OMAP3430ES2,
1343 .recalc = &followparent_recalc, 1271 .recalc = &followparent_recalc,
1344}; 1272};
1345 1273
1346static struct clk ts_fck = { 1274static struct clk ts_fck = {
1347 .name = "ts_fck", 1275 .name = "ts_fck",
1276 .ops = &clkops_omap2_dflt,
1348 .parent = &omap_32k_fck, 1277 .parent = &omap_32k_fck,
1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1350 .enable_bit = OMAP3430ES2_EN_TS_SHIFT, 1279 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1351 .flags = CLOCK_IN_OMAP3430ES2,
1352 .recalc = &followparent_recalc, 1280 .recalc = &followparent_recalc,
1353}; 1281};
1354 1282
1355static struct clk usbtll_fck = { 1283static struct clk usbtll_fck = {
1356 .name = "usbtll_fck", 1284 .name = "usbtll_fck",
1357 .parent = &omap_120m_fck, 1285 .ops = &clkops_omap2_dflt,
1286 .parent = &dpll5_m2_ck,
1358 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), 1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1359 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1288 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1360 .flags = CLOCK_IN_OMAP3430ES2,
1361 .recalc = &followparent_recalc, 1289 .recalc = &followparent_recalc,
1362}; 1290};
1363 1291
@@ -1365,84 +1293,83 @@ static struct clk usbtll_fck = {
1365 1293
1366static struct clk core_96m_fck = { 1294static struct clk core_96m_fck = {
1367 .name = "core_96m_fck", 1295 .name = "core_96m_fck",
1296 .ops = &clkops_null,
1368 .parent = &omap_96m_fck, 1297 .parent = &omap_96m_fck,
1369 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1370 PARENT_CONTROLS_CLOCK,
1371 .clkdm_name = "core_l4_clkdm", 1298 .clkdm_name = "core_l4_clkdm",
1372 .recalc = &followparent_recalc, 1299 .recalc = &followparent_recalc,
1373}; 1300};
1374 1301
1375static struct clk mmchs3_fck = { 1302static struct clk mmchs3_fck = {
1376 .name = "mmchs_fck", 1303 .name = "mmchs_fck",
1304 .ops = &clkops_omap2_dflt_wait,
1377 .id = 2, 1305 .id = 2,
1378 .parent = &core_96m_fck, 1306 .parent = &core_96m_fck,
1379 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1380 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1308 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1381 .flags = CLOCK_IN_OMAP3430ES2,
1382 .clkdm_name = "core_l4_clkdm", 1309 .clkdm_name = "core_l4_clkdm",
1383 .recalc = &followparent_recalc, 1310 .recalc = &followparent_recalc,
1384}; 1311};
1385 1312
1386static struct clk mmchs2_fck = { 1313static struct clk mmchs2_fck = {
1387 .name = "mmchs_fck", 1314 .name = "mmchs_fck",
1315 .ops = &clkops_omap2_dflt_wait,
1388 .id = 1, 1316 .id = 1,
1389 .parent = &core_96m_fck, 1317 .parent = &core_96m_fck,
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1391 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1319 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1392 .flags = CLOCK_IN_OMAP343X,
1393 .clkdm_name = "core_l4_clkdm", 1320 .clkdm_name = "core_l4_clkdm",
1394 .recalc = &followparent_recalc, 1321 .recalc = &followparent_recalc,
1395}; 1322};
1396 1323
1397static struct clk mspro_fck = { 1324static struct clk mspro_fck = {
1398 .name = "mspro_fck", 1325 .name = "mspro_fck",
1326 .ops = &clkops_omap2_dflt_wait,
1399 .parent = &core_96m_fck, 1327 .parent = &core_96m_fck,
1400 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1401 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1329 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1402 .flags = CLOCK_IN_OMAP343X,
1403 .clkdm_name = "core_l4_clkdm", 1330 .clkdm_name = "core_l4_clkdm",
1404 .recalc = &followparent_recalc, 1331 .recalc = &followparent_recalc,
1405}; 1332};
1406 1333
1407static struct clk mmchs1_fck = { 1334static struct clk mmchs1_fck = {
1408 .name = "mmchs_fck", 1335 .name = "mmchs_fck",
1336 .ops = &clkops_omap2_dflt_wait,
1409 .parent = &core_96m_fck, 1337 .parent = &core_96m_fck,
1410 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1411 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1339 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1412 .flags = CLOCK_IN_OMAP343X,
1413 .clkdm_name = "core_l4_clkdm", 1340 .clkdm_name = "core_l4_clkdm",
1414 .recalc = &followparent_recalc, 1341 .recalc = &followparent_recalc,
1415}; 1342};
1416 1343
1417static struct clk i2c3_fck = { 1344static struct clk i2c3_fck = {
1418 .name = "i2c_fck", 1345 .name = "i2c_fck",
1346 .ops = &clkops_omap2_dflt_wait,
1419 .id = 3, 1347 .id = 3,
1420 .parent = &core_96m_fck, 1348 .parent = &core_96m_fck,
1421 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1422 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1350 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1423 .flags = CLOCK_IN_OMAP343X,
1424 .clkdm_name = "core_l4_clkdm", 1351 .clkdm_name = "core_l4_clkdm",
1425 .recalc = &followparent_recalc, 1352 .recalc = &followparent_recalc,
1426}; 1353};
1427 1354
1428static struct clk i2c2_fck = { 1355static struct clk i2c2_fck = {
1429 .name = "i2c_fck", 1356 .name = "i2c_fck",
1357 .ops = &clkops_omap2_dflt_wait,
1430 .id = 2, 1358 .id = 2,
1431 .parent = &core_96m_fck, 1359 .parent = &core_96m_fck,
1432 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1361 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1434 .flags = CLOCK_IN_OMAP343X,
1435 .clkdm_name = "core_l4_clkdm", 1362 .clkdm_name = "core_l4_clkdm",
1436 .recalc = &followparent_recalc, 1363 .recalc = &followparent_recalc,
1437}; 1364};
1438 1365
1439static struct clk i2c1_fck = { 1366static struct clk i2c1_fck = {
1440 .name = "i2c_fck", 1367 .name = "i2c_fck",
1368 .ops = &clkops_omap2_dflt_wait,
1441 .id = 1, 1369 .id = 1,
1442 .parent = &core_96m_fck, 1370 .parent = &core_96m_fck,
1443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1372 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1445 .flags = CLOCK_IN_OMAP343X,
1446 .clkdm_name = "core_l4_clkdm", 1373 .clkdm_name = "core_l4_clkdm",
1447 .recalc = &followparent_recalc, 1374 .recalc = &followparent_recalc,
1448}; 1375};
@@ -1469,6 +1396,7 @@ static const struct clksel mcbsp_15_clksel[] = {
1469 1396
1470static struct clk mcbsp5_fck = { 1397static struct clk mcbsp5_fck = {
1471 .name = "mcbsp_fck", 1398 .name = "mcbsp_fck",
1399 .ops = &clkops_omap2_dflt_wait,
1472 .id = 5, 1400 .id = 5,
1473 .init = &omap2_init_clksel_parent, 1401 .init = &omap2_init_clksel_parent,
1474 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1476,13 +1404,13 @@ static struct clk mcbsp5_fck = {
1476 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 1404 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1477 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, 1405 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1478 .clksel = mcbsp_15_clksel, 1406 .clksel = mcbsp_15_clksel,
1479 .flags = CLOCK_IN_OMAP343X,
1480 .clkdm_name = "core_l4_clkdm", 1407 .clkdm_name = "core_l4_clkdm",
1481 .recalc = &omap2_clksel_recalc, 1408 .recalc = &omap2_clksel_recalc,
1482}; 1409};
1483 1410
1484static struct clk mcbsp1_fck = { 1411static struct clk mcbsp1_fck = {
1485 .name = "mcbsp_fck", 1412 .name = "mcbsp_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1486 .id = 1, 1414 .id = 1,
1487 .init = &omap2_init_clksel_parent, 1415 .init = &omap2_init_clksel_parent,
1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1490,7 +1418,6 @@ static struct clk mcbsp1_fck = {
1490 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 1418 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1491 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, 1419 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1492 .clksel = mcbsp_15_clksel, 1420 .clksel = mcbsp_15_clksel,
1493 .flags = CLOCK_IN_OMAP343X,
1494 .clkdm_name = "core_l4_clkdm", 1421 .clkdm_name = "core_l4_clkdm",
1495 .recalc = &omap2_clksel_recalc, 1422 .recalc = &omap2_clksel_recalc,
1496}; 1423};
@@ -1499,77 +1426,76 @@ static struct clk mcbsp1_fck = {
1499 1426
1500static struct clk core_48m_fck = { 1427static struct clk core_48m_fck = {
1501 .name = "core_48m_fck", 1428 .name = "core_48m_fck",
1429 .ops = &clkops_null,
1502 .parent = &omap_48m_fck, 1430 .parent = &omap_48m_fck,
1503 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1504 PARENT_CONTROLS_CLOCK,
1505 .clkdm_name = "core_l4_clkdm", 1431 .clkdm_name = "core_l4_clkdm",
1506 .recalc = &followparent_recalc, 1432 .recalc = &followparent_recalc,
1507}; 1433};
1508 1434
1509static struct clk mcspi4_fck = { 1435static struct clk mcspi4_fck = {
1510 .name = "mcspi_fck", 1436 .name = "mcspi_fck",
1437 .ops = &clkops_omap2_dflt_wait,
1511 .id = 4, 1438 .id = 4,
1512 .parent = &core_48m_fck, 1439 .parent = &core_48m_fck,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1441 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1515 .flags = CLOCK_IN_OMAP343X,
1516 .recalc = &followparent_recalc, 1442 .recalc = &followparent_recalc,
1517}; 1443};
1518 1444
1519static struct clk mcspi3_fck = { 1445static struct clk mcspi3_fck = {
1520 .name = "mcspi_fck", 1446 .name = "mcspi_fck",
1447 .ops = &clkops_omap2_dflt_wait,
1521 .id = 3, 1448 .id = 3,
1522 .parent = &core_48m_fck, 1449 .parent = &core_48m_fck,
1523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1451 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1525 .flags = CLOCK_IN_OMAP343X,
1526 .recalc = &followparent_recalc, 1452 .recalc = &followparent_recalc,
1527}; 1453};
1528 1454
1529static struct clk mcspi2_fck = { 1455static struct clk mcspi2_fck = {
1530 .name = "mcspi_fck", 1456 .name = "mcspi_fck",
1457 .ops = &clkops_omap2_dflt_wait,
1531 .id = 2, 1458 .id = 2,
1532 .parent = &core_48m_fck, 1459 .parent = &core_48m_fck,
1533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1461 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1535 .flags = CLOCK_IN_OMAP343X,
1536 .recalc = &followparent_recalc, 1462 .recalc = &followparent_recalc,
1537}; 1463};
1538 1464
1539static struct clk mcspi1_fck = { 1465static struct clk mcspi1_fck = {
1540 .name = "mcspi_fck", 1466 .name = "mcspi_fck",
1467 .ops = &clkops_omap2_dflt_wait,
1541 .id = 1, 1468 .id = 1,
1542 .parent = &core_48m_fck, 1469 .parent = &core_48m_fck,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1544 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1471 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1545 .flags = CLOCK_IN_OMAP343X,
1546 .recalc = &followparent_recalc, 1472 .recalc = &followparent_recalc,
1547}; 1473};
1548 1474
1549static struct clk uart2_fck = { 1475static struct clk uart2_fck = {
1550 .name = "uart2_fck", 1476 .name = "uart2_fck",
1477 .ops = &clkops_omap2_dflt_wait,
1551 .parent = &core_48m_fck, 1478 .parent = &core_48m_fck,
1552 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1479 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1553 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1480 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1554 .flags = CLOCK_IN_OMAP343X,
1555 .recalc = &followparent_recalc, 1481 .recalc = &followparent_recalc,
1556}; 1482};
1557 1483
1558static struct clk uart1_fck = { 1484static struct clk uart1_fck = {
1559 .name = "uart1_fck", 1485 .name = "uart1_fck",
1486 .ops = &clkops_omap2_dflt_wait,
1560 .parent = &core_48m_fck, 1487 .parent = &core_48m_fck,
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1562 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1489 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1563 .flags = CLOCK_IN_OMAP343X,
1564 .recalc = &followparent_recalc, 1490 .recalc = &followparent_recalc,
1565}; 1491};
1566 1492
1567static struct clk fshostusb_fck = { 1493static struct clk fshostusb_fck = {
1568 .name = "fshostusb_fck", 1494 .name = "fshostusb_fck",
1495 .ops = &clkops_omap2_dflt_wait,
1569 .parent = &core_48m_fck, 1496 .parent = &core_48m_fck,
1570 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1571 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, 1498 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1572 .flags = CLOCK_IN_OMAP3430ES1,
1573 .recalc = &followparent_recalc, 1499 .recalc = &followparent_recalc,
1574}; 1500};
1575 1501
@@ -1577,19 +1503,18 @@ static struct clk fshostusb_fck = {
1577 1503
1578static struct clk core_12m_fck = { 1504static struct clk core_12m_fck = {
1579 .name = "core_12m_fck", 1505 .name = "core_12m_fck",
1506 .ops = &clkops_null,
1580 .parent = &omap_12m_fck, 1507 .parent = &omap_12m_fck,
1581 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1582 PARENT_CONTROLS_CLOCK,
1583 .clkdm_name = "core_l4_clkdm", 1508 .clkdm_name = "core_l4_clkdm",
1584 .recalc = &followparent_recalc, 1509 .recalc = &followparent_recalc,
1585}; 1510};
1586 1511
1587static struct clk hdq_fck = { 1512static struct clk hdq_fck = {
1588 .name = "hdq_fck", 1513 .name = "hdq_fck",
1514 .ops = &clkops_omap2_dflt_wait,
1589 .parent = &core_12m_fck, 1515 .parent = &core_12m_fck,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1591 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1517 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1592 .flags = CLOCK_IN_OMAP343X,
1593 .recalc = &followparent_recalc, 1518 .recalc = &followparent_recalc,
1594}; 1519};
1595 1520
@@ -1612,22 +1537,22 @@ static const struct clksel ssi_ssr_clksel[] = {
1612 1537
1613static struct clk ssi_ssr_fck = { 1538static struct clk ssi_ssr_fck = {
1614 .name = "ssi_ssr_fck", 1539 .name = "ssi_ssr_fck",
1540 .ops = &clkops_omap2_dflt,
1615 .init = &omap2_init_clksel_parent, 1541 .init = &omap2_init_clksel_parent,
1616 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1617 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1543 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1618 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1619 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, 1545 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1620 .clksel = ssi_ssr_clksel, 1546 .clksel = ssi_ssr_clksel,
1621 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1622 .clkdm_name = "core_l4_clkdm", 1547 .clkdm_name = "core_l4_clkdm",
1623 .recalc = &omap2_clksel_recalc, 1548 .recalc = &omap2_clksel_recalc,
1624}; 1549};
1625 1550
1626static struct clk ssi_sst_fck = { 1551static struct clk ssi_sst_fck = {
1627 .name = "ssi_sst_fck", 1552 .name = "ssi_sst_fck",
1553 .ops = &clkops_null,
1628 .parent = &ssi_ssr_fck, 1554 .parent = &ssi_ssr_fck,
1629 .fixed_div = 2, 1555 .fixed_div = 2,
1630 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1631 .recalc = &omap2_fixed_divisor_recalc, 1556 .recalc = &omap2_fixed_divisor_recalc,
1632}; 1557};
1633 1558
@@ -1641,39 +1566,39 @@ static struct clk ssi_sst_fck = {
1641 */ 1566 */
1642static struct clk core_l3_ick = { 1567static struct clk core_l3_ick = {
1643 .name = "core_l3_ick", 1568 .name = "core_l3_ick",
1569 .ops = &clkops_null,
1644 .parent = &l3_ick, 1570 .parent = &l3_ick,
1645 .init = &omap2_init_clk_clkdm, 1571 .init = &omap2_init_clk_clkdm,
1646 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1647 PARENT_CONTROLS_CLOCK,
1648 .clkdm_name = "core_l3_clkdm", 1572 .clkdm_name = "core_l3_clkdm",
1649 .recalc = &followparent_recalc, 1573 .recalc = &followparent_recalc,
1650}; 1574};
1651 1575
1652static struct clk hsotgusb_ick = { 1576static struct clk hsotgusb_ick = {
1653 .name = "hsotgusb_ick", 1577 .name = "hsotgusb_ick",
1578 .ops = &clkops_omap2_dflt_wait,
1654 .parent = &core_l3_ick, 1579 .parent = &core_l3_ick,
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1656 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1581 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1657 .flags = CLOCK_IN_OMAP343X,
1658 .clkdm_name = "core_l3_clkdm", 1582 .clkdm_name = "core_l3_clkdm",
1659 .recalc = &followparent_recalc, 1583 .recalc = &followparent_recalc,
1660}; 1584};
1661 1585
1662static struct clk sdrc_ick = { 1586static struct clk sdrc_ick = {
1663 .name = "sdrc_ick", 1587 .name = "sdrc_ick",
1588 .ops = &clkops_omap2_dflt_wait,
1664 .parent = &core_l3_ick, 1589 .parent = &core_l3_ick,
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1666 .enable_bit = OMAP3430_EN_SDRC_SHIFT, 1591 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1667 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1592 .flags = ENABLE_ON_INIT,
1668 .clkdm_name = "core_l3_clkdm", 1593 .clkdm_name = "core_l3_clkdm",
1669 .recalc = &followparent_recalc, 1594 .recalc = &followparent_recalc,
1670}; 1595};
1671 1596
1672static struct clk gpmc_fck = { 1597static struct clk gpmc_fck = {
1673 .name = "gpmc_fck", 1598 .name = "gpmc_fck",
1599 .ops = &clkops_null,
1674 .parent = &core_l3_ick, 1600 .parent = &core_l3_ick,
1675 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | 1601 .flags = ENABLE_ON_INIT, /* huh? */
1676 ENABLE_ON_INIT,
1677 .clkdm_name = "core_l3_clkdm", 1602 .clkdm_name = "core_l3_clkdm",
1678 .recalc = &followparent_recalc, 1603 .recalc = &followparent_recalc,
1679}; 1604};
@@ -1682,18 +1607,17 @@ static struct clk gpmc_fck = {
1682 1607
1683static struct clk security_l3_ick = { 1608static struct clk security_l3_ick = {
1684 .name = "security_l3_ick", 1609 .name = "security_l3_ick",
1610 .ops = &clkops_null,
1685 .parent = &l3_ick, 1611 .parent = &l3_ick,
1686 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1687 PARENT_CONTROLS_CLOCK,
1688 .recalc = &followparent_recalc, 1612 .recalc = &followparent_recalc,
1689}; 1613};
1690 1614
1691static struct clk pka_ick = { 1615static struct clk pka_ick = {
1692 .name = "pka_ick", 1616 .name = "pka_ick",
1617 .ops = &clkops_omap2_dflt_wait,
1693 .parent = &security_l3_ick, 1618 .parent = &security_l3_ick,
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1695 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1620 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1696 .flags = CLOCK_IN_OMAP343X,
1697 .recalc = &followparent_recalc, 1621 .recalc = &followparent_recalc,
1698}; 1622};
1699 1623
@@ -1701,31 +1625,30 @@ static struct clk pka_ick = {
1701 1625
1702static struct clk core_l4_ick = { 1626static struct clk core_l4_ick = {
1703 .name = "core_l4_ick", 1627 .name = "core_l4_ick",
1628 .ops = &clkops_null,
1704 .parent = &l4_ick, 1629 .parent = &l4_ick,
1705 .init = &omap2_init_clk_clkdm, 1630 .init = &omap2_init_clk_clkdm,
1706 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1707 PARENT_CONTROLS_CLOCK,
1708 .clkdm_name = "core_l4_clkdm", 1631 .clkdm_name = "core_l4_clkdm",
1709 .recalc = &followparent_recalc, 1632 .recalc = &followparent_recalc,
1710}; 1633};
1711 1634
1712static struct clk usbtll_ick = { 1635static struct clk usbtll_ick = {
1713 .name = "usbtll_ick", 1636 .name = "usbtll_ick",
1637 .ops = &clkops_omap2_dflt_wait,
1714 .parent = &core_l4_ick, 1638 .parent = &core_l4_ick,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1716 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1640 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1717 .flags = CLOCK_IN_OMAP3430ES2,
1718 .clkdm_name = "core_l4_clkdm", 1641 .clkdm_name = "core_l4_clkdm",
1719 .recalc = &followparent_recalc, 1642 .recalc = &followparent_recalc,
1720}; 1643};
1721 1644
1722static struct clk mmchs3_ick = { 1645static struct clk mmchs3_ick = {
1723 .name = "mmchs_ick", 1646 .name = "mmchs_ick",
1647 .ops = &clkops_omap2_dflt_wait,
1724 .id = 2, 1648 .id = 2,
1725 .parent = &core_l4_ick, 1649 .parent = &core_l4_ick,
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1651 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1728 .flags = CLOCK_IN_OMAP3430ES2,
1729 .clkdm_name = "core_l4_clkdm", 1652 .clkdm_name = "core_l4_clkdm",
1730 .recalc = &followparent_recalc, 1653 .recalc = &followparent_recalc,
1731}; 1654};
@@ -1733,250 +1656,251 @@ static struct clk mmchs3_ick = {
1733/* Intersystem Communication Registers - chassis mode only */ 1656/* Intersystem Communication Registers - chassis mode only */
1734static struct clk icr_ick = { 1657static struct clk icr_ick = {
1735 .name = "icr_ick", 1658 .name = "icr_ick",
1659 .ops = &clkops_omap2_dflt_wait,
1736 .parent = &core_l4_ick, 1660 .parent = &core_l4_ick,
1737 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1662 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1739 .flags = CLOCK_IN_OMAP343X,
1740 .clkdm_name = "core_l4_clkdm", 1663 .clkdm_name = "core_l4_clkdm",
1741 .recalc = &followparent_recalc, 1664 .recalc = &followparent_recalc,
1742}; 1665};
1743 1666
1744static struct clk aes2_ick = { 1667static struct clk aes2_ick = {
1745 .name = "aes2_ick", 1668 .name = "aes2_ick",
1669 .ops = &clkops_omap2_dflt_wait,
1746 .parent = &core_l4_ick, 1670 .parent = &core_l4_ick,
1747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1672 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1749 .flags = CLOCK_IN_OMAP343X,
1750 .clkdm_name = "core_l4_clkdm", 1673 .clkdm_name = "core_l4_clkdm",
1751 .recalc = &followparent_recalc, 1674 .recalc = &followparent_recalc,
1752}; 1675};
1753 1676
1754static struct clk sha12_ick = { 1677static struct clk sha12_ick = {
1755 .name = "sha12_ick", 1678 .name = "sha12_ick",
1679 .ops = &clkops_omap2_dflt_wait,
1756 .parent = &core_l4_ick, 1680 .parent = &core_l4_ick,
1757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1758 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1682 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1759 .flags = CLOCK_IN_OMAP343X,
1760 .clkdm_name = "core_l4_clkdm", 1683 .clkdm_name = "core_l4_clkdm",
1761 .recalc = &followparent_recalc, 1684 .recalc = &followparent_recalc,
1762}; 1685};
1763 1686
1764static struct clk des2_ick = { 1687static struct clk des2_ick = {
1765 .name = "des2_ick", 1688 .name = "des2_ick",
1689 .ops = &clkops_omap2_dflt_wait,
1766 .parent = &core_l4_ick, 1690 .parent = &core_l4_ick,
1767 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1768 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1692 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1769 .flags = CLOCK_IN_OMAP343X,
1770 .clkdm_name = "core_l4_clkdm", 1693 .clkdm_name = "core_l4_clkdm",
1771 .recalc = &followparent_recalc, 1694 .recalc = &followparent_recalc,
1772}; 1695};
1773 1696
1774static struct clk mmchs2_ick = { 1697static struct clk mmchs2_ick = {
1775 .name = "mmchs_ick", 1698 .name = "mmchs_ick",
1699 .ops = &clkops_omap2_dflt_wait,
1776 .id = 1, 1700 .id = 1,
1777 .parent = &core_l4_ick, 1701 .parent = &core_l4_ick,
1778 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1779 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1703 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1780 .flags = CLOCK_IN_OMAP343X,
1781 .clkdm_name = "core_l4_clkdm", 1704 .clkdm_name = "core_l4_clkdm",
1782 .recalc = &followparent_recalc, 1705 .recalc = &followparent_recalc,
1783}; 1706};
1784 1707
1785static struct clk mmchs1_ick = { 1708static struct clk mmchs1_ick = {
1786 .name = "mmchs_ick", 1709 .name = "mmchs_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1787 .parent = &core_l4_ick, 1711 .parent = &core_l4_ick,
1788 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1789 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1713 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1790 .flags = CLOCK_IN_OMAP343X,
1791 .clkdm_name = "core_l4_clkdm", 1714 .clkdm_name = "core_l4_clkdm",
1792 .recalc = &followparent_recalc, 1715 .recalc = &followparent_recalc,
1793}; 1716};
1794 1717
1795static struct clk mspro_ick = { 1718static struct clk mspro_ick = {
1796 .name = "mspro_ick", 1719 .name = "mspro_ick",
1720 .ops = &clkops_omap2_dflt_wait,
1797 .parent = &core_l4_ick, 1721 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1723 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1800 .flags = CLOCK_IN_OMAP343X,
1801 .clkdm_name = "core_l4_clkdm", 1724 .clkdm_name = "core_l4_clkdm",
1802 .recalc = &followparent_recalc, 1725 .recalc = &followparent_recalc,
1803}; 1726};
1804 1727
1805static struct clk hdq_ick = { 1728static struct clk hdq_ick = {
1806 .name = "hdq_ick", 1729 .name = "hdq_ick",
1730 .ops = &clkops_omap2_dflt_wait,
1807 .parent = &core_l4_ick, 1731 .parent = &core_l4_ick,
1808 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1809 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1733 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1810 .flags = CLOCK_IN_OMAP343X,
1811 .clkdm_name = "core_l4_clkdm", 1734 .clkdm_name = "core_l4_clkdm",
1812 .recalc = &followparent_recalc, 1735 .recalc = &followparent_recalc,
1813}; 1736};
1814 1737
1815static struct clk mcspi4_ick = { 1738static struct clk mcspi4_ick = {
1816 .name = "mcspi_ick", 1739 .name = "mcspi_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1817 .id = 4, 1741 .id = 4,
1818 .parent = &core_l4_ick, 1742 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1744 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1821 .flags = CLOCK_IN_OMAP343X,
1822 .clkdm_name = "core_l4_clkdm", 1745 .clkdm_name = "core_l4_clkdm",
1823 .recalc = &followparent_recalc, 1746 .recalc = &followparent_recalc,
1824}; 1747};
1825 1748
1826static struct clk mcspi3_ick = { 1749static struct clk mcspi3_ick = {
1827 .name = "mcspi_ick", 1750 .name = "mcspi_ick",
1751 .ops = &clkops_omap2_dflt_wait,
1828 .id = 3, 1752 .id = 3,
1829 .parent = &core_l4_ick, 1753 .parent = &core_l4_ick,
1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1755 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1832 .flags = CLOCK_IN_OMAP343X,
1833 .clkdm_name = "core_l4_clkdm", 1756 .clkdm_name = "core_l4_clkdm",
1834 .recalc = &followparent_recalc, 1757 .recalc = &followparent_recalc,
1835}; 1758};
1836 1759
1837static struct clk mcspi2_ick = { 1760static struct clk mcspi2_ick = {
1838 .name = "mcspi_ick", 1761 .name = "mcspi_ick",
1762 .ops = &clkops_omap2_dflt_wait,
1839 .id = 2, 1763 .id = 2,
1840 .parent = &core_l4_ick, 1764 .parent = &core_l4_ick,
1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1842 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1766 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1843 .flags = CLOCK_IN_OMAP343X,
1844 .clkdm_name = "core_l4_clkdm", 1767 .clkdm_name = "core_l4_clkdm",
1845 .recalc = &followparent_recalc, 1768 .recalc = &followparent_recalc,
1846}; 1769};
1847 1770
1848static struct clk mcspi1_ick = { 1771static struct clk mcspi1_ick = {
1849 .name = "mcspi_ick", 1772 .name = "mcspi_ick",
1773 .ops = &clkops_omap2_dflt_wait,
1850 .id = 1, 1774 .id = 1,
1851 .parent = &core_l4_ick, 1775 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1777 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1854 .flags = CLOCK_IN_OMAP343X,
1855 .clkdm_name = "core_l4_clkdm", 1778 .clkdm_name = "core_l4_clkdm",
1856 .recalc = &followparent_recalc, 1779 .recalc = &followparent_recalc,
1857}; 1780};
1858 1781
1859static struct clk i2c3_ick = { 1782static struct clk i2c3_ick = {
1860 .name = "i2c_ick", 1783 .name = "i2c_ick",
1784 .ops = &clkops_omap2_dflt_wait,
1861 .id = 3, 1785 .id = 3,
1862 .parent = &core_l4_ick, 1786 .parent = &core_l4_ick,
1863 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1864 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1788 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1865 .flags = CLOCK_IN_OMAP343X,
1866 .clkdm_name = "core_l4_clkdm", 1789 .clkdm_name = "core_l4_clkdm",
1867 .recalc = &followparent_recalc, 1790 .recalc = &followparent_recalc,
1868}; 1791};
1869 1792
1870static struct clk i2c2_ick = { 1793static struct clk i2c2_ick = {
1871 .name = "i2c_ick", 1794 .name = "i2c_ick",
1795 .ops = &clkops_omap2_dflt_wait,
1872 .id = 2, 1796 .id = 2,
1873 .parent = &core_l4_ick, 1797 .parent = &core_l4_ick,
1874 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1875 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1799 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1876 .flags = CLOCK_IN_OMAP343X,
1877 .clkdm_name = "core_l4_clkdm", 1800 .clkdm_name = "core_l4_clkdm",
1878 .recalc = &followparent_recalc, 1801 .recalc = &followparent_recalc,
1879}; 1802};
1880 1803
1881static struct clk i2c1_ick = { 1804static struct clk i2c1_ick = {
1882 .name = "i2c_ick", 1805 .name = "i2c_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1883 .id = 1, 1807 .id = 1,
1884 .parent = &core_l4_ick, 1808 .parent = &core_l4_ick,
1885 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1886 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1810 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1887 .flags = CLOCK_IN_OMAP343X,
1888 .clkdm_name = "core_l4_clkdm", 1811 .clkdm_name = "core_l4_clkdm",
1889 .recalc = &followparent_recalc, 1812 .recalc = &followparent_recalc,
1890}; 1813};
1891 1814
1892static struct clk uart2_ick = { 1815static struct clk uart2_ick = {
1893 .name = "uart2_ick", 1816 .name = "uart2_ick",
1817 .ops = &clkops_omap2_dflt_wait,
1894 .parent = &core_l4_ick, 1818 .parent = &core_l4_ick,
1895 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1896 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1820 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1897 .flags = CLOCK_IN_OMAP343X,
1898 .clkdm_name = "core_l4_clkdm", 1821 .clkdm_name = "core_l4_clkdm",
1899 .recalc = &followparent_recalc, 1822 .recalc = &followparent_recalc,
1900}; 1823};
1901 1824
1902static struct clk uart1_ick = { 1825static struct clk uart1_ick = {
1903 .name = "uart1_ick", 1826 .name = "uart1_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1904 .parent = &core_l4_ick, 1828 .parent = &core_l4_ick,
1905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1906 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1830 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1907 .flags = CLOCK_IN_OMAP343X,
1908 .clkdm_name = "core_l4_clkdm", 1831 .clkdm_name = "core_l4_clkdm",
1909 .recalc = &followparent_recalc, 1832 .recalc = &followparent_recalc,
1910}; 1833};
1911 1834
1912static struct clk gpt11_ick = { 1835static struct clk gpt11_ick = {
1913 .name = "gpt11_ick", 1836 .name = "gpt11_ick",
1837 .ops = &clkops_omap2_dflt_wait,
1914 .parent = &core_l4_ick, 1838 .parent = &core_l4_ick,
1915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1916 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1840 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1917 .flags = CLOCK_IN_OMAP343X,
1918 .clkdm_name = "core_l4_clkdm", 1841 .clkdm_name = "core_l4_clkdm",
1919 .recalc = &followparent_recalc, 1842 .recalc = &followparent_recalc,
1920}; 1843};
1921 1844
1922static struct clk gpt10_ick = { 1845static struct clk gpt10_ick = {
1923 .name = "gpt10_ick", 1846 .name = "gpt10_ick",
1847 .ops = &clkops_omap2_dflt_wait,
1924 .parent = &core_l4_ick, 1848 .parent = &core_l4_ick,
1925 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1926 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1850 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1927 .flags = CLOCK_IN_OMAP343X,
1928 .clkdm_name = "core_l4_clkdm", 1851 .clkdm_name = "core_l4_clkdm",
1929 .recalc = &followparent_recalc, 1852 .recalc = &followparent_recalc,
1930}; 1853};
1931 1854
1932static struct clk mcbsp5_ick = { 1855static struct clk mcbsp5_ick = {
1933 .name = "mcbsp_ick", 1856 .name = "mcbsp_ick",
1857 .ops = &clkops_omap2_dflt_wait,
1934 .id = 5, 1858 .id = 5,
1935 .parent = &core_l4_ick, 1859 .parent = &core_l4_ick,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1861 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1938 .flags = CLOCK_IN_OMAP343X,
1939 .clkdm_name = "core_l4_clkdm", 1862 .clkdm_name = "core_l4_clkdm",
1940 .recalc = &followparent_recalc, 1863 .recalc = &followparent_recalc,
1941}; 1864};
1942 1865
1943static struct clk mcbsp1_ick = { 1866static struct clk mcbsp1_ick = {
1944 .name = "mcbsp_ick", 1867 .name = "mcbsp_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1945 .id = 1, 1869 .id = 1,
1946 .parent = &core_l4_ick, 1870 .parent = &core_l4_ick,
1947 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1948 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1872 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1949 .flags = CLOCK_IN_OMAP343X,
1950 .clkdm_name = "core_l4_clkdm", 1873 .clkdm_name = "core_l4_clkdm",
1951 .recalc = &followparent_recalc, 1874 .recalc = &followparent_recalc,
1952}; 1875};
1953 1876
1954static struct clk fac_ick = { 1877static struct clk fac_ick = {
1955 .name = "fac_ick", 1878 .name = "fac_ick",
1879 .ops = &clkops_omap2_dflt_wait,
1956 .parent = &core_l4_ick, 1880 .parent = &core_l4_ick,
1957 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1958 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 1882 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1959 .flags = CLOCK_IN_OMAP3430ES1,
1960 .clkdm_name = "core_l4_clkdm", 1883 .clkdm_name = "core_l4_clkdm",
1961 .recalc = &followparent_recalc, 1884 .recalc = &followparent_recalc,
1962}; 1885};
1963 1886
1964static struct clk mailboxes_ick = { 1887static struct clk mailboxes_ick = {
1965 .name = "mailboxes_ick", 1888 .name = "mailboxes_ick",
1889 .ops = &clkops_omap2_dflt_wait,
1966 .parent = &core_l4_ick, 1890 .parent = &core_l4_ick,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1968 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1892 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1969 .flags = CLOCK_IN_OMAP343X,
1970 .clkdm_name = "core_l4_clkdm", 1893 .clkdm_name = "core_l4_clkdm",
1971 .recalc = &followparent_recalc, 1894 .recalc = &followparent_recalc,
1972}; 1895};
1973 1896
1974static struct clk omapctrl_ick = { 1897static struct clk omapctrl_ick = {
1975 .name = "omapctrl_ick", 1898 .name = "omapctrl_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1976 .parent = &core_l4_ick, 1900 .parent = &core_l4_ick,
1977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1978 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 1902 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1979 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, 1903 .flags = ENABLE_ON_INIT,
1980 .recalc = &followparent_recalc, 1904 .recalc = &followparent_recalc,
1981}; 1905};
1982 1906
@@ -1984,19 +1908,18 @@ static struct clk omapctrl_ick = {
1984 1908
1985static struct clk ssi_l4_ick = { 1909static struct clk ssi_l4_ick = {
1986 .name = "ssi_l4_ick", 1910 .name = "ssi_l4_ick",
1911 .ops = &clkops_null,
1987 .parent = &l4_ick, 1912 .parent = &l4_ick,
1988 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1989 PARENT_CONTROLS_CLOCK,
1990 .clkdm_name = "core_l4_clkdm", 1913 .clkdm_name = "core_l4_clkdm",
1991 .recalc = &followparent_recalc, 1914 .recalc = &followparent_recalc,
1992}; 1915};
1993 1916
1994static struct clk ssi_ick = { 1917static struct clk ssi_ick = {
1995 .name = "ssi_ick", 1918 .name = "ssi_ick",
1919 .ops = &clkops_omap2_dflt,
1996 .parent = &ssi_l4_ick, 1920 .parent = &ssi_l4_ick,
1997 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1998 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1922 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1999 .flags = CLOCK_IN_OMAP343X,
2000 .clkdm_name = "core_l4_clkdm", 1923 .clkdm_name = "core_l4_clkdm",
2001 .recalc = &followparent_recalc, 1924 .recalc = &followparent_recalc,
2002}; 1925};
@@ -2011,6 +1934,7 @@ static const struct clksel usb_l4_clksel[] = {
2011 1934
2012static struct clk usb_l4_ick = { 1935static struct clk usb_l4_ick = {
2013 .name = "usb_l4_ick", 1936 .name = "usb_l4_ick",
1937 .ops = &clkops_omap2_dflt_wait,
2014 .parent = &l4_ick, 1938 .parent = &l4_ick,
2015 .init = &omap2_init_clksel_parent, 1939 .init = &omap2_init_clksel_parent,
2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2018,7 +1942,6 @@ static struct clk usb_l4_ick = {
2018 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), 1942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2019 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, 1943 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2020 .clksel = usb_l4_clksel, 1944 .clksel = usb_l4_clksel,
2021 .flags = CLOCK_IN_OMAP3430ES1,
2022 .recalc = &omap2_clksel_recalc, 1945 .recalc = &omap2_clksel_recalc,
2023}; 1946};
2024 1947
@@ -2028,98 +1951,87 @@ static struct clk usb_l4_ick = {
2028 1951
2029static struct clk security_l4_ick2 = { 1952static struct clk security_l4_ick2 = {
2030 .name = "security_l4_ick2", 1953 .name = "security_l4_ick2",
1954 .ops = &clkops_null,
2031 .parent = &l4_ick, 1955 .parent = &l4_ick,
2032 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2033 PARENT_CONTROLS_CLOCK,
2034 .recalc = &followparent_recalc, 1956 .recalc = &followparent_recalc,
2035}; 1957};
2036 1958
2037static struct clk aes1_ick = { 1959static struct clk aes1_ick = {
2038 .name = "aes1_ick", 1960 .name = "aes1_ick",
1961 .ops = &clkops_omap2_dflt_wait,
2039 .parent = &security_l4_ick2, 1962 .parent = &security_l4_ick2,
2040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2041 .enable_bit = OMAP3430_EN_AES1_SHIFT, 1964 .enable_bit = OMAP3430_EN_AES1_SHIFT,
2042 .flags = CLOCK_IN_OMAP343X,
2043 .recalc = &followparent_recalc, 1965 .recalc = &followparent_recalc,
2044}; 1966};
2045 1967
2046static struct clk rng_ick = { 1968static struct clk rng_ick = {
2047 .name = "rng_ick", 1969 .name = "rng_ick",
1970 .ops = &clkops_omap2_dflt_wait,
2048 .parent = &security_l4_ick2, 1971 .parent = &security_l4_ick2,
2049 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2050 .enable_bit = OMAP3430_EN_RNG_SHIFT, 1973 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2051 .flags = CLOCK_IN_OMAP343X,
2052 .recalc = &followparent_recalc, 1974 .recalc = &followparent_recalc,
2053}; 1975};
2054 1976
2055static struct clk sha11_ick = { 1977static struct clk sha11_ick = {
2056 .name = "sha11_ick", 1978 .name = "sha11_ick",
1979 .ops = &clkops_omap2_dflt_wait,
2057 .parent = &security_l4_ick2, 1980 .parent = &security_l4_ick2,
2058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2059 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 1982 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2060 .flags = CLOCK_IN_OMAP343X,
2061 .recalc = &followparent_recalc, 1983 .recalc = &followparent_recalc,
2062}; 1984};
2063 1985
2064static struct clk des1_ick = { 1986static struct clk des1_ick = {
2065 .name = "des1_ick", 1987 .name = "des1_ick",
1988 .ops = &clkops_omap2_dflt_wait,
2066 .parent = &security_l4_ick2, 1989 .parent = &security_l4_ick2,
2067 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2068 .enable_bit = OMAP3430_EN_DES1_SHIFT, 1991 .enable_bit = OMAP3430_EN_DES1_SHIFT,
2069 .flags = CLOCK_IN_OMAP343X,
2070 .recalc = &followparent_recalc, 1992 .recalc = &followparent_recalc,
2071}; 1993};
2072 1994
2073/* DSS */ 1995/* DSS */
2074static const struct clksel dss1_alwon_fck_clksel[] = {
2075 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2076 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
2077 { .parent = NULL }
2078};
2079
2080static struct clk dss1_alwon_fck = { 1996static struct clk dss1_alwon_fck = {
2081 .name = "dss1_alwon_fck", 1997 .name = "dss1_alwon_fck",
1998 .ops = &clkops_omap2_dflt,
2082 .parent = &dpll4_m4x2_ck, 1999 .parent = &dpll4_m4x2_ck,
2083 .init = &omap2_init_clksel_parent,
2084 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2085 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 2001 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2086 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2087 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2088 .clksel = dss1_alwon_fck_clksel,
2089 .flags = CLOCK_IN_OMAP343X,
2090 .clkdm_name = "dss_clkdm", 2002 .clkdm_name = "dss_clkdm",
2091 .recalc = &omap2_clksel_recalc, 2003 .recalc = &followparent_recalc,
2092}; 2004};
2093 2005
2094static struct clk dss_tv_fck = { 2006static struct clk dss_tv_fck = {
2095 .name = "dss_tv_fck", 2007 .name = "dss_tv_fck",
2008 .ops = &clkops_omap2_dflt,
2096 .parent = &omap_54m_fck, 2009 .parent = &omap_54m_fck,
2097 .init = &omap2_init_clk_clkdm, 2010 .init = &omap2_init_clk_clkdm,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2011 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2099 .enable_bit = OMAP3430_EN_TV_SHIFT, 2012 .enable_bit = OMAP3430_EN_TV_SHIFT,
2100 .flags = CLOCK_IN_OMAP343X,
2101 .clkdm_name = "dss_clkdm", 2013 .clkdm_name = "dss_clkdm",
2102 .recalc = &followparent_recalc, 2014 .recalc = &followparent_recalc,
2103}; 2015};
2104 2016
2105static struct clk dss_96m_fck = { 2017static struct clk dss_96m_fck = {
2106 .name = "dss_96m_fck", 2018 .name = "dss_96m_fck",
2019 .ops = &clkops_omap2_dflt,
2107 .parent = &omap_96m_fck, 2020 .parent = &omap_96m_fck,
2108 .init = &omap2_init_clk_clkdm, 2021 .init = &omap2_init_clk_clkdm,
2109 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2022 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2110 .enable_bit = OMAP3430_EN_TV_SHIFT, 2023 .enable_bit = OMAP3430_EN_TV_SHIFT,
2111 .flags = CLOCK_IN_OMAP343X,
2112 .clkdm_name = "dss_clkdm", 2024 .clkdm_name = "dss_clkdm",
2113 .recalc = &followparent_recalc, 2025 .recalc = &followparent_recalc,
2114}; 2026};
2115 2027
2116static struct clk dss2_alwon_fck = { 2028static struct clk dss2_alwon_fck = {
2117 .name = "dss2_alwon_fck", 2029 .name = "dss2_alwon_fck",
2030 .ops = &clkops_omap2_dflt,
2118 .parent = &sys_ck, 2031 .parent = &sys_ck,
2119 .init = &omap2_init_clk_clkdm, 2032 .init = &omap2_init_clk_clkdm,
2120 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2033 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2121 .enable_bit = OMAP3430_EN_DSS2_SHIFT, 2034 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2122 .flags = CLOCK_IN_OMAP343X,
2123 .clkdm_name = "dss_clkdm", 2035 .clkdm_name = "dss_clkdm",
2124 .recalc = &followparent_recalc, 2036 .recalc = &followparent_recalc,
2125}; 2037};
@@ -2127,45 +2039,46 @@ static struct clk dss2_alwon_fck = {
2127static struct clk dss_ick = { 2039static struct clk dss_ick = {
2128 /* Handles both L3 and L4 clocks */ 2040 /* Handles both L3 and L4 clocks */
2129 .name = "dss_ick", 2041 .name = "dss_ick",
2042 .ops = &clkops_omap2_dflt,
2130 .parent = &l4_ick, 2043 .parent = &l4_ick,
2131 .init = &omap2_init_clk_clkdm, 2044 .init = &omap2_init_clk_clkdm,
2132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2133 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2046 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2134 .flags = CLOCK_IN_OMAP343X,
2135 .clkdm_name = "dss_clkdm", 2047 .clkdm_name = "dss_clkdm",
2136 .recalc = &followparent_recalc, 2048 .recalc = &followparent_recalc,
2137}; 2049};
2138 2050
2139/* CAM */ 2051/* CAM */
2140 2052
2141static const struct clksel cam_mclk_clksel[] = {
2142 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2143 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2144 { .parent = NULL }
2145};
2146
2147static struct clk cam_mclk = { 2053static struct clk cam_mclk = {
2148 .name = "cam_mclk", 2054 .name = "cam_mclk",
2055 .ops = &clkops_omap2_dflt_wait,
2149 .parent = &dpll4_m5x2_ck, 2056 .parent = &dpll4_m5x2_ck,
2150 .init = &omap2_init_clksel_parent,
2151 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2152 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2153 .clksel = cam_mclk_clksel,
2154 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2155 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2058 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2156 .flags = CLOCK_IN_OMAP343X,
2157 .clkdm_name = "cam_clkdm", 2059 .clkdm_name = "cam_clkdm",
2158 .recalc = &omap2_clksel_recalc, 2060 .recalc = &followparent_recalc,
2159}; 2061};
2160 2062
2161static struct clk cam_ick = { 2063static struct clk cam_ick = {
2162 /* Handles both L3 and L4 clocks */ 2064 /* Handles both L3 and L4 clocks */
2163 .name = "cam_ick", 2065 .name = "cam_ick",
2066 .ops = &clkops_omap2_dflt_wait,
2164 .parent = &l4_ick, 2067 .parent = &l4_ick,
2165 .init = &omap2_init_clk_clkdm, 2068 .init = &omap2_init_clk_clkdm,
2166 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2167 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2070 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2168 .flags = CLOCK_IN_OMAP343X, 2071 .clkdm_name = "cam_clkdm",
2072 .recalc = &followparent_recalc,
2073};
2074
2075static struct clk csi2_96m_fck = {
2076 .name = "csi2_96m_fck",
2077 .ops = &clkops_omap2_dflt_wait,
2078 .parent = &core_96m_fck,
2079 .init = &omap2_init_clk_clkdm,
2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2081 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2169 .clkdm_name = "cam_clkdm", 2082 .clkdm_name = "cam_clkdm",
2170 .recalc = &followparent_recalc, 2083 .recalc = &followparent_recalc,
2171}; 2084};
@@ -2174,22 +2087,22 @@ static struct clk cam_ick = {
2174 2087
2175static struct clk usbhost_120m_fck = { 2088static struct clk usbhost_120m_fck = {
2176 .name = "usbhost_120m_fck", 2089 .name = "usbhost_120m_fck",
2177 .parent = &omap_120m_fck, 2090 .ops = &clkops_omap2_dflt_wait,
2091 .parent = &dpll5_m2_ck,
2178 .init = &omap2_init_clk_clkdm, 2092 .init = &omap2_init_clk_clkdm,
2179 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2093 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2180 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, 2094 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2181 .flags = CLOCK_IN_OMAP3430ES2,
2182 .clkdm_name = "usbhost_clkdm", 2095 .clkdm_name = "usbhost_clkdm",
2183 .recalc = &followparent_recalc, 2096 .recalc = &followparent_recalc,
2184}; 2097};
2185 2098
2186static struct clk usbhost_48m_fck = { 2099static struct clk usbhost_48m_fck = {
2187 .name = "usbhost_48m_fck", 2100 .name = "usbhost_48m_fck",
2101 .ops = &clkops_omap2_dflt_wait,
2188 .parent = &omap_48m_fck, 2102 .parent = &omap_48m_fck,
2189 .init = &omap2_init_clk_clkdm, 2103 .init = &omap2_init_clk_clkdm,
2190 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), 2104 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2191 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 2105 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2192 .flags = CLOCK_IN_OMAP3430ES2,
2193 .clkdm_name = "usbhost_clkdm", 2106 .clkdm_name = "usbhost_clkdm",
2194 .recalc = &followparent_recalc, 2107 .recalc = &followparent_recalc,
2195}; 2108};
@@ -2197,22 +2110,11 @@ static struct clk usbhost_48m_fck = {
2197static struct clk usbhost_ick = { 2110static struct clk usbhost_ick = {
2198 /* Handles both L3 and L4 clocks */ 2111 /* Handles both L3 and L4 clocks */
2199 .name = "usbhost_ick", 2112 .name = "usbhost_ick",
2113 .ops = &clkops_omap2_dflt_wait,
2200 .parent = &l4_ick, 2114 .parent = &l4_ick,
2201 .init = &omap2_init_clk_clkdm, 2115 .init = &omap2_init_clk_clkdm,
2202 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2203 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2204 .flags = CLOCK_IN_OMAP3430ES2,
2205 .clkdm_name = "usbhost_clkdm",
2206 .recalc = &followparent_recalc,
2207};
2208
2209static struct clk usbhost_sar_fck = {
2210 .name = "usbhost_sar_fck",
2211 .parent = &osc_sys_ck,
2212 .init = &omap2_init_clk_clkdm,
2213 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2214 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2215 .flags = CLOCK_IN_OMAP3430ES2,
2216 .clkdm_name = "usbhost_clkdm", 2118 .clkdm_name = "usbhost_clkdm",
2217 .recalc = &followparent_recalc, 2119 .recalc = &followparent_recalc,
2218}; 2120};
@@ -2237,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = {
2237 2139
2238static const struct clksel usim_clksel[] = { 2140static const struct clksel usim_clksel[] = {
2239 { .parent = &omap_96m_fck, .rates = usim_96m_rates }, 2141 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2240 { .parent = &omap_120m_fck, .rates = usim_120m_rates }, 2142 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2241 { .parent = &sys_ck, .rates = div2_rates }, 2143 { .parent = &sys_ck, .rates = div2_rates },
2242 { .parent = NULL }, 2144 { .parent = NULL },
2243}; 2145};
@@ -2245,63 +2147,63 @@ static const struct clksel usim_clksel[] = {
2245/* 3430ES2 only */ 2147/* 3430ES2 only */
2246static struct clk usim_fck = { 2148static struct clk usim_fck = {
2247 .name = "usim_fck", 2149 .name = "usim_fck",
2150 .ops = &clkops_omap2_dflt_wait,
2248 .init = &omap2_init_clksel_parent, 2151 .init = &omap2_init_clksel_parent,
2249 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2250 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2251 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2154 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2252 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, 2155 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2253 .clksel = usim_clksel, 2156 .clksel = usim_clksel,
2254 .flags = CLOCK_IN_OMAP3430ES2,
2255 .recalc = &omap2_clksel_recalc, 2157 .recalc = &omap2_clksel_recalc,
2256}; 2158};
2257 2159
2258/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ 2160/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2259static struct clk gpt1_fck = { 2161static struct clk gpt1_fck = {
2260 .name = "gpt1_fck", 2162 .name = "gpt1_fck",
2163 .ops = &clkops_omap2_dflt_wait,
2261 .init = &omap2_init_clksel_parent, 2164 .init = &omap2_init_clksel_parent,
2262 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2165 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2263 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2166 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2264 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), 2167 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2265 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, 2168 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2266 .clksel = omap343x_gpt_clksel, 2169 .clksel = omap343x_gpt_clksel,
2267 .flags = CLOCK_IN_OMAP343X,
2268 .clkdm_name = "wkup_clkdm", 2170 .clkdm_name = "wkup_clkdm",
2269 .recalc = &omap2_clksel_recalc, 2171 .recalc = &omap2_clksel_recalc,
2270}; 2172};
2271 2173
2272static struct clk wkup_32k_fck = { 2174static struct clk wkup_32k_fck = {
2273 .name = "wkup_32k_fck", 2175 .name = "wkup_32k_fck",
2176 .ops = &clkops_null,
2274 .init = &omap2_init_clk_clkdm, 2177 .init = &omap2_init_clk_clkdm,
2275 .parent = &omap_32k_fck, 2178 .parent = &omap_32k_fck,
2276 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2277 .clkdm_name = "wkup_clkdm", 2179 .clkdm_name = "wkup_clkdm",
2278 .recalc = &followparent_recalc, 2180 .recalc = &followparent_recalc,
2279}; 2181};
2280 2182
2281static struct clk gpio1_dbck = { 2183static struct clk gpio1_dbck = {
2282 .name = "gpio1_dbck", 2184 .name = "gpio1_dbck",
2185 .ops = &clkops_omap2_dflt_wait,
2283 .parent = &wkup_32k_fck, 2186 .parent = &wkup_32k_fck,
2284 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2285 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2188 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2286 .flags = CLOCK_IN_OMAP343X,
2287 .clkdm_name = "wkup_clkdm", 2189 .clkdm_name = "wkup_clkdm",
2288 .recalc = &followparent_recalc, 2190 .recalc = &followparent_recalc,
2289}; 2191};
2290 2192
2291static struct clk wdt2_fck = { 2193static struct clk wdt2_fck = {
2292 .name = "wdt2_fck", 2194 .name = "wdt2_fck",
2195 .ops = &clkops_omap2_dflt_wait,
2293 .parent = &wkup_32k_fck, 2196 .parent = &wkup_32k_fck,
2294 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2295 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2198 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2296 .flags = CLOCK_IN_OMAP343X,
2297 .clkdm_name = "wkup_clkdm", 2199 .clkdm_name = "wkup_clkdm",
2298 .recalc = &followparent_recalc, 2200 .recalc = &followparent_recalc,
2299}; 2201};
2300 2202
2301static struct clk wkup_l4_ick = { 2203static struct clk wkup_l4_ick = {
2302 .name = "wkup_l4_ick", 2204 .name = "wkup_l4_ick",
2205 .ops = &clkops_null,
2303 .parent = &sys_ck, 2206 .parent = &sys_ck,
2304 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2305 .clkdm_name = "wkup_clkdm", 2207 .clkdm_name = "wkup_clkdm",
2306 .recalc = &followparent_recalc, 2208 .recalc = &followparent_recalc,
2307}; 2209};
@@ -2310,50 +2212,50 @@ static struct clk wkup_l4_ick = {
2310/* Never specifically named in the TRM, so we have to infer a likely name */ 2212/* Never specifically named in the TRM, so we have to infer a likely name */
2311static struct clk usim_ick = { 2213static struct clk usim_ick = {
2312 .name = "usim_ick", 2214 .name = "usim_ick",
2215 .ops = &clkops_omap2_dflt_wait,
2313 .parent = &wkup_l4_ick, 2216 .parent = &wkup_l4_ick,
2314 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2217 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2315 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2218 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2316 .flags = CLOCK_IN_OMAP3430ES2,
2317 .clkdm_name = "wkup_clkdm", 2219 .clkdm_name = "wkup_clkdm",
2318 .recalc = &followparent_recalc, 2220 .recalc = &followparent_recalc,
2319}; 2221};
2320 2222
2321static struct clk wdt2_ick = { 2223static struct clk wdt2_ick = {
2322 .name = "wdt2_ick", 2224 .name = "wdt2_ick",
2225 .ops = &clkops_omap2_dflt_wait,
2323 .parent = &wkup_l4_ick, 2226 .parent = &wkup_l4_ick,
2324 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2325 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2228 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2326 .flags = CLOCK_IN_OMAP343X,
2327 .clkdm_name = "wkup_clkdm", 2229 .clkdm_name = "wkup_clkdm",
2328 .recalc = &followparent_recalc, 2230 .recalc = &followparent_recalc,
2329}; 2231};
2330 2232
2331static struct clk wdt1_ick = { 2233static struct clk wdt1_ick = {
2332 .name = "wdt1_ick", 2234 .name = "wdt1_ick",
2235 .ops = &clkops_omap2_dflt_wait,
2333 .parent = &wkup_l4_ick, 2236 .parent = &wkup_l4_ick,
2334 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2237 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2335 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2238 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2336 .flags = CLOCK_IN_OMAP343X,
2337 .clkdm_name = "wkup_clkdm", 2239 .clkdm_name = "wkup_clkdm",
2338 .recalc = &followparent_recalc, 2240 .recalc = &followparent_recalc,
2339}; 2241};
2340 2242
2341static struct clk gpio1_ick = { 2243static struct clk gpio1_ick = {
2342 .name = "gpio1_ick", 2244 .name = "gpio1_ick",
2245 .ops = &clkops_omap2_dflt_wait,
2343 .parent = &wkup_l4_ick, 2246 .parent = &wkup_l4_ick,
2344 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2345 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2248 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2346 .flags = CLOCK_IN_OMAP343X,
2347 .clkdm_name = "wkup_clkdm", 2249 .clkdm_name = "wkup_clkdm",
2348 .recalc = &followparent_recalc, 2250 .recalc = &followparent_recalc,
2349}; 2251};
2350 2252
2351static struct clk omap_32ksync_ick = { 2253static struct clk omap_32ksync_ick = {
2352 .name = "omap_32ksync_ick", 2254 .name = "omap_32ksync_ick",
2255 .ops = &clkops_omap2_dflt_wait,
2353 .parent = &wkup_l4_ick, 2256 .parent = &wkup_l4_ick,
2354 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2355 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2258 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2356 .flags = CLOCK_IN_OMAP343X,
2357 .clkdm_name = "wkup_clkdm", 2259 .clkdm_name = "wkup_clkdm",
2358 .recalc = &followparent_recalc, 2260 .recalc = &followparent_recalc,
2359}; 2261};
@@ -2361,20 +2263,20 @@ static struct clk omap_32ksync_ick = {
2361/* XXX This clock no longer exists in 3430 TRM rev F */ 2263/* XXX This clock no longer exists in 3430 TRM rev F */
2362static struct clk gpt12_ick = { 2264static struct clk gpt12_ick = {
2363 .name = "gpt12_ick", 2265 .name = "gpt12_ick",
2266 .ops = &clkops_omap2_dflt_wait,
2364 .parent = &wkup_l4_ick, 2267 .parent = &wkup_l4_ick,
2365 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2268 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2366 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2269 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2367 .flags = CLOCK_IN_OMAP343X,
2368 .clkdm_name = "wkup_clkdm", 2270 .clkdm_name = "wkup_clkdm",
2369 .recalc = &followparent_recalc, 2271 .recalc = &followparent_recalc,
2370}; 2272};
2371 2273
2372static struct clk gpt1_ick = { 2274static struct clk gpt1_ick = {
2373 .name = "gpt1_ick", 2275 .name = "gpt1_ick",
2276 .ops = &clkops_omap2_dflt_wait,
2374 .parent = &wkup_l4_ick, 2277 .parent = &wkup_l4_ick,
2375 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2278 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2376 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2279 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2377 .flags = CLOCK_IN_OMAP343X,
2378 .clkdm_name = "wkup_clkdm", 2280 .clkdm_name = "wkup_clkdm",
2379 .recalc = &followparent_recalc, 2281 .recalc = &followparent_recalc,
2380}; 2282};
@@ -2385,406 +2287,404 @@ static struct clk gpt1_ick = {
2385 2287
2386static struct clk per_96m_fck = { 2288static struct clk per_96m_fck = {
2387 .name = "per_96m_fck", 2289 .name = "per_96m_fck",
2290 .ops = &clkops_null,
2388 .parent = &omap_96m_alwon_fck, 2291 .parent = &omap_96m_alwon_fck,
2389 .init = &omap2_init_clk_clkdm, 2292 .init = &omap2_init_clk_clkdm,
2390 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2391 PARENT_CONTROLS_CLOCK,
2392 .clkdm_name = "per_clkdm", 2293 .clkdm_name = "per_clkdm",
2393 .recalc = &followparent_recalc, 2294 .recalc = &followparent_recalc,
2394}; 2295};
2395 2296
2396static struct clk per_48m_fck = { 2297static struct clk per_48m_fck = {
2397 .name = "per_48m_fck", 2298 .name = "per_48m_fck",
2299 .ops = &clkops_null,
2398 .parent = &omap_48m_fck, 2300 .parent = &omap_48m_fck,
2399 .init = &omap2_init_clk_clkdm, 2301 .init = &omap2_init_clk_clkdm,
2400 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2401 PARENT_CONTROLS_CLOCK,
2402 .clkdm_name = "per_clkdm", 2302 .clkdm_name = "per_clkdm",
2403 .recalc = &followparent_recalc, 2303 .recalc = &followparent_recalc,
2404}; 2304};
2405 2305
2406static struct clk uart3_fck = { 2306static struct clk uart3_fck = {
2407 .name = "uart3_fck", 2307 .name = "uart3_fck",
2308 .ops = &clkops_omap2_dflt_wait,
2408 .parent = &per_48m_fck, 2309 .parent = &per_48m_fck,
2409 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2410 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2311 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2411 .flags = CLOCK_IN_OMAP343X,
2412 .clkdm_name = "per_clkdm", 2312 .clkdm_name = "per_clkdm",
2413 .recalc = &followparent_recalc, 2313 .recalc = &followparent_recalc,
2414}; 2314};
2415 2315
2416static struct clk gpt2_fck = { 2316static struct clk gpt2_fck = {
2417 .name = "gpt2_fck", 2317 .name = "gpt2_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2418 .init = &omap2_init_clksel_parent, 2319 .init = &omap2_init_clksel_parent,
2419 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2320 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2420 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2321 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2421 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2322 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2422 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, 2323 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2423 .clksel = omap343x_gpt_clksel, 2324 .clksel = omap343x_gpt_clksel,
2424 .flags = CLOCK_IN_OMAP343X,
2425 .clkdm_name = "per_clkdm", 2325 .clkdm_name = "per_clkdm",
2426 .recalc = &omap2_clksel_recalc, 2326 .recalc = &omap2_clksel_recalc,
2427}; 2327};
2428 2328
2429static struct clk gpt3_fck = { 2329static struct clk gpt3_fck = {
2430 .name = "gpt3_fck", 2330 .name = "gpt3_fck",
2331 .ops = &clkops_omap2_dflt_wait,
2431 .init = &omap2_init_clksel_parent, 2332 .init = &omap2_init_clksel_parent,
2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2333 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2433 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2334 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2434 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2335 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2435 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, 2336 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2436 .clksel = omap343x_gpt_clksel, 2337 .clksel = omap343x_gpt_clksel,
2437 .flags = CLOCK_IN_OMAP343X,
2438 .clkdm_name = "per_clkdm", 2338 .clkdm_name = "per_clkdm",
2439 .recalc = &omap2_clksel_recalc, 2339 .recalc = &omap2_clksel_recalc,
2440}; 2340};
2441 2341
2442static struct clk gpt4_fck = { 2342static struct clk gpt4_fck = {
2443 .name = "gpt4_fck", 2343 .name = "gpt4_fck",
2344 .ops = &clkops_omap2_dflt_wait,
2444 .init = &omap2_init_clksel_parent, 2345 .init = &omap2_init_clksel_parent,
2445 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2446 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2347 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2447 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2348 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2448 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, 2349 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2449 .clksel = omap343x_gpt_clksel, 2350 .clksel = omap343x_gpt_clksel,
2450 .flags = CLOCK_IN_OMAP343X,
2451 .clkdm_name = "per_clkdm", 2351 .clkdm_name = "per_clkdm",
2452 .recalc = &omap2_clksel_recalc, 2352 .recalc = &omap2_clksel_recalc,
2453}; 2353};
2454 2354
2455static struct clk gpt5_fck = { 2355static struct clk gpt5_fck = {
2456 .name = "gpt5_fck", 2356 .name = "gpt5_fck",
2357 .ops = &clkops_omap2_dflt_wait,
2457 .init = &omap2_init_clksel_parent, 2358 .init = &omap2_init_clksel_parent,
2458 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2359 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2459 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2360 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2460 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2361 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2461 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, 2362 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2462 .clksel = omap343x_gpt_clksel, 2363 .clksel = omap343x_gpt_clksel,
2463 .flags = CLOCK_IN_OMAP343X,
2464 .clkdm_name = "per_clkdm", 2364 .clkdm_name = "per_clkdm",
2465 .recalc = &omap2_clksel_recalc, 2365 .recalc = &omap2_clksel_recalc,
2466}; 2366};
2467 2367
2468static struct clk gpt6_fck = { 2368static struct clk gpt6_fck = {
2469 .name = "gpt6_fck", 2369 .name = "gpt6_fck",
2370 .ops = &clkops_omap2_dflt_wait,
2470 .init = &omap2_init_clksel_parent, 2371 .init = &omap2_init_clksel_parent,
2471 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2372 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2472 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2373 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2473 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2474 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, 2375 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2475 .clksel = omap343x_gpt_clksel, 2376 .clksel = omap343x_gpt_clksel,
2476 .flags = CLOCK_IN_OMAP343X,
2477 .clkdm_name = "per_clkdm", 2377 .clkdm_name = "per_clkdm",
2478 .recalc = &omap2_clksel_recalc, 2378 .recalc = &omap2_clksel_recalc,
2479}; 2379};
2480 2380
2481static struct clk gpt7_fck = { 2381static struct clk gpt7_fck = {
2482 .name = "gpt7_fck", 2382 .name = "gpt7_fck",
2383 .ops = &clkops_omap2_dflt_wait,
2483 .init = &omap2_init_clksel_parent, 2384 .init = &omap2_init_clksel_parent,
2484 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2385 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2485 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2386 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2486 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2387 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2487 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, 2388 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2488 .clksel = omap343x_gpt_clksel, 2389 .clksel = omap343x_gpt_clksel,
2489 .flags = CLOCK_IN_OMAP343X,
2490 .clkdm_name = "per_clkdm", 2390 .clkdm_name = "per_clkdm",
2491 .recalc = &omap2_clksel_recalc, 2391 .recalc = &omap2_clksel_recalc,
2492}; 2392};
2493 2393
2494static struct clk gpt8_fck = { 2394static struct clk gpt8_fck = {
2495 .name = "gpt8_fck", 2395 .name = "gpt8_fck",
2396 .ops = &clkops_omap2_dflt_wait,
2496 .init = &omap2_init_clksel_parent, 2397 .init = &omap2_init_clksel_parent,
2497 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2498 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2399 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2499 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2500 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, 2401 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2501 .clksel = omap343x_gpt_clksel, 2402 .clksel = omap343x_gpt_clksel,
2502 .flags = CLOCK_IN_OMAP343X,
2503 .clkdm_name = "per_clkdm", 2403 .clkdm_name = "per_clkdm",
2504 .recalc = &omap2_clksel_recalc, 2404 .recalc = &omap2_clksel_recalc,
2505}; 2405};
2506 2406
2507static struct clk gpt9_fck = { 2407static struct clk gpt9_fck = {
2508 .name = "gpt9_fck", 2408 .name = "gpt9_fck",
2409 .ops = &clkops_omap2_dflt_wait,
2509 .init = &omap2_init_clksel_parent, 2410 .init = &omap2_init_clksel_parent,
2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2511 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2412 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2512 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), 2413 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2513 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, 2414 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2514 .clksel = omap343x_gpt_clksel, 2415 .clksel = omap343x_gpt_clksel,
2515 .flags = CLOCK_IN_OMAP343X,
2516 .clkdm_name = "per_clkdm", 2416 .clkdm_name = "per_clkdm",
2517 .recalc = &omap2_clksel_recalc, 2417 .recalc = &omap2_clksel_recalc,
2518}; 2418};
2519 2419
2520static struct clk per_32k_alwon_fck = { 2420static struct clk per_32k_alwon_fck = {
2521 .name = "per_32k_alwon_fck", 2421 .name = "per_32k_alwon_fck",
2422 .ops = &clkops_null,
2522 .parent = &omap_32k_fck, 2423 .parent = &omap_32k_fck,
2523 .clkdm_name = "per_clkdm", 2424 .clkdm_name = "per_clkdm",
2524 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2525 .recalc = &followparent_recalc, 2425 .recalc = &followparent_recalc,
2526}; 2426};
2527 2427
2528static struct clk gpio6_dbck = { 2428static struct clk gpio6_dbck = {
2529 .name = "gpio6_dbck", 2429 .name = "gpio6_dbck",
2430 .ops = &clkops_omap2_dflt_wait,
2530 .parent = &per_32k_alwon_fck, 2431 .parent = &per_32k_alwon_fck,
2531 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2532 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2433 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2533 .flags = CLOCK_IN_OMAP343X,
2534 .clkdm_name = "per_clkdm", 2434 .clkdm_name = "per_clkdm",
2535 .recalc = &followparent_recalc, 2435 .recalc = &followparent_recalc,
2536}; 2436};
2537 2437
2538static struct clk gpio5_dbck = { 2438static struct clk gpio5_dbck = {
2539 .name = "gpio5_dbck", 2439 .name = "gpio5_dbck",
2440 .ops = &clkops_omap2_dflt_wait,
2540 .parent = &per_32k_alwon_fck, 2441 .parent = &per_32k_alwon_fck,
2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2542 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2443 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2543 .flags = CLOCK_IN_OMAP343X,
2544 .clkdm_name = "per_clkdm", 2444 .clkdm_name = "per_clkdm",
2545 .recalc = &followparent_recalc, 2445 .recalc = &followparent_recalc,
2546}; 2446};
2547 2447
2548static struct clk gpio4_dbck = { 2448static struct clk gpio4_dbck = {
2549 .name = "gpio4_dbck", 2449 .name = "gpio4_dbck",
2450 .ops = &clkops_omap2_dflt_wait,
2550 .parent = &per_32k_alwon_fck, 2451 .parent = &per_32k_alwon_fck,
2551 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2552 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2453 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2553 .flags = CLOCK_IN_OMAP343X,
2554 .clkdm_name = "per_clkdm", 2454 .clkdm_name = "per_clkdm",
2555 .recalc = &followparent_recalc, 2455 .recalc = &followparent_recalc,
2556}; 2456};
2557 2457
2558static struct clk gpio3_dbck = { 2458static struct clk gpio3_dbck = {
2559 .name = "gpio3_dbck", 2459 .name = "gpio3_dbck",
2460 .ops = &clkops_omap2_dflt_wait,
2560 .parent = &per_32k_alwon_fck, 2461 .parent = &per_32k_alwon_fck,
2561 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2562 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2563 .flags = CLOCK_IN_OMAP343X,
2564 .clkdm_name = "per_clkdm", 2464 .clkdm_name = "per_clkdm",
2565 .recalc = &followparent_recalc, 2465 .recalc = &followparent_recalc,
2566}; 2466};
2567 2467
2568static struct clk gpio2_dbck = { 2468static struct clk gpio2_dbck = {
2569 .name = "gpio2_dbck", 2469 .name = "gpio2_dbck",
2470 .ops = &clkops_omap2_dflt_wait,
2570 .parent = &per_32k_alwon_fck, 2471 .parent = &per_32k_alwon_fck,
2571 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2572 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2473 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2573 .flags = CLOCK_IN_OMAP343X,
2574 .clkdm_name = "per_clkdm", 2474 .clkdm_name = "per_clkdm",
2575 .recalc = &followparent_recalc, 2475 .recalc = &followparent_recalc,
2576}; 2476};
2577 2477
2578static struct clk wdt3_fck = { 2478static struct clk wdt3_fck = {
2579 .name = "wdt3_fck", 2479 .name = "wdt3_fck",
2480 .ops = &clkops_omap2_dflt_wait,
2580 .parent = &per_32k_alwon_fck, 2481 .parent = &per_32k_alwon_fck,
2581 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2482 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2582 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2483 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2583 .flags = CLOCK_IN_OMAP343X,
2584 .clkdm_name = "per_clkdm", 2484 .clkdm_name = "per_clkdm",
2585 .recalc = &followparent_recalc, 2485 .recalc = &followparent_recalc,
2586}; 2486};
2587 2487
2588static struct clk per_l4_ick = { 2488static struct clk per_l4_ick = {
2589 .name = "per_l4_ick", 2489 .name = "per_l4_ick",
2490 .ops = &clkops_null,
2590 .parent = &l4_ick, 2491 .parent = &l4_ick,
2591 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2592 PARENT_CONTROLS_CLOCK,
2593 .clkdm_name = "per_clkdm", 2492 .clkdm_name = "per_clkdm",
2594 .recalc = &followparent_recalc, 2493 .recalc = &followparent_recalc,
2595}; 2494};
2596 2495
2597static struct clk gpio6_ick = { 2496static struct clk gpio6_ick = {
2598 .name = "gpio6_ick", 2497 .name = "gpio6_ick",
2498 .ops = &clkops_omap2_dflt_wait,
2599 .parent = &per_l4_ick, 2499 .parent = &per_l4_ick,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2601 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2501 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2602 .flags = CLOCK_IN_OMAP343X,
2603 .clkdm_name = "per_clkdm", 2502 .clkdm_name = "per_clkdm",
2604 .recalc = &followparent_recalc, 2503 .recalc = &followparent_recalc,
2605}; 2504};
2606 2505
2607static struct clk gpio5_ick = { 2506static struct clk gpio5_ick = {
2608 .name = "gpio5_ick", 2507 .name = "gpio5_ick",
2508 .ops = &clkops_omap2_dflt_wait,
2609 .parent = &per_l4_ick, 2509 .parent = &per_l4_ick,
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2511 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2612 .flags = CLOCK_IN_OMAP343X,
2613 .clkdm_name = "per_clkdm", 2512 .clkdm_name = "per_clkdm",
2614 .recalc = &followparent_recalc, 2513 .recalc = &followparent_recalc,
2615}; 2514};
2616 2515
2617static struct clk gpio4_ick = { 2516static struct clk gpio4_ick = {
2618 .name = "gpio4_ick", 2517 .name = "gpio4_ick",
2518 .ops = &clkops_omap2_dflt_wait,
2619 .parent = &per_l4_ick, 2519 .parent = &per_l4_ick,
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2521 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2622 .flags = CLOCK_IN_OMAP343X,
2623 .clkdm_name = "per_clkdm", 2522 .clkdm_name = "per_clkdm",
2624 .recalc = &followparent_recalc, 2523 .recalc = &followparent_recalc,
2625}; 2524};
2626 2525
2627static struct clk gpio3_ick = { 2526static struct clk gpio3_ick = {
2628 .name = "gpio3_ick", 2527 .name = "gpio3_ick",
2528 .ops = &clkops_omap2_dflt_wait,
2629 .parent = &per_l4_ick, 2529 .parent = &per_l4_ick,
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2531 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2632 .flags = CLOCK_IN_OMAP343X,
2633 .clkdm_name = "per_clkdm", 2532 .clkdm_name = "per_clkdm",
2634 .recalc = &followparent_recalc, 2533 .recalc = &followparent_recalc,
2635}; 2534};
2636 2535
2637static struct clk gpio2_ick = { 2536static struct clk gpio2_ick = {
2638 .name = "gpio2_ick", 2537 .name = "gpio2_ick",
2538 .ops = &clkops_omap2_dflt_wait,
2639 .parent = &per_l4_ick, 2539 .parent = &per_l4_ick,
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2541 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2642 .flags = CLOCK_IN_OMAP343X,
2643 .clkdm_name = "per_clkdm", 2542 .clkdm_name = "per_clkdm",
2644 .recalc = &followparent_recalc, 2543 .recalc = &followparent_recalc,
2645}; 2544};
2646 2545
2647static struct clk wdt3_ick = { 2546static struct clk wdt3_ick = {
2648 .name = "wdt3_ick", 2547 .name = "wdt3_ick",
2548 .ops = &clkops_omap2_dflt_wait,
2649 .parent = &per_l4_ick, 2549 .parent = &per_l4_ick,
2650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2651 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2551 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2652 .flags = CLOCK_IN_OMAP343X,
2653 .clkdm_name = "per_clkdm", 2552 .clkdm_name = "per_clkdm",
2654 .recalc = &followparent_recalc, 2553 .recalc = &followparent_recalc,
2655}; 2554};
2656 2555
2657static struct clk uart3_ick = { 2556static struct clk uart3_ick = {
2658 .name = "uart3_ick", 2557 .name = "uart3_ick",
2558 .ops = &clkops_omap2_dflt_wait,
2659 .parent = &per_l4_ick, 2559 .parent = &per_l4_ick,
2660 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2560 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2661 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2561 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2662 .flags = CLOCK_IN_OMAP343X,
2663 .clkdm_name = "per_clkdm", 2562 .clkdm_name = "per_clkdm",
2664 .recalc = &followparent_recalc, 2563 .recalc = &followparent_recalc,
2665}; 2564};
2666 2565
2667static struct clk gpt9_ick = { 2566static struct clk gpt9_ick = {
2668 .name = "gpt9_ick", 2567 .name = "gpt9_ick",
2568 .ops = &clkops_omap2_dflt_wait,
2669 .parent = &per_l4_ick, 2569 .parent = &per_l4_ick,
2670 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2671 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2571 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2672 .flags = CLOCK_IN_OMAP343X,
2673 .clkdm_name = "per_clkdm", 2572 .clkdm_name = "per_clkdm",
2674 .recalc = &followparent_recalc, 2573 .recalc = &followparent_recalc,
2675}; 2574};
2676 2575
2677static struct clk gpt8_ick = { 2576static struct clk gpt8_ick = {
2678 .name = "gpt8_ick", 2577 .name = "gpt8_ick",
2578 .ops = &clkops_omap2_dflt_wait,
2679 .parent = &per_l4_ick, 2579 .parent = &per_l4_ick,
2680 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2580 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2681 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2581 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2682 .flags = CLOCK_IN_OMAP343X,
2683 .clkdm_name = "per_clkdm", 2582 .clkdm_name = "per_clkdm",
2684 .recalc = &followparent_recalc, 2583 .recalc = &followparent_recalc,
2685}; 2584};
2686 2585
2687static struct clk gpt7_ick = { 2586static struct clk gpt7_ick = {
2688 .name = "gpt7_ick", 2587 .name = "gpt7_ick",
2588 .ops = &clkops_omap2_dflt_wait,
2689 .parent = &per_l4_ick, 2589 .parent = &per_l4_ick,
2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2590 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2691 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2591 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2692 .flags = CLOCK_IN_OMAP343X,
2693 .clkdm_name = "per_clkdm", 2592 .clkdm_name = "per_clkdm",
2694 .recalc = &followparent_recalc, 2593 .recalc = &followparent_recalc,
2695}; 2594};
2696 2595
2697static struct clk gpt6_ick = { 2596static struct clk gpt6_ick = {
2698 .name = "gpt6_ick", 2597 .name = "gpt6_ick",
2598 .ops = &clkops_omap2_dflt_wait,
2699 .parent = &per_l4_ick, 2599 .parent = &per_l4_ick,
2700 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2701 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2601 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2702 .flags = CLOCK_IN_OMAP343X,
2703 .clkdm_name = "per_clkdm", 2602 .clkdm_name = "per_clkdm",
2704 .recalc = &followparent_recalc, 2603 .recalc = &followparent_recalc,
2705}; 2604};
2706 2605
2707static struct clk gpt5_ick = { 2606static struct clk gpt5_ick = {
2708 .name = "gpt5_ick", 2607 .name = "gpt5_ick",
2608 .ops = &clkops_omap2_dflt_wait,
2709 .parent = &per_l4_ick, 2609 .parent = &per_l4_ick,
2710 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2711 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2611 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2712 .flags = CLOCK_IN_OMAP343X,
2713 .clkdm_name = "per_clkdm", 2612 .clkdm_name = "per_clkdm",
2714 .recalc = &followparent_recalc, 2613 .recalc = &followparent_recalc,
2715}; 2614};
2716 2615
2717static struct clk gpt4_ick = { 2616static struct clk gpt4_ick = {
2718 .name = "gpt4_ick", 2617 .name = "gpt4_ick",
2618 .ops = &clkops_omap2_dflt_wait,
2719 .parent = &per_l4_ick, 2619 .parent = &per_l4_ick,
2720 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2721 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2621 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2722 .flags = CLOCK_IN_OMAP343X,
2723 .clkdm_name = "per_clkdm", 2622 .clkdm_name = "per_clkdm",
2724 .recalc = &followparent_recalc, 2623 .recalc = &followparent_recalc,
2725}; 2624};
2726 2625
2727static struct clk gpt3_ick = { 2626static struct clk gpt3_ick = {
2728 .name = "gpt3_ick", 2627 .name = "gpt3_ick",
2628 .ops = &clkops_omap2_dflt_wait,
2729 .parent = &per_l4_ick, 2629 .parent = &per_l4_ick,
2730 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2731 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2631 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2732 .flags = CLOCK_IN_OMAP343X,
2733 .clkdm_name = "per_clkdm", 2632 .clkdm_name = "per_clkdm",
2734 .recalc = &followparent_recalc, 2633 .recalc = &followparent_recalc,
2735}; 2634};
2736 2635
2737static struct clk gpt2_ick = { 2636static struct clk gpt2_ick = {
2738 .name = "gpt2_ick", 2637 .name = "gpt2_ick",
2638 .ops = &clkops_omap2_dflt_wait,
2739 .parent = &per_l4_ick, 2639 .parent = &per_l4_ick,
2740 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2741 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2641 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2742 .flags = CLOCK_IN_OMAP343X,
2743 .clkdm_name = "per_clkdm", 2642 .clkdm_name = "per_clkdm",
2744 .recalc = &followparent_recalc, 2643 .recalc = &followparent_recalc,
2745}; 2644};
2746 2645
2747static struct clk mcbsp2_ick = { 2646static struct clk mcbsp2_ick = {
2748 .name = "mcbsp_ick", 2647 .name = "mcbsp_ick",
2648 .ops = &clkops_omap2_dflt_wait,
2749 .id = 2, 2649 .id = 2,
2750 .parent = &per_l4_ick, 2650 .parent = &per_l4_ick,
2751 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2752 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2652 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2753 .flags = CLOCK_IN_OMAP343X,
2754 .clkdm_name = "per_clkdm", 2653 .clkdm_name = "per_clkdm",
2755 .recalc = &followparent_recalc, 2654 .recalc = &followparent_recalc,
2756}; 2655};
2757 2656
2758static struct clk mcbsp3_ick = { 2657static struct clk mcbsp3_ick = {
2759 .name = "mcbsp_ick", 2658 .name = "mcbsp_ick",
2659 .ops = &clkops_omap2_dflt_wait,
2760 .id = 3, 2660 .id = 3,
2761 .parent = &per_l4_ick, 2661 .parent = &per_l4_ick,
2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2663 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2764 .flags = CLOCK_IN_OMAP343X,
2765 .clkdm_name = "per_clkdm", 2664 .clkdm_name = "per_clkdm",
2766 .recalc = &followparent_recalc, 2665 .recalc = &followparent_recalc,
2767}; 2666};
2768 2667
2769static struct clk mcbsp4_ick = { 2668static struct clk mcbsp4_ick = {
2770 .name = "mcbsp_ick", 2669 .name = "mcbsp_ick",
2670 .ops = &clkops_omap2_dflt_wait,
2771 .id = 4, 2671 .id = 4,
2772 .parent = &per_l4_ick, 2672 .parent = &per_l4_ick,
2773 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2774 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2674 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2775 .flags = CLOCK_IN_OMAP343X,
2776 .clkdm_name = "per_clkdm", 2675 .clkdm_name = "per_clkdm",
2777 .recalc = &followparent_recalc, 2676 .recalc = &followparent_recalc,
2778}; 2677};
2779 2678
2780static const struct clksel mcbsp_234_clksel[] = { 2679static const struct clksel mcbsp_234_clksel[] = {
2781 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, 2680 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2782 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, 2681 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2783 { .parent = NULL } 2682 { .parent = NULL }
2784}; 2683};
2785 2684
2786static struct clk mcbsp2_fck = { 2685static struct clk mcbsp2_fck = {
2787 .name = "mcbsp_fck", 2686 .name = "mcbsp_fck",
2687 .ops = &clkops_omap2_dflt_wait,
2788 .id = 2, 2688 .id = 2,
2789 .init = &omap2_init_clksel_parent, 2689 .init = &omap2_init_clksel_parent,
2790 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2792,13 +2692,13 @@ static struct clk mcbsp2_fck = {
2792 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), 2692 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2793 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, 2693 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2794 .clksel = mcbsp_234_clksel, 2694 .clksel = mcbsp_234_clksel,
2795 .flags = CLOCK_IN_OMAP343X,
2796 .clkdm_name = "per_clkdm", 2695 .clkdm_name = "per_clkdm",
2797 .recalc = &omap2_clksel_recalc, 2696 .recalc = &omap2_clksel_recalc,
2798}; 2697};
2799 2698
2800static struct clk mcbsp3_fck = { 2699static struct clk mcbsp3_fck = {
2801 .name = "mcbsp_fck", 2700 .name = "mcbsp_fck",
2701 .ops = &clkops_omap2_dflt_wait,
2802 .id = 3, 2702 .id = 3,
2803 .init = &omap2_init_clksel_parent, 2703 .init = &omap2_init_clksel_parent,
2804 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2704 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2806,13 +2706,13 @@ static struct clk mcbsp3_fck = {
2806 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2706 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2807 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, 2707 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2808 .clksel = mcbsp_234_clksel, 2708 .clksel = mcbsp_234_clksel,
2809 .flags = CLOCK_IN_OMAP343X,
2810 .clkdm_name = "per_clkdm", 2709 .clkdm_name = "per_clkdm",
2811 .recalc = &omap2_clksel_recalc, 2710 .recalc = &omap2_clksel_recalc,
2812}; 2711};
2813 2712
2814static struct clk mcbsp4_fck = { 2713static struct clk mcbsp4_fck = {
2815 .name = "mcbsp_fck", 2714 .name = "mcbsp_fck",
2715 .ops = &clkops_omap2_dflt_wait,
2816 .id = 4, 2716 .id = 4,
2817 .init = &omap2_init_clksel_parent, 2717 .init = &omap2_init_clksel_parent,
2818 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
@@ -2820,7 +2720,6 @@ static struct clk mcbsp4_fck = {
2820 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), 2720 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2821 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, 2721 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2822 .clksel = mcbsp_234_clksel, 2722 .clksel = mcbsp_234_clksel,
2823 .flags = CLOCK_IN_OMAP343X,
2824 .clkdm_name = "per_clkdm", 2723 .clkdm_name = "per_clkdm",
2825 .recalc = &omap2_clksel_recalc, 2724 .recalc = &omap2_clksel_recalc,
2826}; 2725};
@@ -2864,11 +2763,11 @@ static const struct clksel emu_src_clksel[] = {
2864 */ 2763 */
2865static struct clk emu_src_ck = { 2764static struct clk emu_src_ck = {
2866 .name = "emu_src_ck", 2765 .name = "emu_src_ck",
2766 .ops = &clkops_null,
2867 .init = &omap2_init_clksel_parent, 2767 .init = &omap2_init_clksel_parent,
2868 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2768 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2869 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2769 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2870 .clksel = emu_src_clksel, 2770 .clksel = emu_src_clksel,
2871 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2872 .clkdm_name = "emu_clkdm", 2771 .clkdm_name = "emu_clkdm",
2873 .recalc = &omap2_clksel_recalc, 2772 .recalc = &omap2_clksel_recalc,
2874}; 2773};
@@ -2888,11 +2787,11 @@ static const struct clksel pclk_emu_clksel[] = {
2888 2787
2889static struct clk pclk_fck = { 2788static struct clk pclk_fck = {
2890 .name = "pclk_fck", 2789 .name = "pclk_fck",
2790 .ops = &clkops_null,
2891 .init = &omap2_init_clksel_parent, 2791 .init = &omap2_init_clksel_parent,
2892 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2792 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2893 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2793 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2894 .clksel = pclk_emu_clksel, 2794 .clksel = pclk_emu_clksel,
2895 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2896 .clkdm_name = "emu_clkdm", 2795 .clkdm_name = "emu_clkdm",
2897 .recalc = &omap2_clksel_recalc, 2796 .recalc = &omap2_clksel_recalc,
2898}; 2797};
@@ -2911,11 +2810,11 @@ static const struct clksel pclkx2_emu_clksel[] = {
2911 2810
2912static struct clk pclkx2_fck = { 2811static struct clk pclkx2_fck = {
2913 .name = "pclkx2_fck", 2812 .name = "pclkx2_fck",
2813 .ops = &clkops_null,
2914 .init = &omap2_init_clksel_parent, 2814 .init = &omap2_init_clksel_parent,
2915 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2815 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2916 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2816 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2917 .clksel = pclkx2_emu_clksel, 2817 .clksel = pclkx2_emu_clksel,
2918 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2919 .clkdm_name = "emu_clkdm", 2818 .clkdm_name = "emu_clkdm",
2920 .recalc = &omap2_clksel_recalc, 2819 .recalc = &omap2_clksel_recalc,
2921}; 2820};
@@ -2927,22 +2826,22 @@ static const struct clksel atclk_emu_clksel[] = {
2927 2826
2928static struct clk atclk_fck = { 2827static struct clk atclk_fck = {
2929 .name = "atclk_fck", 2828 .name = "atclk_fck",
2829 .ops = &clkops_null,
2930 .init = &omap2_init_clksel_parent, 2830 .init = &omap2_init_clksel_parent,
2931 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2831 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2932 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2832 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2933 .clksel = atclk_emu_clksel, 2833 .clksel = atclk_emu_clksel,
2934 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2935 .clkdm_name = "emu_clkdm", 2834 .clkdm_name = "emu_clkdm",
2936 .recalc = &omap2_clksel_recalc, 2835 .recalc = &omap2_clksel_recalc,
2937}; 2836};
2938 2837
2939static struct clk traceclk_src_fck = { 2838static struct clk traceclk_src_fck = {
2940 .name = "traceclk_src_fck", 2839 .name = "traceclk_src_fck",
2840 .ops = &clkops_null,
2941 .init = &omap2_init_clksel_parent, 2841 .init = &omap2_init_clksel_parent,
2942 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2842 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2943 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2843 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2944 .clksel = emu_src_clksel, 2844 .clksel = emu_src_clksel,
2945 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2946 .clkdm_name = "emu_clkdm", 2845 .clkdm_name = "emu_clkdm",
2947 .recalc = &omap2_clksel_recalc, 2846 .recalc = &omap2_clksel_recalc,
2948}; 2847};
@@ -2961,11 +2860,11 @@ static const struct clksel traceclk_clksel[] = {
2961 2860
2962static struct clk traceclk_fck = { 2861static struct clk traceclk_fck = {
2963 .name = "traceclk_fck", 2862 .name = "traceclk_fck",
2863 .ops = &clkops_null,
2964 .init = &omap2_init_clksel_parent, 2864 .init = &omap2_init_clksel_parent,
2965 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2865 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2966 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2866 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2967 .clksel = traceclk_clksel, 2867 .clksel = traceclk_clksel,
2968 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2969 .clkdm_name = "emu_clkdm", 2868 .clkdm_name = "emu_clkdm",
2970 .recalc = &omap2_clksel_recalc, 2869 .recalc = &omap2_clksel_recalc,
2971}; 2870};
@@ -2975,27 +2874,27 @@ static struct clk traceclk_fck = {
2975/* SmartReflex fclk (VDD1) */ 2874/* SmartReflex fclk (VDD1) */
2976static struct clk sr1_fck = { 2875static struct clk sr1_fck = {
2977 .name = "sr1_fck", 2876 .name = "sr1_fck",
2877 .ops = &clkops_omap2_dflt_wait,
2978 .parent = &sys_ck, 2878 .parent = &sys_ck,
2979 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2879 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2980 .enable_bit = OMAP3430_EN_SR1_SHIFT, 2880 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2981 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2982 .recalc = &followparent_recalc, 2881 .recalc = &followparent_recalc,
2983}; 2882};
2984 2883
2985/* SmartReflex fclk (VDD2) */ 2884/* SmartReflex fclk (VDD2) */
2986static struct clk sr2_fck = { 2885static struct clk sr2_fck = {
2987 .name = "sr2_fck", 2886 .name = "sr2_fck",
2887 .ops = &clkops_omap2_dflt_wait,
2988 .parent = &sys_ck, 2888 .parent = &sys_ck,
2989 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 2889 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2990 .enable_bit = OMAP3430_EN_SR2_SHIFT, 2890 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2991 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2992 .recalc = &followparent_recalc, 2891 .recalc = &followparent_recalc,
2993}; 2892};
2994 2893
2995static struct clk sr_l4_ick = { 2894static struct clk sr_l4_ick = {
2996 .name = "sr_l4_ick", 2895 .name = "sr_l4_ick",
2896 .ops = &clkops_null, /* RMK: missing? */
2997 .parent = &l4_ick, 2897 .parent = &l4_ick,
2998 .flags = CLOCK_IN_OMAP343X,
2999 .clkdm_name = "core_l4_clkdm", 2898 .clkdm_name = "core_l4_clkdm",
3000 .recalc = &followparent_recalc, 2899 .recalc = &followparent_recalc,
3001}; 2900};
@@ -3005,231 +2904,16 @@ static struct clk sr_l4_ick = {
3005/* XXX This clock no longer exists in 3430 TRM rev F */ 2904/* XXX This clock no longer exists in 3430 TRM rev F */
3006static struct clk gpt12_fck = { 2905static struct clk gpt12_fck = {
3007 .name = "gpt12_fck", 2906 .name = "gpt12_fck",
2907 .ops = &clkops_null,
3008 .parent = &secure_32k_fck, 2908 .parent = &secure_32k_fck,
3009 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
3010 .recalc = &followparent_recalc, 2909 .recalc = &followparent_recalc,
3011}; 2910};
3012 2911
3013static struct clk wdt1_fck = { 2912static struct clk wdt1_fck = {
3014 .name = "wdt1_fck", 2913 .name = "wdt1_fck",
2914 .ops = &clkops_null,
3015 .parent = &secure_32k_fck, 2915 .parent = &secure_32k_fck,
3016 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2916 .recalc = &followparent_recalc,
3017 .recalc = &followparent_recalc,
3018};
3019
3020static struct clk *onchip_34xx_clks[] __initdata = {
3021 &omap_32k_fck,
3022 &virt_12m_ck,
3023 &virt_13m_ck,
3024 &virt_16_8m_ck,
3025 &virt_19_2m_ck,
3026 &virt_26m_ck,
3027 &virt_38_4m_ck,
3028 &osc_sys_ck,
3029 &sys_ck,
3030 &sys_altclk,
3031 &mcbsp_clks,
3032 &sys_clkout1,
3033 &dpll1_ck,
3034 &dpll1_x2_ck,
3035 &dpll1_x2m2_ck,
3036 &dpll2_ck,
3037 &dpll2_m2_ck,
3038 &dpll3_ck,
3039 &core_ck,
3040 &dpll3_x2_ck,
3041 &dpll3_m2_ck,
3042 &dpll3_m2x2_ck,
3043 &dpll3_m3_ck,
3044 &dpll3_m3x2_ck,
3045 &emu_core_alwon_ck,
3046 &dpll4_ck,
3047 &dpll4_x2_ck,
3048 &omap_96m_alwon_fck,
3049 &omap_96m_fck,
3050 &cm_96m_fck,
3051 &virt_omap_54m_fck,
3052 &omap_54m_fck,
3053 &omap_48m_fck,
3054 &omap_12m_fck,
3055 &dpll4_m2_ck,
3056 &dpll4_m2x2_ck,
3057 &dpll4_m3_ck,
3058 &dpll4_m3x2_ck,
3059 &dpll4_m4_ck,
3060 &dpll4_m4x2_ck,
3061 &dpll4_m5_ck,
3062 &dpll4_m5x2_ck,
3063 &dpll4_m6_ck,
3064 &dpll4_m6x2_ck,
3065 &emu_per_alwon_ck,
3066 &dpll5_ck,
3067 &dpll5_m2_ck,
3068 &omap_120m_fck,
3069 &clkout2_src_ck,
3070 &sys_clkout2,
3071 &corex2_fck,
3072 &dpll1_fck,
3073 &mpu_ck,
3074 &arm_fck,
3075 &emu_mpu_alwon_ck,
3076 &dpll2_fck,
3077 &iva2_ck,
3078 &l3_ick,
3079 &l4_ick,
3080 &rm_ick,
3081 &gfx_l3_ck,
3082 &gfx_l3_fck,
3083 &gfx_l3_ick,
3084 &gfx_cg1_ck,
3085 &gfx_cg2_ck,
3086 &sgx_fck,
3087 &sgx_ick,
3088 &d2d_26m_fck,
3089 &gpt10_fck,
3090 &gpt11_fck,
3091 &cpefuse_fck,
3092 &ts_fck,
3093 &usbtll_fck,
3094 &core_96m_fck,
3095 &mmchs3_fck,
3096 &mmchs2_fck,
3097 &mspro_fck,
3098 &mmchs1_fck,
3099 &i2c3_fck,
3100 &i2c2_fck,
3101 &i2c1_fck,
3102 &mcbsp5_fck,
3103 &mcbsp1_fck,
3104 &core_48m_fck,
3105 &mcspi4_fck,
3106 &mcspi3_fck,
3107 &mcspi2_fck,
3108 &mcspi1_fck,
3109 &uart2_fck,
3110 &uart1_fck,
3111 &fshostusb_fck,
3112 &core_12m_fck,
3113 &hdq_fck,
3114 &ssi_ssr_fck,
3115 &ssi_sst_fck,
3116 &core_l3_ick,
3117 &hsotgusb_ick,
3118 &sdrc_ick,
3119 &gpmc_fck,
3120 &security_l3_ick,
3121 &pka_ick,
3122 &core_l4_ick,
3123 &usbtll_ick,
3124 &mmchs3_ick,
3125 &icr_ick,
3126 &aes2_ick,
3127 &sha12_ick,
3128 &des2_ick,
3129 &mmchs2_ick,
3130 &mmchs1_ick,
3131 &mspro_ick,
3132 &hdq_ick,
3133 &mcspi4_ick,
3134 &mcspi3_ick,
3135 &mcspi2_ick,
3136 &mcspi1_ick,
3137 &i2c3_ick,
3138 &i2c2_ick,
3139 &i2c1_ick,
3140 &uart2_ick,
3141 &uart1_ick,
3142 &gpt11_ick,
3143 &gpt10_ick,
3144 &mcbsp5_ick,
3145 &mcbsp1_ick,
3146 &fac_ick,
3147 &mailboxes_ick,
3148 &omapctrl_ick,
3149 &ssi_l4_ick,
3150 &ssi_ick,
3151 &usb_l4_ick,
3152 &security_l4_ick2,
3153 &aes1_ick,
3154 &rng_ick,
3155 &sha11_ick,
3156 &des1_ick,
3157 &dss1_alwon_fck,
3158 &dss_tv_fck,
3159 &dss_96m_fck,
3160 &dss2_alwon_fck,
3161 &dss_ick,
3162 &cam_mclk,
3163 &cam_ick,
3164 &usbhost_120m_fck,
3165 &usbhost_48m_fck,
3166 &usbhost_ick,
3167 &usbhost_sar_fck,
3168 &usim_fck,
3169 &gpt1_fck,
3170 &wkup_32k_fck,
3171 &gpio1_dbck,
3172 &wdt2_fck,
3173 &wkup_l4_ick,
3174 &usim_ick,
3175 &wdt2_ick,
3176 &wdt1_ick,
3177 &gpio1_ick,
3178 &omap_32ksync_ick,
3179 &gpt12_ick,
3180 &gpt1_ick,
3181 &per_96m_fck,
3182 &per_48m_fck,
3183 &uart3_fck,
3184 &gpt2_fck,
3185 &gpt3_fck,
3186 &gpt4_fck,
3187 &gpt5_fck,
3188 &gpt6_fck,
3189 &gpt7_fck,
3190 &gpt8_fck,
3191 &gpt9_fck,
3192 &per_32k_alwon_fck,
3193 &gpio6_dbck,
3194 &gpio5_dbck,
3195 &gpio4_dbck,
3196 &gpio3_dbck,
3197 &gpio2_dbck,
3198 &wdt3_fck,
3199 &per_l4_ick,
3200 &gpio6_ick,
3201 &gpio5_ick,
3202 &gpio4_ick,
3203 &gpio3_ick,
3204 &gpio2_ick,
3205 &wdt3_ick,
3206 &uart3_ick,
3207 &gpt9_ick,
3208 &gpt8_ick,
3209 &gpt7_ick,
3210 &gpt6_ick,
3211 &gpt5_ick,
3212 &gpt4_ick,
3213 &gpt3_ick,
3214 &gpt2_ick,
3215 &mcbsp2_ick,
3216 &mcbsp3_ick,
3217 &mcbsp4_ick,
3218 &mcbsp2_fck,
3219 &mcbsp3_fck,
3220 &mcbsp4_fck,
3221 &emu_src_ck,
3222 &pclk_fck,
3223 &pclkx2_fck,
3224 &atclk_fck,
3225 &traceclk_src_fck,
3226 &traceclk_fck,
3227 &sr1_fck,
3228 &sr2_fck,
3229 &sr_l4_ick,
3230 &secure_32k_fck,
3231 &gpt12_fck,
3232 &wdt1_fck,
3233}; 2917};
3234 2918
3235#endif 2919#endif
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 4c3ce9cfd948..0e7d501865b6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -22,6 +22,7 @@
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/limits.h> 24#include <linux/limits.h>
25#include <linux/err.h>
25 26
26#include <linux/io.h> 27#include <linux/io.h>
27 28
@@ -71,16 +72,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
71 if (!omap_chip_is(autodep->omap_chip)) 72 if (!omap_chip_is(autodep->omap_chip))
72 return; 73 return;
73 74
74 pwrdm = pwrdm_lookup(autodep->pwrdm_name); 75 pwrdm = pwrdm_lookup(autodep->pwrdm.name);
75 if (!pwrdm) { 76 if (!pwrdm) {
76 pr_debug("clockdomain: _autodep_lookup: powerdomain %s " 77 pr_err("clockdomain: autodeps: powerdomain %s does not exist\n",
77 "does not exist\n", autodep->pwrdm_name); 78 autodep->pwrdm.name);
78 WARN_ON(1); 79 pwrdm = ERR_PTR(-ENOENT);
79 return;
80 } 80 }
81 autodep->pwrdm = pwrdm; 81 autodep->pwrdm.ptr = pwrdm;
82
83 return;
84} 82}
85 83
86/* 84/*
@@ -95,16 +93,19 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
95{ 93{
96 struct clkdm_pwrdm_autodep *autodep; 94 struct clkdm_pwrdm_autodep *autodep;
97 95
98 for (autodep = autodeps; autodep->pwrdm_name; autodep++) { 96 for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
99 if (!autodep->pwrdm) 97 if (IS_ERR(autodep->pwrdm.ptr))
98 continue;
99
100 if (!omap_chip_is(autodep->omap_chip))
100 continue; 101 continue;
101 102
102 pr_debug("clockdomain: adding %s sleepdep/wkdep for " 103 pr_debug("clockdomain: adding %s sleepdep/wkdep for "
103 "pwrdm %s\n", autodep->pwrdm_name, 104 "pwrdm %s\n", autodep->pwrdm.ptr->name,
104 clkdm->pwrdm->name); 105 clkdm->pwrdm.ptr->name);
105 106
106 pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm); 107 pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
107 pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm); 108 pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
108 } 109 }
109} 110}
110 111
@@ -120,16 +121,19 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
120{ 121{
121 struct clkdm_pwrdm_autodep *autodep; 122 struct clkdm_pwrdm_autodep *autodep;
122 123
123 for (autodep = autodeps; autodep->pwrdm_name; autodep++) { 124 for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
124 if (!autodep->pwrdm) 125 if (IS_ERR(autodep->pwrdm.ptr))
126 continue;
127
128 if (!omap_chip_is(autodep->omap_chip))
125 continue; 129 continue;
126 130
127 pr_debug("clockdomain: removing %s sleepdep/wkdep for " 131 pr_debug("clockdomain: removing %s sleepdep/wkdep for "
128 "pwrdm %s\n", autodep->pwrdm_name, 132 "pwrdm %s\n", autodep->pwrdm.ptr->name,
129 clkdm->pwrdm->name); 133 clkdm->pwrdm.ptr->name);
130 134
131 pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm); 135 pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
132 pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm); 136 pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
133 } 137 }
134} 138}
135 139
@@ -179,7 +183,7 @@ void clkdm_init(struct clockdomain **clkdms,
179 183
180 autodeps = init_autodeps; 184 autodeps = init_autodeps;
181 if (autodeps) 185 if (autodeps)
182 for (autodep = autodeps; autodep->pwrdm_name; autodep++) 186 for (autodep = autodeps; autodep->pwrdm.ptr; autodep++)
183 _autodep_lookup(autodep); 187 _autodep_lookup(autodep);
184} 188}
185 189
@@ -202,20 +206,20 @@ int clkdm_register(struct clockdomain *clkdm)
202 if (!omap_chip_is(clkdm->omap_chip)) 206 if (!omap_chip_is(clkdm->omap_chip))
203 return -EINVAL; 207 return -EINVAL;
204 208
205 pwrdm = pwrdm_lookup(clkdm->pwrdm_name); 209 pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
206 if (!pwrdm) { 210 if (!pwrdm) {
207 pr_debug("clockdomain: clkdm_register %s: powerdomain %s " 211 pr_err("clockdomain: %s: powerdomain %s does not exist\n",
208 "does not exist\n", clkdm->name, clkdm->pwrdm_name); 212 clkdm->name, clkdm->pwrdm.name);
209 return -EINVAL; 213 return -EINVAL;
210 } 214 }
211 clkdm->pwrdm = pwrdm; 215 clkdm->pwrdm.ptr = pwrdm;
212 216
213 mutex_lock(&clkdm_mutex); 217 mutex_lock(&clkdm_mutex);
214 /* Verify that the clockdomain is not already registered */ 218 /* Verify that the clockdomain is not already registered */
215 if (_clkdm_lookup(clkdm->name)) { 219 if (_clkdm_lookup(clkdm->name)) {
216 ret = -EEXIST; 220 ret = -EEXIST;
217 goto cr_unlock; 221 goto cr_unlock;
218 }; 222 }
219 223
220 list_add(&clkdm->node, &clkdm_list); 224 list_add(&clkdm->node, &clkdm_list);
221 225
@@ -242,7 +246,7 @@ int clkdm_unregister(struct clockdomain *clkdm)
242 if (!clkdm) 246 if (!clkdm)
243 return -EINVAL; 247 return -EINVAL;
244 248
245 pwrdm_del_clkdm(clkdm->pwrdm, clkdm); 249 pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm);
246 250
247 mutex_lock(&clkdm_mutex); 251 mutex_lock(&clkdm_mutex);
248 list_del(&clkdm->node); 252 list_del(&clkdm->node);
@@ -327,7 +331,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
327 if (!clkdm) 331 if (!clkdm)
328 return NULL; 332 return NULL;
329 333
330 return clkdm->pwrdm; 334 return clkdm->pwrdm.ptr;
331} 335}
332 336
333 337
@@ -348,7 +352,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
348 if (!clkdm) 352 if (!clkdm)
349 return -EINVAL; 353 return -EINVAL;
350 354
351 v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); 355 v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
352 v &= clkdm->clktrctrl_mask; 356 v &= clkdm->clktrctrl_mask;
353 v >>= __ffs(clkdm->clktrctrl_mask); 357 v >>= __ffs(clkdm->clktrctrl_mask);
354 358
@@ -380,7 +384,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
380 if (cpu_is_omap24xx()) { 384 if (cpu_is_omap24xx()) {
381 385
382 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, 386 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
383 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); 387 clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
384 388
385 } else if (cpu_is_omap34xx()) { 389 } else if (cpu_is_omap34xx()) {
386 390
@@ -388,7 +392,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
388 __ffs(clkdm->clktrctrl_mask)); 392 __ffs(clkdm->clktrctrl_mask));
389 393
390 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, 394 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
391 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); 395 clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
392 396
393 } else { 397 } else {
394 BUG(); 398 BUG();
@@ -422,7 +426,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
422 if (cpu_is_omap24xx()) { 426 if (cpu_is_omap24xx()) {
423 427
424 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, 428 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
425 clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); 429 clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);
426 430
427 } else if (cpu_is_omap34xx()) { 431 } else if (cpu_is_omap34xx()) {
428 432
@@ -430,7 +434,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
430 __ffs(clkdm->clktrctrl_mask)); 434 __ffs(clkdm->clktrctrl_mask));
431 435
432 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, 436 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
433 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); 437 clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
434 438
435 } else { 439 } else {
436 BUG(); 440 BUG();
@@ -478,7 +482,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
478 482
479 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, 483 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
480 v << __ffs(clkdm->clktrctrl_mask), 484 v << __ffs(clkdm->clktrctrl_mask),
481 clkdm->pwrdm->prcm_offs, 485 clkdm->pwrdm.ptr->prcm_offs,
482 CM_CLKSTCTRL); 486 CM_CLKSTCTRL);
483} 487}
484 488
@@ -516,7 +520,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
516 520
517 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, 521 cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
518 v << __ffs(clkdm->clktrctrl_mask), 522 v << __ffs(clkdm->clktrctrl_mask),
519 clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); 523 clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
520 524
521 if (atomic_read(&clkdm->usecount) > 0) 525 if (atomic_read(&clkdm->usecount) > 0)
522 _clkdm_del_autodeps(clkdm); 526 _clkdm_del_autodeps(clkdm);
@@ -567,6 +571,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
567 else 571 else
568 omap2_clkdm_wakeup(clkdm); 572 omap2_clkdm_wakeup(clkdm);
569 573
574 pwrdm_wait_transition(clkdm->pwrdm.ptr);
575
570 return 0; 576 return 0;
571} 577}
572 578
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index cd86dcc7b424..281d5da19188 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -14,12 +14,29 @@
14 14
15/* 15/*
16 * OMAP2/3-common clockdomains 16 * OMAP2/3-common clockdomains
17 *
18 * Even though the 2420 has a single PRCM module from the
19 * interconnect's perspective, internally it does appear to have
20 * separate PRM and CM clockdomains. The usual test case is
21 * sys_clkout/sys_clkout2.
17 */ 22 */
18 23
19/* This is an implicit clockdomain - it is never defined as such in TRM */ 24/* This is an implicit clockdomain - it is never defined as such in TRM */
20static struct clockdomain wkup_clkdm = { 25static struct clockdomain wkup_clkdm = {
21 .name = "wkup_clkdm", 26 .name = "wkup_clkdm",
22 .pwrdm_name = "wkup_pwrdm", 27 .pwrdm = { .name = "wkup_pwrdm" },
28 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
29};
30
31static struct clockdomain prm_clkdm = {
32 .name = "prm_clkdm",
33 .pwrdm = { .name = "wkup_pwrdm" },
34 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
35};
36
37static struct clockdomain cm_clkdm = {
38 .name = "cm_clkdm",
39 .pwrdm = { .name = "core_pwrdm" },
23 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), 40 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
24}; 41};
25 42
@@ -31,7 +48,7 @@ static struct clockdomain wkup_clkdm = {
31 48
32static struct clockdomain mpu_2420_clkdm = { 49static struct clockdomain mpu_2420_clkdm = {
33 .name = "mpu_clkdm", 50 .name = "mpu_clkdm",
34 .pwrdm_name = "mpu_pwrdm", 51 .pwrdm = { .name = "mpu_pwrdm" },
35 .flags = CLKDM_CAN_HWSUP, 52 .flags = CLKDM_CAN_HWSUP,
36 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, 53 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
37 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -39,7 +56,7 @@ static struct clockdomain mpu_2420_clkdm = {
39 56
40static struct clockdomain iva1_2420_clkdm = { 57static struct clockdomain iva1_2420_clkdm = {
41 .name = "iva1_clkdm", 58 .name = "iva1_clkdm",
42 .pwrdm_name = "dsp_pwrdm", 59 .pwrdm = { .name = "dsp_pwrdm" },
43 .flags = CLKDM_CAN_HWSUP_SWSUP, 60 .flags = CLKDM_CAN_HWSUP_SWSUP,
44 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, 61 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -56,7 +73,7 @@ static struct clockdomain iva1_2420_clkdm = {
56 73
57static struct clockdomain mpu_2430_clkdm = { 74static struct clockdomain mpu_2430_clkdm = {
58 .name = "mpu_clkdm", 75 .name = "mpu_clkdm",
59 .pwrdm_name = "mpu_pwrdm", 76 .pwrdm = { .name = "mpu_pwrdm" },
60 .flags = CLKDM_CAN_HWSUP_SWSUP, 77 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, 78 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -64,7 +81,7 @@ static struct clockdomain mpu_2430_clkdm = {
64 81
65static struct clockdomain mdm_clkdm = { 82static struct clockdomain mdm_clkdm = {
66 .name = "mdm_clkdm", 83 .name = "mdm_clkdm",
67 .pwrdm_name = "mdm_pwrdm", 84 .pwrdm = { .name = "mdm_pwrdm" },
68 .flags = CLKDM_CAN_HWSUP_SWSUP, 85 .flags = CLKDM_CAN_HWSUP_SWSUP,
69 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, 86 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -81,7 +98,7 @@ static struct clockdomain mdm_clkdm = {
81 98
82static struct clockdomain dsp_clkdm = { 99static struct clockdomain dsp_clkdm = {
83 .name = "dsp_clkdm", 100 .name = "dsp_clkdm",
84 .pwrdm_name = "dsp_pwrdm", 101 .pwrdm = { .name = "dsp_pwrdm" },
85 .flags = CLKDM_CAN_HWSUP_SWSUP, 102 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, 103 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 104 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -89,7 +106,7 @@ static struct clockdomain dsp_clkdm = {
89 106
90static struct clockdomain gfx_24xx_clkdm = { 107static struct clockdomain gfx_24xx_clkdm = {
91 .name = "gfx_clkdm", 108 .name = "gfx_clkdm",
92 .pwrdm_name = "gfx_pwrdm", 109 .pwrdm = { .name = "gfx_pwrdm" },
93 .flags = CLKDM_CAN_HWSUP_SWSUP, 110 .flags = CLKDM_CAN_HWSUP_SWSUP,
94 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, 111 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 112 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -97,7 +114,7 @@ static struct clockdomain gfx_24xx_clkdm = {
97 114
98static struct clockdomain core_l3_24xx_clkdm = { 115static struct clockdomain core_l3_24xx_clkdm = {
99 .name = "core_l3_clkdm", 116 .name = "core_l3_clkdm",
100 .pwrdm_name = "core_pwrdm", 117 .pwrdm = { .name = "core_pwrdm" },
101 .flags = CLKDM_CAN_HWSUP, 118 .flags = CLKDM_CAN_HWSUP,
102 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, 119 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -105,7 +122,7 @@ static struct clockdomain core_l3_24xx_clkdm = {
105 122
106static struct clockdomain core_l4_24xx_clkdm = { 123static struct clockdomain core_l4_24xx_clkdm = {
107 .name = "core_l4_clkdm", 124 .name = "core_l4_clkdm",
108 .pwrdm_name = "core_pwrdm", 125 .pwrdm = { .name = "core_pwrdm" },
109 .flags = CLKDM_CAN_HWSUP, 126 .flags = CLKDM_CAN_HWSUP,
110 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, 127 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -113,7 +130,7 @@ static struct clockdomain core_l4_24xx_clkdm = {
113 130
114static struct clockdomain dss_24xx_clkdm = { 131static struct clockdomain dss_24xx_clkdm = {
115 .name = "dss_clkdm", 132 .name = "dss_clkdm",
116 .pwrdm_name = "core_pwrdm", 133 .pwrdm = { .name = "core_pwrdm" },
117 .flags = CLKDM_CAN_HWSUP, 134 .flags = CLKDM_CAN_HWSUP,
118 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, 135 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), 136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -130,7 +147,7 @@ static struct clockdomain dss_24xx_clkdm = {
130 147
131static struct clockdomain mpu_34xx_clkdm = { 148static struct clockdomain mpu_34xx_clkdm = {
132 .name = "mpu_clkdm", 149 .name = "mpu_clkdm",
133 .pwrdm_name = "mpu_pwrdm", 150 .pwrdm = { .name = "mpu_pwrdm" },
134 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, 151 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
135 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, 152 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 153 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -138,7 +155,7 @@ static struct clockdomain mpu_34xx_clkdm = {
138 155
139static struct clockdomain neon_clkdm = { 156static struct clockdomain neon_clkdm = {
140 .name = "neon_clkdm", 157 .name = "neon_clkdm",
141 .pwrdm_name = "neon_pwrdm", 158 .pwrdm = { .name = "neon_pwrdm" },
142 .flags = CLKDM_CAN_HWSUP_SWSUP, 159 .flags = CLKDM_CAN_HWSUP_SWSUP,
143 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, 160 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
144 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 161 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -146,7 +163,7 @@ static struct clockdomain neon_clkdm = {
146 163
147static struct clockdomain iva2_clkdm = { 164static struct clockdomain iva2_clkdm = {
148 .name = "iva2_clkdm", 165 .name = "iva2_clkdm",
149 .pwrdm_name = "iva2_pwrdm", 166 .pwrdm = { .name = "iva2_pwrdm" },
150 .flags = CLKDM_CAN_HWSUP_SWSUP, 167 .flags = CLKDM_CAN_HWSUP_SWSUP,
151 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, 168 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 169 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -154,7 +171,7 @@ static struct clockdomain iva2_clkdm = {
154 171
155static struct clockdomain gfx_3430es1_clkdm = { 172static struct clockdomain gfx_3430es1_clkdm = {
156 .name = "gfx_clkdm", 173 .name = "gfx_clkdm",
157 .pwrdm_name = "gfx_pwrdm", 174 .pwrdm = { .name = "gfx_pwrdm" },
158 .flags = CLKDM_CAN_HWSUP_SWSUP, 175 .flags = CLKDM_CAN_HWSUP_SWSUP,
159 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, 176 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), 177 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
@@ -162,10 +179,10 @@ static struct clockdomain gfx_3430es1_clkdm = {
162 179
163static struct clockdomain sgx_clkdm = { 180static struct clockdomain sgx_clkdm = {
164 .name = "sgx_clkdm", 181 .name = "sgx_clkdm",
165 .pwrdm_name = "sgx_pwrdm", 182 .pwrdm = { .name = "sgx_pwrdm" },
166 .flags = CLKDM_CAN_HWSUP_SWSUP, 183 .flags = CLKDM_CAN_HWSUP_SWSUP,
167 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, 184 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), 185 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
169}; 186};
170 187
171/* 188/*
@@ -177,7 +194,7 @@ static struct clockdomain sgx_clkdm = {
177 */ 194 */
178static struct clockdomain d2d_clkdm = { 195static struct clockdomain d2d_clkdm = {
179 .name = "d2d_clkdm", 196 .name = "d2d_clkdm",
180 .pwrdm_name = "core_pwrdm", 197 .pwrdm = { .name = "core_pwrdm" },
181 .flags = CLKDM_CAN_HWSUP, 198 .flags = CLKDM_CAN_HWSUP,
182 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, 199 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -185,7 +202,7 @@ static struct clockdomain d2d_clkdm = {
185 202
186static struct clockdomain core_l3_34xx_clkdm = { 203static struct clockdomain core_l3_34xx_clkdm = {
187 .name = "core_l3_clkdm", 204 .name = "core_l3_clkdm",
188 .pwrdm_name = "core_pwrdm", 205 .pwrdm = { .name = "core_pwrdm" },
189 .flags = CLKDM_CAN_HWSUP, 206 .flags = CLKDM_CAN_HWSUP,
190 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, 207 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 208 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -193,7 +210,7 @@ static struct clockdomain core_l3_34xx_clkdm = {
193 210
194static struct clockdomain core_l4_34xx_clkdm = { 211static struct clockdomain core_l4_34xx_clkdm = {
195 .name = "core_l4_clkdm", 212 .name = "core_l4_clkdm",
196 .pwrdm_name = "core_pwrdm", 213 .pwrdm = { .name = "core_pwrdm" },
197 .flags = CLKDM_CAN_HWSUP, 214 .flags = CLKDM_CAN_HWSUP,
198 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, 215 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
199 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -201,7 +218,7 @@ static struct clockdomain core_l4_34xx_clkdm = {
201 218
202static struct clockdomain dss_34xx_clkdm = { 219static struct clockdomain dss_34xx_clkdm = {
203 .name = "dss_clkdm", 220 .name = "dss_clkdm",
204 .pwrdm_name = "dss_pwrdm", 221 .pwrdm = { .name = "dss_pwrdm" },
205 .flags = CLKDM_CAN_HWSUP_SWSUP, 222 .flags = CLKDM_CAN_HWSUP_SWSUP,
206 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, 223 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -209,7 +226,7 @@ static struct clockdomain dss_34xx_clkdm = {
209 226
210static struct clockdomain cam_clkdm = { 227static struct clockdomain cam_clkdm = {
211 .name = "cam_clkdm", 228 .name = "cam_clkdm",
212 .pwrdm_name = "cam_pwrdm", 229 .pwrdm = { .name = "cam_pwrdm" },
213 .flags = CLKDM_CAN_HWSUP_SWSUP, 230 .flags = CLKDM_CAN_HWSUP_SWSUP,
214 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, 231 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -217,28 +234,62 @@ static struct clockdomain cam_clkdm = {
217 234
218static struct clockdomain usbhost_clkdm = { 235static struct clockdomain usbhost_clkdm = {
219 .name = "usbhost_clkdm", 236 .name = "usbhost_clkdm",
220 .pwrdm_name = "usbhost_pwrdm", 237 .pwrdm = { .name = "usbhost_pwrdm" },
221 .flags = CLKDM_CAN_HWSUP_SWSUP, 238 .flags = CLKDM_CAN_HWSUP_SWSUP,
222 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, 239 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), 240 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
224}; 241};
225 242
226static struct clockdomain per_clkdm = { 243static struct clockdomain per_clkdm = {
227 .name = "per_clkdm", 244 .name = "per_clkdm",
228 .pwrdm_name = "per_pwrdm", 245 .pwrdm = { .name = "per_pwrdm" },
229 .flags = CLKDM_CAN_HWSUP_SWSUP, 246 .flags = CLKDM_CAN_HWSUP_SWSUP,
230 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, 247 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
231 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
232}; 249};
233 250
251/*
252 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
253 * switched of even if sdti is in use
254 */
234static struct clockdomain emu_clkdm = { 255static struct clockdomain emu_clkdm = {
235 .name = "emu_clkdm", 256 .name = "emu_clkdm",
236 .pwrdm_name = "emu_pwrdm", 257 .pwrdm = { .name = "emu_pwrdm" },
237 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP, 258 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
238 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, 259 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 260 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
240}; 261};
241 262
263static struct clockdomain dpll1_clkdm = {
264 .name = "dpll1_clkdm",
265 .pwrdm = { .name = "dpll1_pwrdm" },
266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
267};
268
269static struct clockdomain dpll2_clkdm = {
270 .name = "dpll2_clkdm",
271 .pwrdm = { .name = "dpll2_pwrdm" },
272 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
273};
274
275static struct clockdomain dpll3_clkdm = {
276 .name = "dpll3_clkdm",
277 .pwrdm = { .name = "dpll3_pwrdm" },
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
279};
280
281static struct clockdomain dpll4_clkdm = {
282 .name = "dpll4_clkdm",
283 .pwrdm = { .name = "dpll4_pwrdm" },
284 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
285};
286
287static struct clockdomain dpll5_clkdm = {
288 .name = "dpll5_clkdm",
289 .pwrdm = { .name = "dpll5_pwrdm" },
290 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
291};
292
242#endif /* CONFIG_ARCH_OMAP34XX */ 293#endif /* CONFIG_ARCH_OMAP34XX */
243 294
244/* 295/*
@@ -247,14 +298,16 @@ static struct clockdomain emu_clkdm = {
247 298
248static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { 299static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
249 { 300 {
250 .pwrdm_name = "mpu_pwrdm", 301 .pwrdm = { .name = "mpu_pwrdm" },
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
252 }, 303 },
253 { 304 {
254 .pwrdm_name = "iva2_pwrdm", 305 .pwrdm = { .name = "iva2_pwrdm" },
255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
256 }, 307 },
257 { NULL } 308 {
309 .pwrdm = { .name = NULL },
310 }
258}; 311};
259 312
260/* 313/*
@@ -264,6 +317,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
264static struct clockdomain *clockdomains_omap[] = { 317static struct clockdomain *clockdomains_omap[] = {
265 318
266 &wkup_clkdm, 319 &wkup_clkdm,
320 &cm_clkdm,
321 &prm_clkdm,
267 322
268#ifdef CONFIG_ARCH_OMAP2420 323#ifdef CONFIG_ARCH_OMAP2420
269 &mpu_2420_clkdm, 324 &mpu_2420_clkdm,
@@ -297,6 +352,11 @@ static struct clockdomain *clockdomains_omap[] = {
297 &usbhost_clkdm, 352 &usbhost_clkdm,
298 &per_clkdm, 353 &per_clkdm,
299 &emu_clkdm, 354 &emu_clkdm,
355 &dpll1_clkdm,
356 &dpll2_clkdm,
357 &dpll3_clkdm,
358 &dpll4_clkdm,
359 &dpll5_clkdm,
300#endif 360#endif
301 361
302 NULL, 362 NULL,
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 1098ecfab861..297a2fe634ea 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -110,35 +110,56 @@
110#define OMAP24XX_EN_DES (1 << 0) 110#define OMAP24XX_EN_DES (1 << 0)
111 111
112/* CM_IDLEST1_CORE specific bits */ 112/* CM_IDLEST1_CORE specific bits */
113#define OMAP24XX_ST_MAILBOXES (1 << 30) 113#define OMAP24XX_ST_MAILBOXES_SHIFT 30
114#define OMAP24XX_ST_WDT4 (1 << 29) 114#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
115#define OMAP2420_ST_WDT3 (1 << 28) 115#define OMAP24XX_ST_WDT4_SHIFT 29
116#define OMAP24XX_ST_MSPRO (1 << 27) 116#define OMAP24XX_ST_WDT4_MASK (1 << 29)
117#define OMAP24XX_ST_FAC (1 << 25) 117#define OMAP2420_ST_WDT3_SHIFT 28
118#define OMAP2420_ST_EAC (1 << 24) 118#define OMAP2420_ST_WDT3_MASK (1 << 28)
119#define OMAP24XX_ST_HDQ (1 << 23) 119#define OMAP24XX_ST_MSPRO_SHIFT 27
120#define OMAP24XX_ST_I2C2 (1 << 20) 120#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
121#define OMAP24XX_ST_I2C1 (1 << 19) 121#define OMAP24XX_ST_FAC_SHIFT 25
122#define OMAP24XX_ST_MCBSP2 (1 << 16) 122#define OMAP24XX_ST_FAC_MASK (1 << 25)
123#define OMAP24XX_ST_MCBSP1 (1 << 15) 123#define OMAP2420_ST_EAC_SHIFT 24
124#define OMAP24XX_ST_DSS (1 << 0) 124#define OMAP2420_ST_EAC_MASK (1 << 24)
125#define OMAP24XX_ST_HDQ_SHIFT 23
126#define OMAP24XX_ST_HDQ_MASK (1 << 23)
127#define OMAP2420_ST_I2C2_SHIFT 20
128#define OMAP2420_ST_I2C2_MASK (1 << 20)
129#define OMAP2420_ST_I2C1_SHIFT 19
130#define OMAP2420_ST_I2C1_MASK (1 << 19)
131#define OMAP24XX_ST_MCBSP2_SHIFT 16
132#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
133#define OMAP24XX_ST_MCBSP1_SHIFT 15
134#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
135#define OMAP24XX_ST_DSS_SHIFT 0
136#define OMAP24XX_ST_DSS_MASK (1 << 0)
125 137
126/* CM_IDLEST2_CORE */ 138/* CM_IDLEST2_CORE */
127#define OMAP2430_ST_MCBSP5 (1 << 5) 139#define OMAP2430_ST_MCBSP5_SHIFT 5
128#define OMAP2430_ST_MCBSP4 (1 << 4) 140#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
129#define OMAP2430_ST_MCBSP3 (1 << 3) 141#define OMAP2430_ST_MCBSP4_SHIFT 4
130#define OMAP24XX_ST_SSI (1 << 1) 142#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
143#define OMAP2430_ST_MCBSP3_SHIFT 3
144#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
145#define OMAP24XX_ST_SSI_SHIFT 1
146#define OMAP24XX_ST_SSI_MASK (1 << 1)
131 147
132/* CM_IDLEST3_CORE */ 148/* CM_IDLEST3_CORE */
133/* 2430 only */ 149/* 2430 only */
134#define OMAP2430_ST_SDRC (1 << 2) 150#define OMAP2430_ST_SDRC_MASK (1 << 2)
135 151
136/* CM_IDLEST4_CORE */ 152/* CM_IDLEST4_CORE */
137#define OMAP24XX_ST_PKA (1 << 4) 153#define OMAP24XX_ST_PKA_SHIFT 4
138#define OMAP24XX_ST_AES (1 << 3) 154#define OMAP24XX_ST_PKA_MASK (1 << 4)
139#define OMAP24XX_ST_RNG (1 << 2) 155#define OMAP24XX_ST_AES_SHIFT 3
140#define OMAP24XX_ST_SHA (1 << 1) 156#define OMAP24XX_ST_AES_MASK (1 << 3)
141#define OMAP24XX_ST_DES (1 << 0) 157#define OMAP24XX_ST_RNG_SHIFT 2
158#define OMAP24XX_ST_RNG_MASK (1 << 2)
159#define OMAP24XX_ST_SHA_SHIFT 1
160#define OMAP24XX_ST_SHA_MASK (1 << 1)
161#define OMAP24XX_ST_DES_SHIFT 0
162#define OMAP24XX_ST_DES_MASK (1 << 0)
142 163
143/* CM_AUTOIDLE1_CORE */ 164/* CM_AUTOIDLE1_CORE */
144#define OMAP24XX_AUTO_CAM (1 << 31) 165#define OMAP24XX_AUTO_CAM (1 << 31)
@@ -275,11 +296,16 @@
275#define OMAP24XX_EN_32KSYNC (1 << 1) 296#define OMAP24XX_EN_32KSYNC (1 << 1)
276 297
277/* CM_IDLEST_WKUP specific bits */ 298/* CM_IDLEST_WKUP specific bits */
278#define OMAP2430_ST_ICR (1 << 6) 299#define OMAP2430_ST_ICR_SHIFT 6
279#define OMAP24XX_ST_OMAPCTRL (1 << 5) 300#define OMAP2430_ST_ICR_MASK (1 << 6)
280#define OMAP24XX_ST_WDT1 (1 << 4) 301#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
281#define OMAP24XX_ST_MPU_WDT (1 << 3) 302#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
282#define OMAP24XX_ST_32KSYNC (1 << 1) 303#define OMAP24XX_ST_WDT1_SHIFT 4
304#define OMAP24XX_ST_WDT1_MASK (1 << 4)
305#define OMAP24XX_ST_MPU_WDT_SHIFT 3
306#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
307#define OMAP24XX_ST_32KSYNC_SHIFT 1
308#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
283 309
284/* CM_AUTOIDLE_WKUP */ 310/* CM_AUTOIDLE_WKUP */
285#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) 311#define OMAP24XX_AUTO_OMAPCTRL (1 << 5)
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 219f5c8d9659..6f3f5a36aae6 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -183,31 +183,58 @@
183#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 183#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
184 184
185/* CM_IDLEST1_CORE specific bits */ 185/* CM_IDLEST1_CORE specific bits */
186#define OMAP3430_ST_ICR (1 << 29) 186#define OMAP3430ES2_ST_MMC3_SHIFT 30
187#define OMAP3430_ST_AES2 (1 << 28) 187#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
188#define OMAP3430_ST_SHA12 (1 << 27) 188#define OMAP3430_ST_ICR_SHIFT 29
189#define OMAP3430_ST_DES2 (1 << 26) 189#define OMAP3430_ST_ICR_MASK (1 << 29)
190#define OMAP3430_ST_MSPRO (1 << 23) 190#define OMAP3430_ST_AES2_SHIFT 28
191#define OMAP3430_ST_HDQ (1 << 22) 191#define OMAP3430_ST_AES2_MASK (1 << 28)
192#define OMAP3430ES1_ST_FAC (1 << 8) 192#define OMAP3430_ST_SHA12_SHIFT 27
193#define OMAP3430ES1_ST_MAILBOXES (1 << 7) 193#define OMAP3430_ST_SHA12_MASK (1 << 27)
194#define OMAP3430_ST_OMAPCTRL (1 << 6) 194#define OMAP3430_ST_DES2_SHIFT 26
195#define OMAP3430_ST_SDMA (1 << 2) 195#define OMAP3430_ST_DES2_MASK (1 << 26)
196#define OMAP3430_ST_SDRC (1 << 1) 196#define OMAP3430_ST_MSPRO_SHIFT 23
197#define OMAP3430_ST_SSI (1 << 0) 197#define OMAP3430_ST_MSPRO_MASK (1 << 23)
198#define OMAP3430_ST_HDQ_SHIFT 22
199#define OMAP3430_ST_HDQ_MASK (1 << 22)
200#define OMAP3430ES1_ST_FAC_SHIFT 8
201#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
202#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
203#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
204#define OMAP3430_ST_MAILBOXES_SHIFT 7
205#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
206#define OMAP3430_ST_OMAPCTRL_SHIFT 6
207#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
208#define OMAP3430_ST_SDMA_SHIFT 2
209#define OMAP3430_ST_SDMA_MASK (1 << 2)
210#define OMAP3430_ST_SDRC_SHIFT 1
211#define OMAP3430_ST_SDRC_MASK (1 << 1)
212#define OMAP3430_ST_SSI_STDBY_SHIFT 0
213#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
198 214
199/* CM_IDLEST2_CORE */ 215/* CM_IDLEST2_CORE */
200#define OMAP3430_ST_PKA (1 << 4) 216#define OMAP3430_ST_PKA_SHIFT 4
201#define OMAP3430_ST_AES1 (1 << 3) 217#define OMAP3430_ST_PKA_MASK (1 << 4)
202#define OMAP3430_ST_RNG (1 << 2) 218#define OMAP3430_ST_AES1_SHIFT 3
203#define OMAP3430_ST_SHA11 (1 << 1) 219#define OMAP3430_ST_AES1_MASK (1 << 3)
204#define OMAP3430_ST_DES1 (1 << 0) 220#define OMAP3430_ST_RNG_SHIFT 2
221#define OMAP3430_ST_RNG_MASK (1 << 2)
222#define OMAP3430_ST_SHA11_SHIFT 1
223#define OMAP3430_ST_SHA11_MASK (1 << 1)
224#define OMAP3430_ST_DES1_SHIFT 0
225#define OMAP3430_ST_DES1_MASK (1 << 0)
205 226
206/* CM_IDLEST3_CORE */ 227/* CM_IDLEST3_CORE */
207#define OMAP3430ES2_ST_USBTLL_SHIFT 2 228#define OMAP3430ES2_ST_USBTLL_SHIFT 2
208#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 229#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
230#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
231#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
209 232
210/* CM_AUTOIDLE1_CORE */ 233/* CM_AUTOIDLE1_CORE */
234#define OMAP3430ES2_AUTO_MMC3 (1 << 30)
235#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
236#define OMAP3430ES2_AUTO_ICR (1 << 29)
237#define OMAP3430ES2_AUTO_ICR_SHIFT 29
211#define OMAP3430_AUTO_AES2 (1 << 28) 238#define OMAP3430_AUTO_AES2 (1 << 28)
212#define OMAP3430_AUTO_AES2_SHIFT 28 239#define OMAP3430_AUTO_AES2_SHIFT 28
213#define OMAP3430_AUTO_SHA12 (1 << 27) 240#define OMAP3430_AUTO_SHA12 (1 << 27)
@@ -276,6 +303,9 @@
276#define OMAP3430_AUTO_DES1_SHIFT 0 303#define OMAP3430_AUTO_DES1_SHIFT 0
277 304
278/* CM_AUTOIDLE3_CORE */ 305/* CM_AUTOIDLE3_CORE */
306#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
307#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
308#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
279#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 309#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
280#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 310#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
281 311
@@ -332,8 +362,12 @@
332#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 362#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
333 363
334/* CM_FCLKEN_SGX */ 364/* CM_FCLKEN_SGX */
335#define OMAP3430ES2_EN_SGX_SHIFT 1 365#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
336#define OMAP3430ES2_EN_SGX_MASK (1 << 1) 366#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
367
368/* CM_ICLKEN_SGX */
369#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
370#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
337 371
338/* CM_CLKSEL_SGX */ 372/* CM_CLKSEL_SGX */
339#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 373#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
@@ -349,6 +383,7 @@
349 383
350/* CM_FCLKEN_WKUP specific bits */ 384/* CM_FCLKEN_WKUP specific bits */
351#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 385#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
386#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
352 387
353/* CM_ICLKEN_WKUP specific bits */ 388/* CM_ICLKEN_WKUP specific bits */
354#define OMAP3430_EN_WDT1 (1 << 4) 389#define OMAP3430_EN_WDT1 (1 << 4)
@@ -357,11 +392,18 @@
357#define OMAP3430_EN_32KSYNC_SHIFT 2 392#define OMAP3430_EN_32KSYNC_SHIFT 2
358 393
359/* CM_IDLEST_WKUP specific bits */ 394/* CM_IDLEST_WKUP specific bits */
360#define OMAP3430_ST_WDT2 (1 << 5) 395#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
361#define OMAP3430_ST_WDT1 (1 << 4) 396#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
362#define OMAP3430_ST_32KSYNC (1 << 2) 397#define OMAP3430_ST_WDT2_SHIFT 5
398#define OMAP3430_ST_WDT2_MASK (1 << 5)
399#define OMAP3430_ST_WDT1_SHIFT 4
400#define OMAP3430_ST_WDT1_MASK (1 << 4)
401#define OMAP3430_ST_32KSYNC_SHIFT 2
402#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
363 403
364/* CM_AUTOIDLE_WKUP */ 404/* CM_AUTOIDLE_WKUP */
405#define OMAP3430ES2_AUTO_USIMOCP (1 << 9)
406#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
365#define OMAP3430_AUTO_WDT2 (1 << 5) 407#define OMAP3430_AUTO_WDT2 (1 << 5)
366#define OMAP3430_AUTO_WDT2_SHIFT 5 408#define OMAP3430_AUTO_WDT2_SHIFT 5
367#define OMAP3430_AUTO_WDT1 (1 << 4) 409#define OMAP3430_AUTO_WDT1 (1 << 4)
@@ -426,6 +468,8 @@
426#define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 468#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
427 469
428/* CM_IDLEST2_CKGEN */ 470/* CM_IDLEST2_CKGEN */
471#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
472#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
429#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 473#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
430#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 474#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
431#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 475#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
@@ -449,8 +493,12 @@
449#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 493#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
450#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 494#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
451#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 495#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
452#define OMAP3430_SOURCE_54M (1 << 5) 496#define OMAP3430_SOURCE_96M_SHIFT 6
453#define OMAP3430_SOURCE_48M (1 << 3) 497#define OMAP3430_SOURCE_96M_MASK (1 << 6)
498#define OMAP3430_SOURCE_54M_SHIFT 5
499#define OMAP3430_SOURCE_54M_MASK (1 << 5)
500#define OMAP3430_SOURCE_48M_SHIFT 3
501#define OMAP3430_SOURCE_48M_MASK (1 << 3)
454 502
455/* CM_CLKSEL2_PLL */ 503/* CM_CLKSEL2_PLL */
456#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 504#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
@@ -493,7 +541,12 @@
493#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 541#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
494 542
495/* CM_IDLEST_DSS */ 543/* CM_IDLEST_DSS */
496#define OMAP3430_ST_DSS (1 << 0) 544#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
545#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
546#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
547#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
548#define OMAP3430ES1_ST_DSS_SHIFT 0
549#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
497 550
498/* CM_AUTOIDLE_DSS */ 551/* CM_AUTOIDLE_DSS */
499#define OMAP3430_AUTO_DSS (1 << 0) 552#define OMAP3430_AUTO_DSS (1 << 0)
@@ -516,6 +569,8 @@
516#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 569#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
517 570
518/* CM_FCLKEN_CAM specific bits */ 571/* CM_FCLKEN_CAM specific bits */
572#define OMAP3430_EN_CSI2 (1 << 1)
573#define OMAP3430_EN_CSI2_SHIFT 1
519 574
520/* CM_ICLKEN_CAM specific bits */ 575/* CM_ICLKEN_CAM specific bits */
521 576
@@ -545,10 +600,14 @@
545/* CM_ICLKEN_PER specific bits */ 600/* CM_ICLKEN_PER specific bits */
546 601
547/* CM_IDLEST_PER */ 602/* CM_IDLEST_PER */
548#define OMAP3430_ST_WDT3 (1 << 12) 603#define OMAP3430_ST_WDT3_SHIFT 12
549#define OMAP3430_ST_MCBSP4 (1 << 2) 604#define OMAP3430_ST_WDT3_MASK (1 << 12)
550#define OMAP3430_ST_MCBSP3 (1 << 1) 605#define OMAP3430_ST_MCBSP4_SHIFT 2
551#define OMAP3430_ST_MCBSP2 (1 << 0) 606#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
607#define OMAP3430_ST_MCBSP3_SHIFT 1
608#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
609#define OMAP3430_ST_MCBSP2_SHIFT 0
610#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
552 611
553/* CM_AUTOIDLE_PER */ 612/* CM_AUTOIDLE_PER */
554#define OMAP3430_AUTO_GPIO6 (1 << 17) 613#define OMAP3430_AUTO_GPIO6 (1 << 17)
@@ -676,6 +735,10 @@
676#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 735#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
677 736
678/* CM_IDLEST_USBHOST */ 737/* CM_IDLEST_USBHOST */
738#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
739#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
740#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
741#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
679 742
680/* CM_AUTOIDLE_USBHOST */ 743/* CM_AUTOIDLE_USBHOST */
681#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 744#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index ce03fa750775..8075f5868c38 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -348,11 +348,12 @@ static void __init omap_hsmmc_reset(void)
348 } 348 }
349 349
350 dummy_pdev.id = i; 350 dummy_pdev.id = i;
351 iclk = clk_get(dev, "mmchs_ick"); 351 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
352 iclk = clk_get(dev, "ick");
352 if (iclk && clk_enable(iclk)) 353 if (iclk && clk_enable(iclk))
353 iclk = NULL; 354 iclk = NULL;
354 355
355 fclk = clk_get(dev, "mmchs_fck"); 356 fclk = clk_get(dev, "fck");
356 if (fclk && clk_enable(fclk)) 357 if (fclk && clk_enable(fclk))
357 fclk = NULL; 358 fclk = NULL;
358 359
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index b52a02fc7cd6..34b5914e0f8b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -217,8 +217,13 @@ void __init omap2_check_revision(void)
217 omap_chip.oc = CHIP_IS_OMAP3430; 217 omap_chip.oc = CHIP_IS_OMAP3430;
218 if (omap_rev() == OMAP3430_REV_ES1_0) 218 if (omap_rev() == OMAP3430_REV_ES1_0)
219 omap_chip.oc |= CHIP_IS_OMAP3430ES1; 219 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
220 else if (omap_rev() > OMAP3430_REV_ES1_0) 220 else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
221 omap_rev() <= OMAP3430_REV_ES2_1)
221 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 222 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
223 else if (omap_rev() == OMAP3430_REV_ES3_0)
224 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
225 else if (omap_rev() == OMAP3430_REV_ES3_1)
226 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
222 } else { 227 } else {
223 pr_err("Uninitialized omap_chip, please fix!\n"); 228 pr_err("Uninitialized omap_chip, please fix!\n");
224 } 229 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5ea64f926ed5..916fcd3a2328 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,8 +27,8 @@
27#include <mach/mux.h> 27#include <mach/mux.h>
28#include <mach/omapfb.h> 28#include <mach/omapfb.h>
29#include <mach/sram.h> 29#include <mach/sram.h>
30 30#include <mach/sdrc.h>
31#include "memory.h" 31#include <mach/gpmc.h>
32 32
33#include "clock.h" 33#include "clock.h"
34 34
@@ -195,12 +195,12 @@ void __init omap2_map_common_io(void)
195 omapfb_reserve_sdram(); 195 omapfb_reserve_sdram();
196} 196}
197 197
198void __init omap2_init_common_hw(void) 198void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
199{ 199{
200 omap2_mux_init(); 200 omap2_mux_init();
201 pwrdm_init(powerdomains_omap); 201 pwrdm_init(powerdomains_omap);
202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
203 omap2_clk_init(); 203 omap2_clk_init();
204 omap2_init_memory(); 204 omap2_sdrc_init(sp);
205 gpmc_init(); 205 gpmc_init();
206} 206}
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a9e631fc1134..a5c0f0435cd6 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -24,8 +24,6 @@
24#include <mach/cpu.h> 24#include <mach/cpu.h>
25#include <mach/mcbsp.h> 25#include <mach/mcbsp.h>
26 26
27const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
28
29static void omap2_mcbsp2_mux_setup(void) 27static void omap2_mcbsp2_mux_setup(void)
30{ 28{
31 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); 29 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
@@ -57,8 +55,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
57 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 55 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
58 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 56 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
59 .ops = &omap2_mcbsp_ops, 57 .ops = &omap2_mcbsp_ops,
60 .clk_names = clk_names,
61 .num_clks = 2,
62 }, 58 },
63 { 59 {
64 .phys_base = OMAP24XX_MCBSP2_BASE, 60 .phys_base = OMAP24XX_MCBSP2_BASE,
@@ -67,8 +63,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
67 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 63 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
68 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 64 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
69 .ops = &omap2_mcbsp_ops, 65 .ops = &omap2_mcbsp_ops,
70 .clk_names = clk_names,
71 .num_clks = 2,
72 }, 66 },
73}; 67};
74#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) 68#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -86,8 +80,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
86 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 80 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
87 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 81 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
88 .ops = &omap2_mcbsp_ops, 82 .ops = &omap2_mcbsp_ops,
89 .clk_names = clk_names,
90 .num_clks = 2,
91 }, 83 },
92 { 84 {
93 .phys_base = OMAP24XX_MCBSP2_BASE, 85 .phys_base = OMAP24XX_MCBSP2_BASE,
@@ -96,8 +88,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
96 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 88 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
97 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 89 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
98 .ops = &omap2_mcbsp_ops, 90 .ops = &omap2_mcbsp_ops,
99 .clk_names = clk_names,
100 .num_clks = 2,
101 }, 91 },
102 { 92 {
103 .phys_base = OMAP2430_MCBSP3_BASE, 93 .phys_base = OMAP2430_MCBSP3_BASE,
@@ -106,8 +96,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
106 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 96 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
107 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 97 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
108 .ops = &omap2_mcbsp_ops, 98 .ops = &omap2_mcbsp_ops,
109 .clk_names = clk_names,
110 .num_clks = 2,
111 }, 99 },
112 { 100 {
113 .phys_base = OMAP2430_MCBSP4_BASE, 101 .phys_base = OMAP2430_MCBSP4_BASE,
@@ -116,8 +104,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
116 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 104 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
117 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 105 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
118 .ops = &omap2_mcbsp_ops, 106 .ops = &omap2_mcbsp_ops,
119 .clk_names = clk_names,
120 .num_clks = 2,
121 }, 107 },
122 { 108 {
123 .phys_base = OMAP2430_MCBSP5_BASE, 109 .phys_base = OMAP2430_MCBSP5_BASE,
@@ -126,8 +112,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
126 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 112 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
127 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 113 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
128 .ops = &omap2_mcbsp_ops, 114 .ops = &omap2_mcbsp_ops,
129 .clk_names = clk_names,
130 .num_clks = 2,
131 }, 115 },
132}; 116};
133#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) 117#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -145,8 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
145 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 129 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
146 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 130 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
147 .ops = &omap2_mcbsp_ops, 131 .ops = &omap2_mcbsp_ops,
148 .clk_names = clk_names,
149 .num_clks = 2,
150 }, 132 },
151 { 133 {
152 .phys_base = OMAP34XX_MCBSP2_BASE, 134 .phys_base = OMAP34XX_MCBSP2_BASE,
@@ -155,8 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
155 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 137 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
156 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 138 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
157 .ops = &omap2_mcbsp_ops, 139 .ops = &omap2_mcbsp_ops,
158 .clk_names = clk_names,
159 .num_clks = 2,
160 }, 140 },
161 { 141 {
162 .phys_base = OMAP34XX_MCBSP3_BASE, 142 .phys_base = OMAP34XX_MCBSP3_BASE,
@@ -165,8 +145,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
165 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 145 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
166 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 146 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
167 .ops = &omap2_mcbsp_ops, 147 .ops = &omap2_mcbsp_ops,
168 .clk_names = clk_names,
169 .num_clks = 2,
170 }, 148 },
171 { 149 {
172 .phys_base = OMAP34XX_MCBSP4_BASE, 150 .phys_base = OMAP34XX_MCBSP4_BASE,
@@ -175,8 +153,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
175 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 153 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
176 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 154 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
177 .ops = &omap2_mcbsp_ops, 155 .ops = &omap2_mcbsp_ops,
178 .clk_names = clk_names,
179 .num_clks = 2,
180 }, 156 },
181 { 157 {
182 .phys_base = OMAP34XX_MCBSP5_BASE, 158 .phys_base = OMAP34XX_MCBSP5_BASE,
@@ -185,8 +161,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
185 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 161 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
186 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 162 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
187 .ops = &omap2_mcbsp_ops, 163 .ops = &omap2_mcbsp_ops,
188 .clk_names = clk_names,
189 .num_clks = 2,
190 }, 164 },
191}; 165};
192#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 166#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
deleted file mode 100644
index bb3db80a7c46..000000000000
--- a/arch/arm/mach-omap2/memory.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/memory.h
3 *
4 * Interface for memory timing related functions for OMAP24XX
5 *
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
18#define ARCH_ARM_MACH_OMAP2_MEMORY_H
19
20/* Memory timings */
21#define M_DDR 1
22#define M_LOCK_CTRL (1 << 2)
23#define M_UNLOCK 0
24#define M_LOCK 1
25
26struct memory_timings {
27 u32 m_type; /* ddr = 1, sdr = 0 */
28 u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
29 u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
30 u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
31 u32 base_cs; /* base chip select to use for calculations */
32};
33
34extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode);
35extern u32 omap2_memory_get_slow_dll_ctrl(void);
36extern u32 omap2_memory_get_fast_dll_ctrl(void);
37extern u32 omap2_memory_get_type(void);
38u32 omap2_dll_force_needed(void);
39u32 omap2_reprogram_sdrc(u32 level, u32 force);
40void __init omap2_init_memory(void);
41void __init gpmc_init(void);
42
43#endif
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 55361c16c9d9..ea8ceaed09cb 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = {
103 .valid = suspend_valid_only_mem, 103 .valid = suspend_valid_only_mem,
104}; 104};
105 105
106int __init omap2_pm_init(void) 106static int __init omap2_pm_init(void)
107{ 107{
108 return 0; 108 return 0;
109} 109}
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 1e151faebbd3..691470ea4c6a 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,13 +171,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
171 &iva2_pwrdm, 171 &iva2_pwrdm,
172 &mpu_34xx_pwrdm, 172 &mpu_34xx_pwrdm,
173 &neon_pwrdm, 173 &neon_pwrdm,
174 &core_34xx_pwrdm, 174 &core_34xx_pre_es3_1_pwrdm,
175 &core_34xx_es3_1_pwrdm,
175 &cam_pwrdm, 176 &cam_pwrdm,
176 &dss_pwrdm, 177 &dss_pwrdm,
177 &per_pwrdm, 178 &per_pwrdm,
178 &emu_pwrdm, 179 &emu_pwrdm,
179 &sgx_pwrdm, 180 &sgx_pwrdm,
180 &usbhost_pwrdm, 181 &usbhost_pwrdm,
182 &dpll1_pwrdm,
183 &dpll2_pwrdm,
184 &dpll3_pwrdm,
185 &dpll4_pwrdm,
186 &dpll5_pwrdm,
181#endif 187#endif
182 188
183 NULL 189 NULL
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index f573f7108398..4dcf94b800ab 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = {
200}; 200};
201 201
202/* No wkdeps or sleepdeps for 34xx core apparently */ 202/* No wkdeps or sleepdeps for 34xx core apparently */
203static struct powerdomain core_34xx_pwrdm = { 203static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
204 .name = "core_pwrdm", 204 .name = "core_pwrdm",
205 .prcm_offs = CORE_MOD, 205 .prcm_offs = CORE_MOD,
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
207 CHIP_IS_OMAP3430ES2 |
208 CHIP_IS_OMAP3430ES3_0),
209 .pwrsts = PWRSTS_OFF_RET_ON,
210 .dep_bit = OMAP3430_EN_CORE_SHIFT,
211 .banks = 2,
212 .pwrsts_mem_ret = {
213 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
214 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
215 },
216 .pwrsts_mem_on = {
217 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
218 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
219 },
220};
221
222/* No wkdeps or sleepdeps for 34xx core apparently */
223static struct powerdomain core_34xx_es3_1_pwrdm = {
224 .name = "core_pwrdm",
225 .prcm_offs = CORE_MOD,
226 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
207 .pwrsts = PWRSTS_OFF_RET_ON, 227 .pwrsts = PWRSTS_OFF_RET_ON,
208 .dep_bit = OMAP3430_EN_CORE_SHIFT, 228 .dep_bit = OMAP3430_EN_CORE_SHIFT,
229 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
209 .banks = 2, 230 .banks = 2,
210 .pwrsts_mem_ret = { 231 .pwrsts_mem_ret = {
211 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 232 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
@@ -236,14 +257,19 @@ static struct powerdomain dss_pwrdm = {
236 }, 257 },
237}; 258};
238 259
260/*
261 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
262 * possible SGX powerstate, the SGX device itself does not support
263 * retention.
264 */
239static struct powerdomain sgx_pwrdm = { 265static struct powerdomain sgx_pwrdm = {
240 .name = "sgx_pwrdm", 266 .name = "sgx_pwrdm",
241 .prcm_offs = OMAP3430ES2_SGX_MOD, 267 .prcm_offs = OMAP3430ES2_SGX_MOD,
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), 268 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
243 .wkdep_srcs = gfx_sgx_wkdeps, 269 .wkdep_srcs = gfx_sgx_wkdeps,
244 .sleepdep_srcs = cam_gfx_sleepdeps, 270 .sleepdep_srcs = cam_gfx_sleepdeps,
245 /* XXX This is accurate for 3430 SGX, but what about GFX? */ 271 /* XXX This is accurate for 3430 SGX, but what about GFX? */
246 .pwrsts = PWRSTS_OFF_RET_ON, 272 .pwrsts = PWRSTS_OFF_ON,
247 .pwrsts_logic_ret = PWRDM_POWER_RET, 273 .pwrsts_logic_ret = PWRDM_POWER_RET,
248 .banks = 1, 274 .banks = 1,
249 .pwrsts_mem_ret = { 275 .pwrsts_mem_ret = {
@@ -307,11 +333,12 @@ static struct powerdomain neon_pwrdm = {
307static struct powerdomain usbhost_pwrdm = { 333static struct powerdomain usbhost_pwrdm = {
308 .name = "usbhost_pwrdm", 334 .name = "usbhost_pwrdm",
309 .prcm_offs = OMAP3430ES2_USBHOST_MOD, 335 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), 336 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
311 .wkdep_srcs = per_usbhost_wkdeps, 337 .wkdep_srcs = per_usbhost_wkdeps,
312 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 338 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
313 .pwrsts = PWRSTS_OFF_RET_ON, 339 .pwrsts = PWRSTS_OFF_RET_ON,
314 .pwrsts_logic_ret = PWRDM_POWER_RET, 340 .pwrsts_logic_ret = PWRDM_POWER_RET,
341 .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */
315 .banks = 1, 342 .banks = 1,
316 .pwrsts_mem_ret = { 343 .pwrsts_mem_ret = {
317 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 344 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
@@ -321,6 +348,37 @@ static struct powerdomain usbhost_pwrdm = {
321 }, 348 },
322}; 349};
323 350
351static struct powerdomain dpll1_pwrdm = {
352 .name = "dpll1_pwrdm",
353 .prcm_offs = MPU_MOD,
354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
355};
356
357static struct powerdomain dpll2_pwrdm = {
358 .name = "dpll2_pwrdm",
359 .prcm_offs = OMAP3430_IVA2_MOD,
360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
361};
362
363static struct powerdomain dpll3_pwrdm = {
364 .name = "dpll3_pwrdm",
365 .prcm_offs = PLL_MOD,
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
367};
368
369static struct powerdomain dpll4_pwrdm = {
370 .name = "dpll4_pwrdm",
371 .prcm_offs = PLL_MOD,
372 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
373};
374
375static struct powerdomain dpll5_pwrdm = {
376 .name = "dpll5_pwrdm",
377 .prcm_offs = PLL_MOD,
378 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
379};
380
381
324#endif /* CONFIG_ARCH_OMAP34XX */ 382#endif /* CONFIG_ARCH_OMAP34XX */
325 383
326 384
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 4a32822ff3fc..812d50ee495d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -113,33 +113,58 @@
113#define OMAP2430_EN_USBHS (1 << 6) 113#define OMAP2430_EN_USBHS (1 << 6)
114 114
115/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 115/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
116#define OMAP2420_ST_MMC (1 << 26) 116#define OMAP2420_ST_MMC_SHIFT 26
117#define OMAP24XX_ST_UART2 (1 << 22) 117#define OMAP2420_ST_MMC_MASK (1 << 26)
118#define OMAP24XX_ST_UART1 (1 << 21) 118#define OMAP24XX_ST_UART2_SHIFT 22
119#define OMAP24XX_ST_MCSPI2 (1 << 18) 119#define OMAP24XX_ST_UART2_MASK (1 << 22)
120#define OMAP24XX_ST_MCSPI1 (1 << 17) 120#define OMAP24XX_ST_UART1_SHIFT 21
121#define OMAP24XX_ST_GPT12 (1 << 14) 121#define OMAP24XX_ST_UART1_MASK (1 << 21)
122#define OMAP24XX_ST_GPT11 (1 << 13) 122#define OMAP24XX_ST_MCSPI2_SHIFT 18
123#define OMAP24XX_ST_GPT10 (1 << 12) 123#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
124#define OMAP24XX_ST_GPT9 (1 << 11) 124#define OMAP24XX_ST_MCSPI1_SHIFT 17
125#define OMAP24XX_ST_GPT8 (1 << 10) 125#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
126#define OMAP24XX_ST_GPT7 (1 << 9) 126#define OMAP24XX_ST_GPT12_SHIFT 14
127#define OMAP24XX_ST_GPT6 (1 << 8) 127#define OMAP24XX_ST_GPT12_MASK (1 << 14)
128#define OMAP24XX_ST_GPT5 (1 << 7) 128#define OMAP24XX_ST_GPT11_SHIFT 13
129#define OMAP24XX_ST_GPT4 (1 << 6) 129#define OMAP24XX_ST_GPT11_MASK (1 << 13)
130#define OMAP24XX_ST_GPT3 (1 << 5) 130#define OMAP24XX_ST_GPT10_SHIFT 12
131#define OMAP24XX_ST_GPT2 (1 << 4) 131#define OMAP24XX_ST_GPT10_MASK (1 << 12)
132#define OMAP2420_ST_VLYNQ (1 << 3) 132#define OMAP24XX_ST_GPT9_SHIFT 11
133#define OMAP24XX_ST_GPT9_MASK (1 << 11)
134#define OMAP24XX_ST_GPT8_SHIFT 10
135#define OMAP24XX_ST_GPT8_MASK (1 << 10)
136#define OMAP24XX_ST_GPT7_SHIFT 9
137#define OMAP24XX_ST_GPT7_MASK (1 << 9)
138#define OMAP24XX_ST_GPT6_SHIFT 8
139#define OMAP24XX_ST_GPT6_MASK (1 << 8)
140#define OMAP24XX_ST_GPT5_SHIFT 7
141#define OMAP24XX_ST_GPT5_MASK (1 << 7)
142#define OMAP24XX_ST_GPT4_SHIFT 6
143#define OMAP24XX_ST_GPT4_MASK (1 << 6)
144#define OMAP24XX_ST_GPT3_SHIFT 5
145#define OMAP24XX_ST_GPT3_MASK (1 << 5)
146#define OMAP24XX_ST_GPT2_SHIFT 4
147#define OMAP24XX_ST_GPT2_MASK (1 << 4)
148#define OMAP2420_ST_VLYNQ_SHIFT 3
149#define OMAP2420_ST_VLYNQ_MASK (1 << 3)
133 150
134/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 151/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
135#define OMAP2430_ST_MDM_INTC (1 << 11) 152#define OMAP2430_ST_MDM_INTC_SHIFT 11
136#define OMAP2430_ST_GPIO5 (1 << 10) 153#define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
137#define OMAP2430_ST_MCSPI3 (1 << 9) 154#define OMAP2430_ST_GPIO5_SHIFT 10
138#define OMAP2430_ST_MMCHS2 (1 << 8) 155#define OMAP2430_ST_GPIO5_MASK (1 << 10)
139#define OMAP2430_ST_MMCHS1 (1 << 7) 156#define OMAP2430_ST_MCSPI3_SHIFT 9
140#define OMAP2430_ST_USBHS (1 << 6) 157#define OMAP2430_ST_MCSPI3_MASK (1 << 9)
141#define OMAP24XX_ST_UART3 (1 << 2) 158#define OMAP2430_ST_MMCHS2_SHIFT 8
142#define OMAP24XX_ST_USB (1 << 0) 159#define OMAP2430_ST_MMCHS2_MASK (1 << 8)
160#define OMAP2430_ST_MMCHS1_SHIFT 7
161#define OMAP2430_ST_MMCHS1_MASK (1 << 7)
162#define OMAP2430_ST_USBHS_SHIFT 6
163#define OMAP2430_ST_USBHS_MASK (1 << 6)
164#define OMAP24XX_ST_UART3_SHIFT 2
165#define OMAP24XX_ST_UART3_MASK (1 << 2)
166#define OMAP24XX_ST_USB_SHIFT 0
167#define OMAP24XX_ST_USB_MASK (1 << 0)
143 168
144/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 169/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
145#define OMAP24XX_EN_GPIOS_SHIFT 2 170#define OMAP24XX_EN_GPIOS_SHIFT 2
@@ -148,11 +173,13 @@
148#define OMAP24XX_EN_GPT1 (1 << 0) 173#define OMAP24XX_EN_GPT1 (1 << 0)
149 174
150/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 175/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
151#define OMAP24XX_ST_GPIOS (1 << 2) 176#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
152#define OMAP24XX_ST_GPT1 (1 << 0) 177#define OMAP24XX_ST_GPIOS_MASK 2
178#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
179#define OMAP24XX_ST_GPT1_MASK 0
153 180
154/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 181/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
155#define OMAP2430_ST_MDM (1 << 0) 182#define OMAP2430_ST_MDM_SHIFT (1 << 0)
156 183
157 184
158/* 3430 register bits shared between CM & PRM registers */ 185/* 3430 register bits shared between CM & PRM registers */
@@ -205,24 +232,46 @@
205#define OMAP3430_EN_HSOTGUSB_SHIFT 4 232#define OMAP3430_EN_HSOTGUSB_SHIFT 4
206 233
207/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 234/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
208#define OMAP3430_ST_MMC2 (1 << 25) 235#define OMAP3430_ST_MMC2_SHIFT 25
209#define OMAP3430_ST_MMC1 (1 << 24) 236#define OMAP3430_ST_MMC2_MASK (1 << 25)
210#define OMAP3430_ST_MCSPI4 (1 << 21) 237#define OMAP3430_ST_MMC1_SHIFT 24
211#define OMAP3430_ST_MCSPI3 (1 << 20) 238#define OMAP3430_ST_MMC1_MASK (1 << 24)
212#define OMAP3430_ST_MCSPI2 (1 << 19) 239#define OMAP3430_ST_MCSPI4_SHIFT 21
213#define OMAP3430_ST_MCSPI1 (1 << 18) 240#define OMAP3430_ST_MCSPI4_MASK (1 << 21)
214#define OMAP3430_ST_I2C3 (1 << 17) 241#define OMAP3430_ST_MCSPI3_SHIFT 20
215#define OMAP3430_ST_I2C2 (1 << 16) 242#define OMAP3430_ST_MCSPI3_MASK (1 << 20)
216#define OMAP3430_ST_I2C1 (1 << 15) 243#define OMAP3430_ST_MCSPI2_SHIFT 19
217#define OMAP3430_ST_UART2 (1 << 14) 244#define OMAP3430_ST_MCSPI2_MASK (1 << 19)
218#define OMAP3430_ST_UART1 (1 << 13) 245#define OMAP3430_ST_MCSPI1_SHIFT 18
219#define OMAP3430_ST_GPT11 (1 << 12) 246#define OMAP3430_ST_MCSPI1_MASK (1 << 18)
220#define OMAP3430_ST_GPT10 (1 << 11) 247#define OMAP3430_ST_I2C3_SHIFT 17
221#define OMAP3430_ST_MCBSP5 (1 << 10) 248#define OMAP3430_ST_I2C3_MASK (1 << 17)
222#define OMAP3430_ST_MCBSP1 (1 << 9) 249#define OMAP3430_ST_I2C2_SHIFT 16
223#define OMAP3430_ST_FSHOSTUSB (1 << 5) 250#define OMAP3430_ST_I2C2_MASK (1 << 16)
224#define OMAP3430_ST_HSOTGUSB (1 << 4) 251#define OMAP3430_ST_I2C1_SHIFT 15
225#define OMAP3430_ST_D2D (1 << 3) 252#define OMAP3430_ST_I2C1_MASK (1 << 15)
253#define OMAP3430_ST_UART2_SHIFT 14
254#define OMAP3430_ST_UART2_MASK (1 << 14)
255#define OMAP3430_ST_UART1_SHIFT 13
256#define OMAP3430_ST_UART1_MASK (1 << 13)
257#define OMAP3430_ST_GPT11_SHIFT 12
258#define OMAP3430_ST_GPT11_MASK (1 << 12)
259#define OMAP3430_ST_GPT10_SHIFT 11
260#define OMAP3430_ST_GPT10_MASK (1 << 11)
261#define OMAP3430_ST_MCBSP5_SHIFT 10
262#define OMAP3430_ST_MCBSP5_MASK (1 << 10)
263#define OMAP3430_ST_MCBSP1_SHIFT 9
264#define OMAP3430_ST_MCBSP1_MASK (1 << 9)
265#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
266#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
267#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
268#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
269#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
270#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
271#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
272#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
273#define OMAP3430_ST_D2D_SHIFT 3
274#define OMAP3430_ST_D2D_MASK (1 << 3)
226 275
227/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 276/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
228#define OMAP3430_EN_GPIO1 (1 << 3) 277#define OMAP3430_EN_GPIO1 (1 << 3)
@@ -241,11 +290,16 @@
241#define OMAP3430_EN_GPT12_SHIFT 1 290#define OMAP3430_EN_GPT12_SHIFT 1
242 291
243/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 292/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
244#define OMAP3430_ST_SR2 (1 << 7) 293#define OMAP3430_ST_SR2_SHIFT 7
245#define OMAP3430_ST_SR1 (1 << 6) 294#define OMAP3430_ST_SR2_MASK (1 << 7)
246#define OMAP3430_ST_GPIO1 (1 << 3) 295#define OMAP3430_ST_SR1_SHIFT 6
247#define OMAP3430_ST_GPT12 (1 << 1) 296#define OMAP3430_ST_SR1_MASK (1 << 6)
248#define OMAP3430_ST_GPT1 (1 << 0) 297#define OMAP3430_ST_GPIO1_SHIFT 3
298#define OMAP3430_ST_GPIO1_MASK (1 << 3)
299#define OMAP3430_ST_GPT12_SHIFT 1
300#define OMAP3430_ST_GPT12_MASK (1 << 1)
301#define OMAP3430_ST_GPT1_SHIFT 0
302#define OMAP3430_ST_GPT1_MASK (1 << 0)
249 303
250/* 304/*
251 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 305 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
@@ -296,20 +350,34 @@
296#define OMAP3430_EN_MCBSP2_SHIFT 0 350#define OMAP3430_EN_MCBSP2_SHIFT 0
297 351
298/* CM_IDLEST_PER, PM_WKST_PER shared bits */ 352/* CM_IDLEST_PER, PM_WKST_PER shared bits */
299#define OMAP3430_ST_GPIO6 (1 << 17) 353#define OMAP3430_ST_GPIO6_SHIFT 17
300#define OMAP3430_ST_GPIO5 (1 << 16) 354#define OMAP3430_ST_GPIO6_MASK (1 << 17)
301#define OMAP3430_ST_GPIO4 (1 << 15) 355#define OMAP3430_ST_GPIO5_SHIFT 16
302#define OMAP3430_ST_GPIO3 (1 << 14) 356#define OMAP3430_ST_GPIO5_MASK (1 << 16)
303#define OMAP3430_ST_GPIO2 (1 << 13) 357#define OMAP3430_ST_GPIO4_SHIFT 15
304#define OMAP3430_ST_UART3 (1 << 11) 358#define OMAP3430_ST_GPIO4_MASK (1 << 15)
305#define OMAP3430_ST_GPT9 (1 << 10) 359#define OMAP3430_ST_GPIO3_SHIFT 14
306#define OMAP3430_ST_GPT8 (1 << 9) 360#define OMAP3430_ST_GPIO3_MASK (1 << 14)
307#define OMAP3430_ST_GPT7 (1 << 8) 361#define OMAP3430_ST_GPIO2_SHIFT 13
308#define OMAP3430_ST_GPT6 (1 << 7) 362#define OMAP3430_ST_GPIO2_MASK (1 << 13)
309#define OMAP3430_ST_GPT5 (1 << 6) 363#define OMAP3430_ST_UART3_SHIFT 11
310#define OMAP3430_ST_GPT4 (1 << 5) 364#define OMAP3430_ST_UART3_MASK (1 << 11)
311#define OMAP3430_ST_GPT3 (1 << 4) 365#define OMAP3430_ST_GPT9_SHIFT 10
312#define OMAP3430_ST_GPT2 (1 << 3) 366#define OMAP3430_ST_GPT9_MASK (1 << 10)
367#define OMAP3430_ST_GPT8_SHIFT 9
368#define OMAP3430_ST_GPT8_MASK (1 << 9)
369#define OMAP3430_ST_GPT7_SHIFT 8
370#define OMAP3430_ST_GPT7_MASK (1 << 8)
371#define OMAP3430_ST_GPT6_SHIFT 7
372#define OMAP3430_ST_GPT6_MASK (1 << 7)
373#define OMAP3430_ST_GPT5_SHIFT 6
374#define OMAP3430_ST_GPT5_MASK (1 << 6)
375#define OMAP3430_ST_GPT4_SHIFT 5
376#define OMAP3430_ST_GPT4_MASK (1 << 5)
377#define OMAP3430_ST_GPT3_SHIFT 4
378#define OMAP3430_ST_GPT3_MASK (1 << 4)
379#define OMAP3430_ST_GPT2_SHIFT 3
380#define OMAP3430_ST_GPT2_MASK (1 << 3)
313 381
314/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 382/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
315#define OMAP3430_EN_CORE_SHIFT 0 383#define OMAP3430_EN_CORE_SHIFT 0
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 5b5ecfe6c999..c6a7940f4287 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -366,6 +366,7 @@
366 366
367/* PM_WKEN_WKUP specific bits */ 367/* PM_WKEN_WKUP specific bits */
368#define OMAP3430_EN_IO (1 << 8) 368#define OMAP3430_EN_IO (1 << 8)
369#define OMAP3430_EN_GPIO1 (1 << 3)
369 370
370/* PM_MPUGRPSEL_WKUP specific bits */ 371/* PM_MPUGRPSEL_WKUP specific bits */
371 372
@@ -452,6 +453,14 @@
452#define OMAP3430_CMDRA0_MASK (0xff << 0) 453#define OMAP3430_CMDRA0_MASK (0xff << 0)
453 454
454/* PRM_VC_CMD_VAL_0 specific bits */ 455/* PRM_VC_CMD_VAL_0 specific bits */
456#define OMAP3430_VC_CMD_ON_SHIFT 24
457#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
458#define OMAP3430_VC_CMD_ONLP_SHIFT 16
459#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
460#define OMAP3430_VC_CMD_RET_SHIFT 8
461#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
462#define OMAP3430_VC_CMD_OFF_SHIFT 0
463#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
455 464
456/* PRM_VC_CMD_VAL_1 specific bits */ 465/* PRM_VC_CMD_VAL_1 specific bits */
457 466
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index e4dc4b17881d..826d326b8062 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -141,6 +141,19 @@
141#define PM_PWSTCTRL 0x00e0 141#define PM_PWSTCTRL 0x00e0
142#define PM_PWSTST 0x00e4 142#define PM_PWSTST 0x00e4
143 143
144/* Omap2 specific registers */
145#define OMAP24XX_PM_WKEN2 0x00a4
146#define OMAP24XX_PM_WKST2 0x00b4
147
148#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
149#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
150#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
151#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
152
153/* Omap3 specific registers */
154#define OMAP3430ES2_PM_WKEN3 0x00f0
155#define OMAP3430ES2_PM_WKST3 0x00b8
156
144#define OMAP3430_PM_MPUGRPSEL 0x00a4 157#define OMAP3430_PM_MPUGRPSEL 0x00a4
145#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL 158#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
146 159
@@ -153,16 +166,6 @@
153#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc 166#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
154 167
155 168
156/* Architecture-specific registers */
157
158#define OMAP24XX_PM_WKEN2 0x00a4
159#define OMAP24XX_PM_WKST2 0x00b4
160
161#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
162#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
163#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
164#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
165
166#ifndef __ASSEMBLER__ 169#ifndef __ASSEMBLER__
167 170
168/* Power/reset management domain register get/set */ 171/* Power/reset management domain register get/set */
@@ -228,7 +231,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
228#define OMAP_RSTTIME1_SHIFT 0 231#define OMAP_RSTTIME1_SHIFT 0
229#define OMAP_RSTTIME1_MASK (0xff << 0) 232#define OMAP_RSTTIME1_MASK (0xff << 0)
230 233
231
232/* PRM_RSTCTRL */ 234/* PRM_RSTCTRL */
233/* Named RM_RSTCTRL_WKUP on the 24xx */ 235/* Named RM_RSTCTRL_WKUP on the 24xx */
234/* 2420 calls RST_DPLL3 'RST_DPLL' */ 236/* 2420 calls RST_DPLL3 'RST_DPLL' */
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
new file mode 100644
index 000000000000..2a30060cb4b7
--- /dev/null
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -0,0 +1,93 @@
1/*
2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
3 *
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
6 *
7 * Tony Lindgren <tony@atomide.com>
8 * Paul Walmsley
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h>
21#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <mach/common.h>
27#include <mach/clock.h>
28#include <mach/sram.h>
29
30#include "prm.h"
31
32#include <mach/sdrc.h>
33#include "sdrc.h"
34
35static struct omap_sdrc_params *sdrc_init_params;
36
37void __iomem *omap2_sdrc_base;
38void __iomem *omap2_sms_base;
39
40
41/**
42 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
43 * @r: SDRC clock rate (in Hz)
44 *
45 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
46 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
47 * SDRC clock rate 'r'. These parameters control various timing
48 * delays in the SDRAM controller that are expressed in terms of the
49 * number of SDRC clock cycles to wait; hence the clock rate
50 * dependency. Note that sdrc_init_params must be sorted rate
51 * descending. Also assumes that both chip-selects use the same
52 * timing parameters. Returns a struct omap_sdrc_params * upon
53 * success, or NULL upon failure.
54 */
55struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
56{
57 struct omap_sdrc_params *sp;
58
59 sp = sdrc_init_params;
60
61 while (sp->rate != r)
62 sp++;
63
64 if (!sp->rate)
65 return NULL;
66
67 return sp;
68}
69
70
71void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
72{
73 omap2_sdrc_base = omap2_globals->sdrc;
74 omap2_sms_base = omap2_globals->sms;
75}
76
77/* turn on smart idle modes for SDRAM scheduler and controller */
78void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
79{
80 u32 l;
81
82 l = sms_read_reg(SMS_SYSCONFIG);
83 l &= ~(0x3 << 3);
84 l |= (0x2 << 3);
85 sms_write_reg(l, SMS_SYSCONFIG);
86
87 l = sdrc_read_reg(SDRC_SYSCONFIG);
88 l &= ~(0x3 << 3);
89 l |= (0x2 << 3);
90 sdrc_write_reg(l, SDRC_SYSCONFIG);
91
92 sdrc_init_params = sp;
93}
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 882c70224292..0afdad5ae9fb 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -1,13 +1,14 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/memory.c 2 * linux/arch/arm/mach-omap2/sdrc2xxx.c
3 * 3 *
4 * Memory timing related functions for OMAP24XX 4 * SDRAM timing related functions for OMAP2xxx
5 * 5 *
6 * Copyright (C) 2005 Texas Instruments Inc. 6 * Copyright (C) 2005, 2008 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com> 7 * Copyright (C) 2005, 2008 Nokia Corporation
8 * 8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com> 9 * Tony Lindgren <tony@atomide.com>
10 * Paul Walmsley
11 * Richard Woodruff <r-woodruff2@ti.com>
11 * 12 *
12 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
@@ -28,27 +29,31 @@
28#include <mach/sram.h> 29#include <mach/sram.h>
29 30
30#include "prm.h" 31#include "prm.h"
31 32#include "clock.h"
32#include "memory.h" 33#include <mach/sdrc.h>
33#include "sdrc.h" 34#include "sdrc.h"
34 35
35void __iomem *omap2_sdrc_base; 36/* Memory timing, DLL mode flags */
36void __iomem *omap2_sms_base; 37#define M_DDR 1
38#define M_LOCK_CTRL (1 << 2)
39#define M_UNLOCK 0
40#define M_LOCK 1
41
37 42
38static struct memory_timings mem_timings; 43static struct memory_timings mem_timings;
39static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; 44static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
40 45
41u32 omap2_memory_get_slow_dll_ctrl(void) 46static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
42{ 47{
43 return mem_timings.slow_dll_ctrl; 48 return mem_timings.slow_dll_ctrl;
44} 49}
45 50
46u32 omap2_memory_get_fast_dll_ctrl(void) 51static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
47{ 52{
48 return mem_timings.fast_dll_ctrl; 53 return mem_timings.fast_dll_ctrl;
49} 54}
50 55
51u32 omap2_memory_get_type(void) 56static u32 omap2xxx_sdrc_get_type(void)
52{ 57{
53 return mem_timings.m_type; 58 return mem_timings.m_type;
54} 59}
@@ -57,7 +62,7 @@ u32 omap2_memory_get_type(void)
57 * Check the DLL lock state, and return tue if running in unlock mode. 62 * Check the DLL lock state, and return tue if running in unlock mode.
58 * This is needed to compensate for the shifted DLL value in unlock mode. 63 * This is needed to compensate for the shifted DLL value in unlock mode.
59 */ 64 */
60u32 omap2_dll_force_needed(void) 65u32 omap2xxx_sdrc_dll_is_unlocked(void)
61{ 66{
62 /* dlla and dllb are a set */ 67 /* dlla and dllb are a set */
63 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); 68 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
@@ -72,8 +77,10 @@ u32 omap2_dll_force_needed(void)
72 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. 77 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
73 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or 78 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
74 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) 79 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
80 *
81 * Used by the clock framework during CORE DPLL changes
75 */ 82 */
76u32 omap2_reprogram_sdrc(u32 level, u32 force) 83u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
77{ 84{
78 u32 dll_ctrl, m_type; 85 u32 dll_ctrl, m_type;
79 u32 prev = curr_perf_level; 86 u32 prev = curr_perf_level;
@@ -82,15 +89,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
82 if ((curr_perf_level == level) && !force) 89 if ((curr_perf_level == level) && !force)
83 return prev; 90 return prev;
84 91
85 if (level == CORE_CLK_SRC_DPLL) { 92 if (level == CORE_CLK_SRC_DPLL)
86 dll_ctrl = omap2_memory_get_slow_dll_ctrl(); 93 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
87 } else if (level == CORE_CLK_SRC_DPLL_X2) { 94 else if (level == CORE_CLK_SRC_DPLL_X2)
88 dll_ctrl = omap2_memory_get_fast_dll_ctrl(); 95 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
89 } else { 96 else
90 return prev; 97 return prev;
91 }
92 98
93 m_type = omap2_memory_get_type(); 99 m_type = omap2xxx_sdrc_get_type();
94 100
95 local_irq_save(flags); 101 local_irq_save(flags);
96 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); 102 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
@@ -101,23 +107,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
101 return prev; 107 return prev;
102} 108}
103 109
104#if !defined(CONFIG_ARCH_OMAP2) 110/* Used by the clock framework during CORE DPLL changes */
105void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 111void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
106 u32 base_cs, u32 force_unlock)
107{
108}
109void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
110 u32 mem_type)
111{
112}
113#endif
114
115void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
116{ 112{
117 unsigned long dll_cnt; 113 unsigned long dll_cnt;
118 u32 fast_dll = 0; 114 u32 fast_dll = 0;
119 115
120 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ 116 /* DDR = 1, SDR = 0 */
117 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
121 118
122 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 119 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
123 * In the case of 2422, its ok to use CS1 instead of CS0. 120 * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -164,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
164 /* 90 degree phase for anything below 133Mhz + disable DLL filter */ 161 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
165 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 162 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
166} 163}
167
168void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
169{
170 omap2_sdrc_base = omap2_globals->sdrc;
171 omap2_sms_base = omap2_globals->sms;
172}
173
174/* turn on smart idle modes for SDRAM scheduler and controller */
175void __init omap2_init_memory(void)
176{
177 u32 l;
178
179 if (!cpu_is_omap2420())
180 return;
181
182 l = sms_read_reg(SMS_SYSCONFIG);
183 l &= ~(0x3 << 3);
184 l |= (0x2 << 3);
185 sms_write_reg(l, SMS_SYSCONFIG);
186
187 l = sdrc_read_reg(SDRC_SYSCONFIG);
188 l &= ~(0x3 << 3);
189 l |= (0x2 << 3);
190 sdrc_write_reg(l, SDRC_SYSCONFIG);
191}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 20:26:53 -0500