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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-11-04 11:35:03 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 06:38:39 -0500
commit897dcded6fb6565f4d1c22a55d21f135403db132 (patch)
treeda9c4028ed49a1482445131760b4fc45c6524abe /arch/arm/mach-omap2
parent548d849574847b788fe846fe21a41386063be161 (diff)
[ARM] omap: provide a NULL clock operations structure
... and use it for clocks which are ALWAYS_ENABLED. These clocks use a non-NULL enable_reg pointer for other purposes (such as selecting clock rates.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock.c4
-rw-r--r--arch/arm/mach-omap2/clock24xx.h31
-rw-r--r--arch/arm/mach-omap2/clock34xx.h85
3 files changed, 75 insertions, 45 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d3213f565d5f..fa99c0b71d3f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -271,7 +271,7 @@ int _omap2_clk_enable(struct clk *clk)
271{ 271{
272 u32 regval32; 272 u32 regval32;
273 273
274 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) 274 if (clk->flags & PARENT_CONTROLS_CLOCK)
275 return 0; 275 return 0;
276 276
277 if (clk->ops && clk->ops->enable) 277 if (clk->ops && clk->ops->enable)
@@ -301,7 +301,7 @@ void _omap2_clk_disable(struct clk *clk)
301{ 301{
302 u32 regval32; 302 u32 regval32;
303 303
304 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) 304 if (clk->flags & PARENT_CONTROLS_CLOCK)
305 return; 305 return;
306 306
307 if (clk->ops && clk->ops->disable) { 307 if (clk->ops && clk->ops->disable) {
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 2aa0b5e65608..d4869377307a 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -619,9 +619,10 @@ static struct prcm_config rate_table[] = {
619/* Base external input clocks */ 619/* Base external input clocks */
620static struct clk func_32k_ck = { 620static struct clk func_32k_ck = {
621 .name = "func_32k_ck", 621 .name = "func_32k_ck",
622 .ops = &clkops_null,
622 .rate = 32000, 623 .rate = 32000,
623 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 624 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
624 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 625 RATE_FIXED | RATE_PROPAGATES,
625 .clkdm_name = "wkup_clkdm", 626 .clkdm_name = "wkup_clkdm",
626 .recalc = &propagate_rate, 627 .recalc = &propagate_rate,
627}; 628};
@@ -639,18 +640,20 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
639/* Without modem likely 12MHz, with modem likely 13MHz */ 640/* Without modem likely 12MHz, with modem likely 13MHz */
640static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ 641static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
641 .name = "sys_ck", /* ~ ref_clk also */ 642 .name = "sys_ck", /* ~ ref_clk also */
643 .ops = &clkops_null,
642 .parent = &osc_ck, 644 .parent = &osc_ck,
643 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 645 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
644 ALWAYS_ENABLED | RATE_PROPAGATES, 646 RATE_PROPAGATES,
645 .clkdm_name = "wkup_clkdm", 647 .clkdm_name = "wkup_clkdm",
646 .recalc = &omap2_sys_clk_recalc, 648 .recalc = &omap2_sys_clk_recalc,
647}; 649};
648 650
649static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ 651static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
650 .name = "alt_ck", 652 .name = "alt_ck",
653 .ops = &clkops_null,
651 .rate = 54000000, 654 .rate = 54000000,
652 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
653 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 656 RATE_FIXED | RATE_PROPAGATES,
654 .clkdm_name = "wkup_clkdm", 657 .clkdm_name = "wkup_clkdm",
655 .recalc = &propagate_rate, 658 .recalc = &propagate_rate,
656}; 659};
@@ -679,10 +682,11 @@ static struct dpll_data dpll_dd = {
679 */ 682 */
680static struct clk dpll_ck = { 683static struct clk dpll_ck = {
681 .name = "dpll_ck", 684 .name = "dpll_ck",
685 .ops = &clkops_null,
682 .parent = &sys_ck, /* Can be func_32k also */ 686 .parent = &sys_ck, /* Can be func_32k also */
683 .dpll_data = &dpll_dd, 687 .dpll_data = &dpll_dd,
684 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 688 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
685 RATE_PROPAGATES | ALWAYS_ENABLED, 689 RATE_PROPAGATES,
686 .clkdm_name = "wkup_clkdm", 690 .clkdm_name = "wkup_clkdm",
687 .recalc = &omap2_dpllcore_recalc, 691 .recalc = &omap2_dpllcore_recalc,
688 .set_rate = &omap2_reprogram_dpllcore, 692 .set_rate = &omap2_reprogram_dpllcore,
@@ -751,9 +755,10 @@ static struct clk func_54m_ck = {
751 755
752static struct clk core_ck = { 756static struct clk core_ck = {
753 .name = "core_ck", 757 .name = "core_ck",
758 .ops = &clkops_null,
754 .parent = &dpll_ck, /* can also be 32k */ 759 .parent = &dpll_ck, /* can also be 32k */
755 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
756 ALWAYS_ENABLED | RATE_PROPAGATES, 761 RATE_PROPAGATES,
757 .clkdm_name = "wkup_clkdm", 762 .clkdm_name = "wkup_clkdm",
758 .recalc = &followparent_recalc, 763 .recalc = &followparent_recalc,
759}; 764};
@@ -837,6 +842,7 @@ static struct clk func_12m_ck = {
837/* Secure timer, only available in secure mode */ 842/* Secure timer, only available in secure mode */
838static struct clk wdt1_osc_ck = { 843static struct clk wdt1_osc_ck = {
839 .name = "ck_wdt1_osc", 844 .name = "ck_wdt1_osc",
845 .ops = &clkops_null, /* RMK: missing? */
840 .parent = &osc_ck, 846 .parent = &osc_ck,
841 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 847 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
842 .recalc = &followparent_recalc, 848 .recalc = &followparent_recalc,
@@ -996,9 +1002,10 @@ static const struct clksel mpu_clksel[] = {
996 1002
997static struct clk mpu_ck = { /* Control cpu */ 1003static struct clk mpu_ck = { /* Control cpu */
998 .name = "mpu_ck", 1004 .name = "mpu_ck",
1005 .ops = &clkops_null,
999 .parent = &core_ck, 1006 .parent = &core_ck,
1000 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1007 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1001 ALWAYS_ENABLED | DELAYED_APP | 1008 DELAYED_APP |
1002 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1009 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1003 .clkdm_name = "mpu_clkdm", 1010 .clkdm_name = "mpu_clkdm",
1004 .init = &omap2_init_clksel_parent, 1011 .init = &omap2_init_clksel_parent,
@@ -1168,9 +1175,10 @@ static const struct clksel core_l3_clksel[] = {
1168 1175
1169static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ 1176static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
1170 .name = "core_l3_ck", 1177 .name = "core_l3_ck",
1178 .ops = &clkops_null,
1171 .parent = &core_ck, 1179 .parent = &core_ck,
1172 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1180 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1173 ALWAYS_ENABLED | DELAYED_APP | 1181 DELAYED_APP |
1174 CONFIG_PARTICIPANT | RATE_PROPAGATES, 1182 CONFIG_PARTICIPANT | RATE_PROPAGATES,
1175 .clkdm_name = "core_l3_clkdm", 1183 .clkdm_name = "core_l3_clkdm",
1176 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1184 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
@@ -1231,9 +1239,10 @@ static const struct clksel l4_clksel[] = {
1231 1239
1232static struct clk l4_ck = { /* used both as an ick and fck */ 1240static struct clk l4_ck = { /* used both as an ick and fck */
1233 .name = "l4_ck", 1241 .name = "l4_ck",
1242 .ops = &clkops_null,
1234 .parent = &core_l3_ck, 1243 .parent = &core_l3_ck,
1235 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 1244 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1236 ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, 1245 DELAYED_APP | RATE_PROPAGATES,
1237 .clkdm_name = "core_l4_clkdm", 1246 .clkdm_name = "core_l4_clkdm",
1238 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 1247 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1239 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 1248 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
@@ -2359,6 +2368,7 @@ static struct clk i2chs1_fck = {
2359 2368
2360static struct clk gpmc_fck = { 2369static struct clk gpmc_fck = {
2361 .name = "gpmc_fck", 2370 .name = "gpmc_fck",
2371 .ops = &clkops_null, /* RMK: missing? */
2362 .parent = &core_l3_ck, 2372 .parent = &core_l3_ck,
2363 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2373 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2364 ENABLE_ON_INIT, 2374 ENABLE_ON_INIT,
@@ -2368,6 +2378,7 @@ static struct clk gpmc_fck = {
2368 2378
2369static struct clk sdma_fck = { 2379static struct clk sdma_fck = {
2370 .name = "sdma_fck", 2380 .name = "sdma_fck",
2381 .ops = &clkops_null, /* RMK: missing? */
2371 .parent = &core_l3_ck, 2382 .parent = &core_l3_ck,
2372 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2383 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2373 .clkdm_name = "core_l3_clkdm", 2384 .clkdm_name = "core_l3_clkdm",
@@ -2376,6 +2387,7 @@ static struct clk sdma_fck = {
2376 2387
2377static struct clk sdma_ick = { 2388static struct clk sdma_ick = {
2378 .name = "sdma_ick", 2389 .name = "sdma_ick",
2390 .ops = &clkops_null, /* RMK: missing? */
2379 .parent = &l4_ck, 2391 .parent = &l4_ck,
2380 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 2392 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
2381 .clkdm_name = "core_l3_clkdm", 2393 .clkdm_name = "core_l3_clkdm",
@@ -2621,8 +2633,9 @@ static struct clk mmchsdb2_fck = {
2621 */ 2633 */
2622static struct clk virt_prcm_set = { 2634static struct clk virt_prcm_set = {
2623 .name = "virt_prcm_set", 2635 .name = "virt_prcm_set",
2636 .ops = &clkops_null,
2624 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 2637 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
2625 ALWAYS_ENABLED | DELAYED_APP, 2638 DELAYED_APP,
2626 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ 2639 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
2627 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ 2640 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
2628 .set_rate = &omap2_select_table_rate, 2641 .set_rate = &omap2_select_table_rate,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 8b188fb9beab..b56fd2897626 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -55,66 +55,66 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk);
55/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 55/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
56static struct clk omap_32k_fck = { 56static struct clk omap_32k_fck = {
57 .name = "omap_32k_fck", 57 .name = "omap_32k_fck",
58 .ops = &clkops_null,
58 .rate = 32768, 59 .rate = 32768,
59 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 60 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
60 ALWAYS_ENABLED,
61 .recalc = &propagate_rate, 61 .recalc = &propagate_rate,
62}; 62};
63 63
64static struct clk secure_32k_fck = { 64static struct clk secure_32k_fck = {
65 .name = "secure_32k_fck", 65 .name = "secure_32k_fck",
66 .ops = &clkops_null,
66 .rate = 32768, 67 .rate = 32768,
67 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 68 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
68 ALWAYS_ENABLED,
69 .recalc = &propagate_rate, 69 .recalc = &propagate_rate,
70}; 70};
71 71
72/* Virtual source clocks for osc_sys_ck */ 72/* Virtual source clocks for osc_sys_ck */
73static struct clk virt_12m_ck = { 73static struct clk virt_12m_ck = {
74 .name = "virt_12m_ck", 74 .name = "virt_12m_ck",
75 .ops = &clkops_null,
75 .rate = 12000000, 76 .rate = 12000000,
76 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 77 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
77 ALWAYS_ENABLED,
78 .recalc = &propagate_rate, 78 .recalc = &propagate_rate,
79}; 79};
80 80
81static struct clk virt_13m_ck = { 81static struct clk virt_13m_ck = {
82 .name = "virt_13m_ck", 82 .name = "virt_13m_ck",
83 .ops = &clkops_null,
83 .rate = 13000000, 84 .rate = 13000000,
84 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 85 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
85 ALWAYS_ENABLED,
86 .recalc = &propagate_rate, 86 .recalc = &propagate_rate,
87}; 87};
88 88
89static struct clk virt_16_8m_ck = { 89static struct clk virt_16_8m_ck = {
90 .name = "virt_16_8m_ck", 90 .name = "virt_16_8m_ck",
91 .ops = &clkops_null,
91 .rate = 16800000, 92 .rate = 16800000,
92 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | 93 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES,
93 ALWAYS_ENABLED,
94 .recalc = &propagate_rate, 94 .recalc = &propagate_rate,
95}; 95};
96 96
97static struct clk virt_19_2m_ck = { 97static struct clk virt_19_2m_ck = {
98 .name = "virt_19_2m_ck", 98 .name = "virt_19_2m_ck",
99 .ops = &clkops_null,
99 .rate = 19200000, 100 .rate = 19200000,
100 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 101 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
101 ALWAYS_ENABLED,
102 .recalc = &propagate_rate, 102 .recalc = &propagate_rate,
103}; 103};
104 104
105static struct clk virt_26m_ck = { 105static struct clk virt_26m_ck = {
106 .name = "virt_26m_ck", 106 .name = "virt_26m_ck",
107 .ops = &clkops_null,
107 .rate = 26000000, 108 .rate = 26000000,
108 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 109 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
109 ALWAYS_ENABLED,
110 .recalc = &propagate_rate, 110 .recalc = &propagate_rate,
111}; 111};
112 112
113static struct clk virt_38_4m_ck = { 113static struct clk virt_38_4m_ck = {
114 .name = "virt_38_4m_ck", 114 .name = "virt_38_4m_ck",
115 .ops = &clkops_null,
115 .rate = 38400000, 116 .rate = 38400000,
116 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 117 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
117 ALWAYS_ENABLED,
118 .recalc = &propagate_rate, 118 .recalc = &propagate_rate,
119}; 119};
120 120
@@ -162,13 +162,13 @@ static const struct clksel osc_sys_clksel[] = {
162/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ 162/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
163static struct clk osc_sys_ck = { 163static struct clk osc_sys_ck = {
164 .name = "osc_sys_ck", 164 .name = "osc_sys_ck",
165 .ops = &clkops_null,
165 .init = &omap2_init_clksel_parent, 166 .init = &omap2_init_clksel_parent,
166 .clksel_reg = OMAP3430_PRM_CLKSEL, 167 .clksel_reg = OMAP3430_PRM_CLKSEL,
167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, 168 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
168 .clksel = osc_sys_clksel, 169 .clksel = osc_sys_clksel,
169 /* REVISIT: deal with autoextclkmode? */ 170 /* REVISIT: deal with autoextclkmode? */
170 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | 171 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES,
171 ALWAYS_ENABLED,
172 .recalc = &omap2_clksel_recalc, 172 .recalc = &omap2_clksel_recalc,
173}; 173};
174 174
@@ -187,25 +187,28 @@ static const struct clksel sys_clksel[] = {
187/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ 187/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
188static struct clk sys_ck = { 188static struct clk sys_ck = {
189 .name = "sys_ck", 189 .name = "sys_ck",
190 .ops = &clkops_null,
190 .parent = &osc_sys_ck, 191 .parent = &osc_sys_ck,
191 .init = &omap2_init_clksel_parent, 192 .init = &omap2_init_clksel_parent,
192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, 193 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
193 .clksel_mask = OMAP_SYSCLKDIV_MASK, 194 .clksel_mask = OMAP_SYSCLKDIV_MASK,
194 .clksel = sys_clksel, 195 .clksel = sys_clksel,
195 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 196 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
196 .recalc = &omap2_clksel_recalc, 197 .recalc = &omap2_clksel_recalc,
197}; 198};
198 199
199static struct clk sys_altclk = { 200static struct clk sys_altclk = {
200 .name = "sys_altclk", 201 .name = "sys_altclk",
201 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 202 .ops = &clkops_null,
203 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
202 .recalc = &propagate_rate, 204 .recalc = &propagate_rate,
203}; 205};
204 206
205/* Optional external clock input for some McBSPs */ 207/* Optional external clock input for some McBSPs */
206static struct clk mcbsp_clks = { 208static struct clk mcbsp_clks = {
207 .name = "mcbsp_clks", 209 .name = "mcbsp_clks",
208 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 210 .ops = &clkops_null,
211 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
209 .recalc = &propagate_rate, 212 .recalc = &propagate_rate,
210}; 213};
211 214
@@ -278,9 +281,10 @@ static struct dpll_data dpll1_dd = {
278 281
279static struct clk dpll1_ck = { 282static struct clk dpll1_ck = {
280 .name = "dpll1_ck", 283 .name = "dpll1_ck",
284 .ops = &clkops_null,
281 .parent = &sys_ck, 285 .parent = &sys_ck,
282 .dpll_data = &dpll1_dd, 286 .dpll_data = &dpll1_dd,
283 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 287 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
284 .round_rate = &omap2_dpll_round_rate, 288 .round_rate = &omap2_dpll_round_rate,
285 .recalc = &omap3_dpll_recalc, 289 .recalc = &omap3_dpll_recalc,
286}; 290};
@@ -398,9 +402,10 @@ static struct dpll_data dpll3_dd = {
398 402
399static struct clk dpll3_ck = { 403static struct clk dpll3_ck = {
400 .name = "dpll3_ck", 404 .name = "dpll3_ck",
405 .ops = &clkops_null,
401 .parent = &sys_ck, 406 .parent = &sys_ck,
402 .dpll_data = &dpll3_dd, 407 .dpll_data = &dpll3_dd,
403 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 408 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
404 .round_rate = &omap2_dpll_round_rate, 409 .round_rate = &omap2_dpll_round_rate,
405 .recalc = &omap3_dpll_recalc, 410 .recalc = &omap3_dpll_recalc,
406}; 411};
@@ -2266,9 +2271,10 @@ static struct clk gpt1_fck = {
2266 2271
2267static struct clk wkup_32k_fck = { 2272static struct clk wkup_32k_fck = {
2268 .name = "wkup_32k_fck", 2273 .name = "wkup_32k_fck",
2274 .ops = &clkops_null,
2269 .init = &omap2_init_clk_clkdm, 2275 .init = &omap2_init_clk_clkdm,
2270 .parent = &omap_32k_fck, 2276 .parent = &omap_32k_fck,
2271 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2277 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2272 .clkdm_name = "wkup_clkdm", 2278 .clkdm_name = "wkup_clkdm",
2273 .recalc = &followparent_recalc, 2279 .recalc = &followparent_recalc,
2274}; 2280};
@@ -2295,8 +2301,9 @@ static struct clk wdt2_fck = {
2295 2301
2296static struct clk wkup_l4_ick = { 2302static struct clk wkup_l4_ick = {
2297 .name = "wkup_l4_ick", 2303 .name = "wkup_l4_ick",
2304 .ops = &clkops_null,
2298 .parent = &sys_ck, 2305 .parent = &sys_ck,
2299 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2306 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2300 .clkdm_name = "wkup_clkdm", 2307 .clkdm_name = "wkup_clkdm",
2301 .recalc = &followparent_recalc, 2308 .recalc = &followparent_recalc,
2302}; 2309};
@@ -2514,9 +2521,10 @@ static struct clk gpt9_fck = {
2514 2521
2515static struct clk per_32k_alwon_fck = { 2522static struct clk per_32k_alwon_fck = {
2516 .name = "per_32k_alwon_fck", 2523 .name = "per_32k_alwon_fck",
2524 .ops = &clkops_null,
2517 .parent = &omap_32k_fck, 2525 .parent = &omap_32k_fck,
2518 .clkdm_name = "per_clkdm", 2526 .clkdm_name = "per_clkdm",
2519 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2527 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2520 .recalc = &followparent_recalc, 2528 .recalc = &followparent_recalc,
2521}; 2529};
2522 2530
@@ -2859,11 +2867,12 @@ static const struct clksel emu_src_clksel[] = {
2859 */ 2867 */
2860static struct clk emu_src_ck = { 2868static struct clk emu_src_ck = {
2861 .name = "emu_src_ck", 2869 .name = "emu_src_ck",
2870 .ops = &clkops_null,
2862 .init = &omap2_init_clksel_parent, 2871 .init = &omap2_init_clksel_parent,
2863 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2872 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2864 .clksel_mask = OMAP3430_MUX_CTRL_MASK, 2873 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2865 .clksel = emu_src_clksel, 2874 .clksel = emu_src_clksel,
2866 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2875 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2867 .clkdm_name = "emu_clkdm", 2876 .clkdm_name = "emu_clkdm",
2868 .recalc = &omap2_clksel_recalc, 2877 .recalc = &omap2_clksel_recalc,
2869}; 2878};
@@ -2883,11 +2892,12 @@ static const struct clksel pclk_emu_clksel[] = {
2883 2892
2884static struct clk pclk_fck = { 2893static struct clk pclk_fck = {
2885 .name = "pclk_fck", 2894 .name = "pclk_fck",
2895 .ops = &clkops_null,
2886 .init = &omap2_init_clksel_parent, 2896 .init = &omap2_init_clksel_parent,
2887 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2897 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2888 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, 2898 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2889 .clksel = pclk_emu_clksel, 2899 .clksel = pclk_emu_clksel,
2890 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2900 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2891 .clkdm_name = "emu_clkdm", 2901 .clkdm_name = "emu_clkdm",
2892 .recalc = &omap2_clksel_recalc, 2902 .recalc = &omap2_clksel_recalc,
2893}; 2903};
@@ -2906,11 +2916,12 @@ static const struct clksel pclkx2_emu_clksel[] = {
2906 2916
2907static struct clk pclkx2_fck = { 2917static struct clk pclkx2_fck = {
2908 .name = "pclkx2_fck", 2918 .name = "pclkx2_fck",
2919 .ops = &clkops_null,
2909 .init = &omap2_init_clksel_parent, 2920 .init = &omap2_init_clksel_parent,
2910 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2921 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2911 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, 2922 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2912 .clksel = pclkx2_emu_clksel, 2923 .clksel = pclkx2_emu_clksel,
2913 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2924 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2914 .clkdm_name = "emu_clkdm", 2925 .clkdm_name = "emu_clkdm",
2915 .recalc = &omap2_clksel_recalc, 2926 .recalc = &omap2_clksel_recalc,
2916}; 2927};
@@ -2922,22 +2933,24 @@ static const struct clksel atclk_emu_clksel[] = {
2922 2933
2923static struct clk atclk_fck = { 2934static struct clk atclk_fck = {
2924 .name = "atclk_fck", 2935 .name = "atclk_fck",
2936 .ops = &clkops_null,
2925 .init = &omap2_init_clksel_parent, 2937 .init = &omap2_init_clksel_parent,
2926 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2938 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2927 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, 2939 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2928 .clksel = atclk_emu_clksel, 2940 .clksel = atclk_emu_clksel,
2929 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2941 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2930 .clkdm_name = "emu_clkdm", 2942 .clkdm_name = "emu_clkdm",
2931 .recalc = &omap2_clksel_recalc, 2943 .recalc = &omap2_clksel_recalc,
2932}; 2944};
2933 2945
2934static struct clk traceclk_src_fck = { 2946static struct clk traceclk_src_fck = {
2935 .name = "traceclk_src_fck", 2947 .name = "traceclk_src_fck",
2948 .ops = &clkops_null,
2936 .init = &omap2_init_clksel_parent, 2949 .init = &omap2_init_clksel_parent,
2937 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2950 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2938 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, 2951 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2939 .clksel = emu_src_clksel, 2952 .clksel = emu_src_clksel,
2940 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 2953 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2941 .clkdm_name = "emu_clkdm", 2954 .clkdm_name = "emu_clkdm",
2942 .recalc = &omap2_clksel_recalc, 2955 .recalc = &omap2_clksel_recalc,
2943}; 2956};
@@ -2956,11 +2969,12 @@ static const struct clksel traceclk_clksel[] = {
2956 2969
2957static struct clk traceclk_fck = { 2970static struct clk traceclk_fck = {
2958 .name = "traceclk_fck", 2971 .name = "traceclk_fck",
2972 .ops = &clkops_null,
2959 .init = &omap2_init_clksel_parent, 2973 .init = &omap2_init_clksel_parent,
2960 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), 2974 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2961 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, 2975 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2962 .clksel = traceclk_clksel, 2976 .clksel = traceclk_clksel,
2963 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 2977 .flags = CLOCK_IN_OMAP343X,
2964 .clkdm_name = "emu_clkdm", 2978 .clkdm_name = "emu_clkdm",
2965 .recalc = &omap2_clksel_recalc, 2979 .recalc = &omap2_clksel_recalc,
2966}; 2980};
@@ -2989,6 +3003,7 @@ static struct clk sr2_fck = {
2989 3003
2990static struct clk sr_l4_ick = { 3004static struct clk sr_l4_ick = {
2991 .name = "sr_l4_ick", 3005 .name = "sr_l4_ick",
3006 .ops = &clkops_null, /* RMK: missing? */
2992 .parent = &l4_ick, 3007 .parent = &l4_ick,
2993 .flags = CLOCK_IN_OMAP343X, 3008 .flags = CLOCK_IN_OMAP343X,
2994 .clkdm_name = "core_l4_clkdm", 3009 .clkdm_name = "core_l4_clkdm",
@@ -3000,15 +3015,17 @@ static struct clk sr_l4_ick = {
3000/* XXX This clock no longer exists in 3430 TRM rev F */ 3015/* XXX This clock no longer exists in 3430 TRM rev F */
3001static struct clk gpt12_fck = { 3016static struct clk gpt12_fck = {
3002 .name = "gpt12_fck", 3017 .name = "gpt12_fck",
3018 .ops = &clkops_null,
3003 .parent = &secure_32k_fck, 3019 .parent = &secure_32k_fck,
3004 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 3020 .flags = CLOCK_IN_OMAP343X,
3005 .recalc = &followparent_recalc, 3021 .recalc = &followparent_recalc,
3006}; 3022};
3007 3023
3008static struct clk wdt1_fck = { 3024static struct clk wdt1_fck = {
3009 .name = "wdt1_fck", 3025 .name = "wdt1_fck",
3026 .ops = &clkops_null,
3010 .parent = &secure_32k_fck, 3027 .parent = &secure_32k_fck,
3011 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, 3028 .flags = CLOCK_IN_OMAP343X,
3012 .recalc = &followparent_recalc, 3029 .recalc = &followparent_recalc,
3013}; 3030};
3014 3031