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authorTony Lindgren <tony@atomide.com>2012-11-02 15:24:06 -0400
committerTony Lindgren <tony@atomide.com>2012-11-20 13:04:41 -0500
commited1c7de29f9f3d56b3ca5ef69682cc1a3d369e9d (patch)
treecd61bc6adacd14f97d12e51f43171bf0b685727f /arch/arm/mach-omap2
parentc8d35c84f5494d8d294205b598f927a11fd41f34 (diff)
ARM: OMAP2+: Move iommu2 to drivers/iommu/omap-iommu2.c
This file should not be in arch/arm. Move it to drivers/iommu to allow making most of the header local to drivers/iommu. This is needed as we are removing plat and mach includes from drivers for ARM common zImage support. Cc: Ido Yariv <ido@wizery.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Mauro Carvalho Chehab <mchehab@infradead.org> Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: linux-media@vger.kernel.org Acked-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: Joerg Roedel <joro@8bytes.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/iommu2.c362
2 files changed, 0 insertions, 364 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..d6721a7f4c3b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -184,8 +184,6 @@ obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o
184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 184obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
185mailbox_mach-objs := mailbox.o 185mailbox_mach-objs := mailbox.o
186 186
187obj-$(CONFIG_OMAP_IOMMU) += iommu2.o
188
189iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o 187iommu-$(CONFIG_OMAP_IOMMU) := omap-iommu.o
190obj-y += $(iommu-m) $(iommu-y) 188obj-y += $(iommu-m) $(iommu-y)
191 189
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
deleted file mode 100644
index e8116cf58e15..000000000000
--- a/arch/arm/mach-omap2/iommu2.c
+++ /dev/null
@@ -1,362 +0,0 @@
1/*
2 * omap iommu: omap2/3 architecture specific functions
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/err.h>
15#include <linux/device.h>
16#include <linux/jiffies.h>
17#include <linux/module.h>
18#include <linux/omap-iommu.h>
19#include <linux/slab.h>
20#include <linux/stringify.h>
21
22#include <plat/iommu.h>
23
24/*
25 * omap2 architecture specific register bit definitions
26 */
27#define IOMMU_ARCH_VERSION 0x00000011
28
29/* SYSCONF */
30#define MMU_SYS_IDLE_SHIFT 3
31#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
32#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
33#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
34#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
35
36#define MMU_SYS_SOFTRESET (1 << 1)
37#define MMU_SYS_AUTOIDLE 1
38
39/* SYSSTATUS */
40#define MMU_SYS_RESETDONE 1
41
42/* IRQSTATUS & IRQENABLE */
43#define MMU_IRQ_MULTIHITFAULT (1 << 4)
44#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
45#define MMU_IRQ_EMUMISS (1 << 2)
46#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
47#define MMU_IRQ_TLBMISS (1 << 0)
48
49#define __MMU_IRQ_FAULT \
50 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
51#define MMU_IRQ_MASK \
52 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
53#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
54#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
55
56/* MMU_CNTL */
57#define MMU_CNTL_SHIFT 1
58#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
59#define MMU_CNTL_EML_TLB (1 << 3)
60#define MMU_CNTL_TWL_EN (1 << 2)
61#define MMU_CNTL_MMU_EN (1 << 1)
62
63#define get_cam_va_mask(pgsz) \
64 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
65 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
66 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
67 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
68
69
70static void __iommu_set_twl(struct omap_iommu *obj, bool on)
71{
72 u32 l = iommu_read_reg(obj, MMU_CNTL);
73
74 if (on)
75 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
76 else
77 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
78
79 l &= ~MMU_CNTL_MASK;
80 if (on)
81 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
82 else
83 l |= (MMU_CNTL_MMU_EN);
84
85 iommu_write_reg(obj, l, MMU_CNTL);
86}
87
88
89static int omap2_iommu_enable(struct omap_iommu *obj)
90{
91 u32 l, pa;
92 unsigned long timeout;
93
94 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
95 return -EINVAL;
96
97 pa = virt_to_phys(obj->iopgd);
98 if (!IS_ALIGNED(pa, SZ_16K))
99 return -EINVAL;
100
101 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
102
103 timeout = jiffies + msecs_to_jiffies(20);
104 do {
105 l = iommu_read_reg(obj, MMU_SYSSTATUS);
106 if (l & MMU_SYS_RESETDONE)
107 break;
108 } while (!time_after(jiffies, timeout));
109
110 if (!(l & MMU_SYS_RESETDONE)) {
111 dev_err(obj->dev, "can't take mmu out of reset\n");
112 return -ENODEV;
113 }
114
115 l = iommu_read_reg(obj, MMU_REVISION);
116 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
117 (l >> 4) & 0xf, l & 0xf);
118
119 l = iommu_read_reg(obj, MMU_SYSCONFIG);
120 l &= ~MMU_SYS_IDLE_MASK;
121 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
122 iommu_write_reg(obj, l, MMU_SYSCONFIG);
123
124 iommu_write_reg(obj, pa, MMU_TTB);
125
126 __iommu_set_twl(obj, true);
127
128 return 0;
129}
130
131static void omap2_iommu_disable(struct omap_iommu *obj)
132{
133 u32 l = iommu_read_reg(obj, MMU_CNTL);
134
135 l &= ~MMU_CNTL_MASK;
136 iommu_write_reg(obj, l, MMU_CNTL);
137 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
138
139 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
140}
141
142static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
143{
144 __iommu_set_twl(obj, false);
145}
146
147static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
148{
149 u32 stat, da;
150 u32 errs = 0;
151
152 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
153 stat &= MMU_IRQ_MASK;
154 if (!stat) {
155 *ra = 0;
156 return 0;
157 }
158
159 da = iommu_read_reg(obj, MMU_FAULT_AD);
160 *ra = da;
161
162 if (stat & MMU_IRQ_TLBMISS)
163 errs |= OMAP_IOMMU_ERR_TLB_MISS;
164 if (stat & MMU_IRQ_TRANSLATIONFAULT)
165 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
166 if (stat & MMU_IRQ_EMUMISS)
167 errs |= OMAP_IOMMU_ERR_EMU_MISS;
168 if (stat & MMU_IRQ_TABLEWALKFAULT)
169 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
170 if (stat & MMU_IRQ_MULTIHITFAULT)
171 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
172 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
173
174 return errs;
175}
176
177static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
178{
179 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
180 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
181}
182
183static void omap2_tlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
184{
185 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
186 iommu_write_reg(obj, cr->ram, MMU_RAM);
187}
188
189static u32 omap2_cr_to_virt(struct cr_regs *cr)
190{
191 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
192 u32 mask = get_cam_va_mask(cr->cam & page_size);
193
194 return cr->cam & mask;
195}
196
197static struct cr_regs *omap2_alloc_cr(struct omap_iommu *obj,
198 struct iotlb_entry *e)
199{
200 struct cr_regs *cr;
201
202 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
203 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
204 e->da);
205 return ERR_PTR(-EINVAL);
206 }
207
208 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
209 if (!cr)
210 return ERR_PTR(-ENOMEM);
211
212 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
213 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
214
215 return cr;
216}
217
218static inline int omap2_cr_valid(struct cr_regs *cr)
219{
220 return cr->cam & MMU_CAM_V;
221}
222
223static u32 omap2_get_pte_attr(struct iotlb_entry *e)
224{
225 u32 attr;
226
227 attr = e->mixed << 5;
228 attr |= e->endian;
229 attr |= e->elsz >> 3;
230 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
231 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
232 return attr;
233}
234
235static ssize_t
236omap2_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, char *buf)
237{
238 char *p = buf;
239
240 /* FIXME: Need more detail analysis of cam/ram */
241 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
242 (cr->cam & MMU_CAM_P) ? 1 : 0);
243
244 return p - buf;
245}
246
247#define pr_reg(name) \
248 do { \
249 ssize_t bytes; \
250 const char *str = "%20s: %08x\n"; \
251 const int maxcol = 32; \
252 bytes = snprintf(p, maxcol, str, __stringify(name), \
253 iommu_read_reg(obj, MMU_##name)); \
254 p += bytes; \
255 len -= bytes; \
256 if (len < maxcol) \
257 goto out; \
258 } while (0)
259
260static ssize_t
261omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
262{
263 char *p = buf;
264
265 pr_reg(REVISION);
266 pr_reg(SYSCONFIG);
267 pr_reg(SYSSTATUS);
268 pr_reg(IRQSTATUS);
269 pr_reg(IRQENABLE);
270 pr_reg(WALKING_ST);
271 pr_reg(CNTL);
272 pr_reg(FAULT_AD);
273 pr_reg(TTB);
274 pr_reg(LOCK);
275 pr_reg(LD_TLB);
276 pr_reg(CAM);
277 pr_reg(RAM);
278 pr_reg(GFLUSH);
279 pr_reg(FLUSH_ENTRY);
280 pr_reg(READ_CAM);
281 pr_reg(READ_RAM);
282 pr_reg(EMU_FAULT_AD);
283out:
284 return p - buf;
285}
286
287static void omap2_iommu_save_ctx(struct omap_iommu *obj)
288{
289 int i;
290 u32 *p = obj->ctx;
291
292 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
293 p[i] = iommu_read_reg(obj, i * sizeof(u32));
294 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
295 }
296
297 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
298}
299
300static void omap2_iommu_restore_ctx(struct omap_iommu *obj)
301{
302 int i;
303 u32 *p = obj->ctx;
304
305 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
306 iommu_write_reg(obj, p[i], i * sizeof(u32));
307 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
308 }
309
310 BUG_ON(p[0] != IOMMU_ARCH_VERSION);
311}
312
313static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
314{
315 e->da = cr->cam & MMU_CAM_VATAG_MASK;
316 e->pa = cr->ram & MMU_RAM_PADDR_MASK;
317 e->valid = cr->cam & MMU_CAM_V;
318 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
319 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
320 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
321 e->mixed = cr->ram & MMU_RAM_MIXED;
322}
323
324static const struct iommu_functions omap2_iommu_ops = {
325 .version = IOMMU_ARCH_VERSION,
326
327 .enable = omap2_iommu_enable,
328 .disable = omap2_iommu_disable,
329 .set_twl = omap2_iommu_set_twl,
330 .fault_isr = omap2_iommu_fault_isr,
331
332 .tlb_read_cr = omap2_tlb_read_cr,
333 .tlb_load_cr = omap2_tlb_load_cr,
334
335 .cr_to_e = omap2_cr_to_e,
336 .cr_to_virt = omap2_cr_to_virt,
337 .alloc_cr = omap2_alloc_cr,
338 .cr_valid = omap2_cr_valid,
339 .dump_cr = omap2_dump_cr,
340
341 .get_pte_attr = omap2_get_pte_attr,
342
343 .save_ctx = omap2_iommu_save_ctx,
344 .restore_ctx = omap2_iommu_restore_ctx,
345 .dump_ctx = omap2_iommu_dump_ctx,
346};
347
348static int __init omap2_iommu_init(void)
349{
350 return omap_install_iommu_arch(&omap2_iommu_ops);
351}
352module_init(omap2_iommu_init);
353
354static void __exit omap2_iommu_exit(void)
355{
356 omap_uninstall_iommu_arch(&omap2_iommu_ops);
357}
358module_exit(omap2_iommu_exit);
359
360MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
361MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
362MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 18:15:57 -0500