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authorOlof Johansson <olof@lixom.net>2012-05-11 02:42:52 -0400
committerOlof Johansson <olof@lixom.net>2012-05-11 02:42:52 -0400
commite2e9bbeec90cb5a23cef153b54ec4307255f4e09 (patch)
treef1366f708e5ceb02e5ee4afe20e1e0aee9a42eed /arch/arm/mach-omap2
parent5056c073d1a4cfcbbf3bb224f3bc04090fe54aec (diff)
parent6c432f72b2bd75f7c427eec5558c72f62b35d4a0 (diff)
Merge tag 'omap-cleanup-devices-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup2
Changes to split plat-omap/devices.c into mach-omap1 and mach-omap2 except for the RNG driver that will be done later on. As this depends on omap-devel-hwmod-data-for-v3.5 and causes merge conflict with omap-fixes-non-critical-for-v3.5, this branch is based on merge of the two. By Tony Lindgren (7) and others via Tony Lindgren (4) and Paul Walmsley (1) * tag 'omap-cleanup-devices-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (27 commits) ARM: OMAP1: Pass dma request lines in platform data to MMC driver ARM: OMAP: Move omap_mmc_add() to mach-omap1 ARM: OMAP2: Use hwmod to initialize mmc for 2420 ARM: OMAP2+: Move omap_dsp_reserve_sdram_memblock() to mach-omap2 ARM: OMAP1: Move omap_init_uwire to mach-omap1 ARM: OMAP1: Move omap_init_audio() to keep the devices in alphabetical order ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after hwmod reset ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod database ARM: OMAP4: hwmod_data: Name the common irq for McBSP ports ARM: OMAP4: hwmod data: I2C: add flag for context restore ARM: OMAP3: hwmod_data: Rename the common irq for McBSP ports ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmod ARM: OMAP3: hwmod data: add HDQ/1-wire hwmod ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared data ARM: OMAP2+: HDQ1W: add custom reset function ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420 arm: omap3: clockdomain data: Remove superfluous commas from gfx_sgx_3xxx_wkdeps[] ARM: OMAP2+: powerdomain: Get rid off duplicate pwrdm_clkdm_state_switch() API ARM: OMAP3: clock data: add clockdomain for HDQ functional clock ARM: OMAP3+: dpll: Configure autoidle mode only if it's supported ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/clock.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c25
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c11
-rw-r--r--arch/arm/mach-omap2/clockdomain.c7
-rw-r--r--arch/arm/mach-omap2/clockdomains3xxx_data.c6
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h4
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c28
-rw-r--r--arch/arm/mach-omap2/common.c1
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/devices.c19
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c23
-rw-r--r--arch/arm/mach-omap2/dsp.c27
-rw-r--r--arch/arm/mach-omap2/hdq1w.c72
-rw-r--r--arch/arm/mach-omap2/io.c18
-rw-r--r--arch/arm/mach-omap2/msdi.c88
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c112
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c47
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c22
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c23
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c94
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h5
-rw-r--r--arch/arm/mach-omap2/powerdomain.c10
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/prcm-common.h17
-rw-r--r--arch/arm/mach-omap2/prcm.c8
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c27
-rw-r--r--arch/arm/mach-omap2/timer.c7
-rw-r--r--arch/arm/mach-omap2/wd_timer.c45
-rw-r--r--arch/arm/mach-omap2/wd_timer.h1
32 files changed, 658 insertions, 119 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7cdb9401ffa1..fa742f3c2629 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o display.o i2c.o 7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
8 8
9omap-2-3-common = irq.o sdrc.o 9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \ 10hwmod-common = omap_hwmod.o \
@@ -186,6 +186,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),)
186obj-y += dsp.o 186obj-y += dsp.o
187endif 187endif
188 188
189# OMAP2420 MSDI controller integration support ("MMC")
190obj-$(CONFIG_SOC_OMAP2420) += msdi.o
191
189# Specific board support 192# Specific board support
190obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 193obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
191obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 194obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931513f9..5c4e66542169 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
439 clk->ops->disable(clk); 439 clk->ops->disable(clk);
440 } 440 }
441 if (clk->clkdm != NULL) 441 if (clk->clkdm != NULL)
442 pwrdm_clkdm_state_switch(clk->clkdm); 442 pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
443} 443}
444#endif 444#endif
445 445
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f4a626f7c79e..4e1a3b0e8cc8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP3 clock data 2 * OMAP3 clock data
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
1640 .name = "hdq_fck", 1640 .name = "hdq_fck",
1641 .ops = &clkops_omap2_dflt_wait, 1641 .ops = &clkops_omap2_dflt_wait,
1642 .parent = &core_12m_fck, 1642 .parent = &core_12m_fck,
1643 .clkdm_name = "core_l4_clkdm",
1643 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1644 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1644 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1645 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1645 .recalc = &followparent_recalc, 1646 .recalc = &followparent_recalc,
@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
3294 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3295 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3295 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3296 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3296 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3297 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3297 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), 3298 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3298 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), 3299 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3300 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3300 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), 3301 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3301 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), 3302 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
3419 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3420 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3420 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3421 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3421 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), 3422 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3422 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), 3423 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3423 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), 3424 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3424 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), 3425 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3425 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), 3426 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
3513 struct omap_clk *c; 3514 struct omap_clk *c;
3514 u32 cpu_clkflg = 0; 3515 u32 cpu_clkflg = 0;
3515 3516
3516 /* 3517 if (cpu_is_omap3517()) {
3517 * 3505 must be tested before 3517, since 3517 returns true
3518 * for both AM3517 chips and AM3517 family chips, which
3519 * includes 3505. Unfortunately there's no obvious family
3520 * test for 3517/3505 :-(
3521 */
3522 if (cpu_is_omap3505()) {
3523 cpu_mask = RATE_IN_34XX;
3524 cpu_clkflg = CK_3505;
3525 } else if (cpu_is_omap3517()) {
3526 cpu_mask = RATE_IN_34XX;
3527 cpu_clkflg = CK_3517;
3528 } else if (cpu_is_omap3505()) {
3529 cpu_mask = RATE_IN_34XX; 3518 cpu_mask = RATE_IN_34XX;
3530 cpu_clkflg = CK_3505; 3519 cpu_clkflg = CK_AM35XX;
3531 } else if (cpu_is_omap3630()) { 3520 } else if (cpu_is_omap3630()) {
3532 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); 3521 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3533 cpu_clkflg = CK_36XX; 3522 cpu_clkflg = CK_36XX;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fa6ea65ad44b..2172f6603848 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
3355 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), 3355 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3356 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), 3356 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3357 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3357 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3358 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3359 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
3360 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
3361 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
3362 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
3363 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
3364 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
3365 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
3366 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
3367 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
3368 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
3369 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), 3358 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3370 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3359 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3371 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3360 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689e1563..8664f5a8bfb6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
840 spin_lock_irqsave(&clkdm->lock, flags); 840 spin_lock_irqsave(&clkdm->lock, flags);
841 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; 841 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
842 arch_clkdm->clkdm_allow_idle(clkdm); 842 arch_clkdm->clkdm_allow_idle(clkdm);
843 pwrdm_clkdm_state_switch(clkdm); 843 pwrdm_state_switch(clkdm->pwrdm.ptr);
844 spin_unlock_irqrestore(&clkdm->lock, flags); 844 spin_unlock_irqrestore(&clkdm->lock, flags);
845} 845}
846 846
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
924 924
925 spin_lock_irqsave(&clkdm->lock, flags); 925 spin_lock_irqsave(&clkdm->lock, flags);
926 arch_clkdm->clkdm_clk_enable(clkdm); 926 arch_clkdm->clkdm_clk_enable(clkdm);
927 pwrdm_wait_transition(clkdm->pwrdm.ptr); 927 pwrdm_state_switch(clkdm->pwrdm.ptr);
928 pwrdm_clkdm_state_switch(clkdm);
929 spin_unlock_irqrestore(&clkdm->lock, flags); 928 spin_unlock_irqrestore(&clkdm->lock, flags);
930 929
931 pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name); 930 pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
950 949
951 spin_lock_irqsave(&clkdm->lock, flags); 950 spin_lock_irqsave(&clkdm->lock, flags);
952 arch_clkdm->clkdm_clk_disable(clkdm); 951 arch_clkdm->clkdm_clk_disable(clkdm);
953 pwrdm_clkdm_state_switch(clkdm); 952 pwrdm_state_switch(clkdm->pwrdm.ptr);
954 spin_unlock_irqrestore(&clkdm->lock, flags); 953 spin_unlock_irqrestore(&clkdm->lock, flags);
955 954
956 pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name); 955 pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index b84e138d99c8..6038adb97710 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -53,9 +53,9 @@
53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE 53 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
54 */ 54 */
55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { 55static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
56 { .clkdm_name = "iva2_clkdm", }, 56 { .clkdm_name = "iva2_clkdm" },
57 { .clkdm_name = "mpu_clkdm", }, 57 { .clkdm_name = "mpu_clkdm" },
58 { .clkdm_name = "wkup_clkdm", }, 58 { .clkdm_name = "wkup_clkdm" },
59 { NULL }, 59 { NULL },
60}; 60};
61 61
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index b91275908f33..8083a8cdc55f 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -79,7 +79,7 @@
79 79
80/* CM_CLKSEL1_PLL_IVA2 */ 80/* CM_CLKSEL1_PLL_IVA2 */
81#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 81#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
82#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 82#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
83#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 83#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
84#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 84#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
85#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 85#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
@@ -124,7 +124,7 @@
124 124
125/* CM_CLKSEL1_PLL_MPU */ 125/* CM_CLKSEL1_PLL_MPU */
126#define OMAP3430_MPU_CLK_SRC_SHIFT 19 126#define OMAP3430_MPU_CLK_SRC_SHIFT 19
127#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 127#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
128#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 128#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
129#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 129#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
130#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 130#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index bd8810c3753f..8c86d294b1a3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -32,6 +32,7 @@
32#include "prcm44xx.h" 32#include "prcm44xx.h"
33#include "prm44xx.h" 33#include "prm44xx.h"
34#include "prcm_mpu44xx.h" 34#include "prcm_mpu44xx.h"
35#include "prcm-common.h"
35 36
36/* 37/*
37 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: 38 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
@@ -49,14 +50,21 @@
49#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 50#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
50#define CLKCTRL_IDLEST_DISABLED 0x3 51#define CLKCTRL_IDLEST_DISABLED 0x3
51 52
52static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 53static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
53 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 54
54 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 55/**
55 [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, 56 * omap_cm_base_init - Populates the cm partitions
56 [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, 57 *
57 [OMAP4430_SCRM_PARTITION] = 0, 58 * Populates the base addresses of the _cm_bases
58 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 59 * array used for read/write of cm module registers.
59}; 60 */
61void omap_cm_base_init(void)
62{
63 _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
64 _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
65 _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
66 _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
67}
60 68
61/* Private functions */ 69/* Private functions */
62 70
@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
106 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 114 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
107 part == OMAP4430_INVALID_PRCM_PARTITION || 115 part == OMAP4430_INVALID_PRCM_PARTITION ||
108 !_cm_bases[part]); 116 !_cm_bases[part]);
109 return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 117 return __raw_readl(_cm_bases[part] + inst + idx);
110} 118}
111 119
112/* Write into a register in a CM instance */ 120/* Write into a register in a CM instance */
@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
115 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 123 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
116 part == OMAP4430_INVALID_PRCM_PARTITION || 124 part == OMAP4430_INVALID_PRCM_PARTITION ||
117 !_cm_bases[part]); 125 !_cm_bases[part]);
118 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); 126 __raw_writel(val, _cm_bases[part] + inst + idx);
119} 127}
120 128
121/* Read-modify-write a register in CM1. Caller must lock */ 129/* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 1549c11000d3..8a6953a34fe2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
166 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), 166 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
167 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 167 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
168 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), 168 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
169 .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
169}; 170};
170 171
171void __init omap2_set_globals_443x(void) 172void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 9c255a3cb392..ec22c24f4e81 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -112,6 +112,7 @@ struct omap_globals {
112 void __iomem *prm; /* Power and Reset Management */ 112 void __iomem *prm; /* Power and Reset Management */
113 void __iomem *cm; /* Clock Management */ 113 void __iomem *cm; /* Clock Management */
114 void __iomem *cm2; 114 void __iomem *cm2;
115 void __iomem *prcm_mpu;
115}; 116};
116 117
117void omap2_set_globals_242x(void); 118void omap2_set_globals_242x(void);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e4336035c0ea..3318f67fef7a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -616,7 +616,11 @@ static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
616 616
617void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) 617void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
618{ 618{
619 char *name = "mmci-omap"; 619 struct platform_device *pdev;
620 struct omap_hwmod *oh;
621 int id = 0;
622 char *oh_name = "msdi1";
623 char *dev_name = "mmci-omap";
620 624
621 if (!mmc_data[0]) { 625 if (!mmc_data[0]) {
622 pr_err("%s fails: Incomplete platform data\n", __func__); 626 pr_err("%s fails: Incomplete platform data\n", __func__);
@@ -624,8 +628,17 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
624 } 628 }
625 629
626 omap242x_mmc_mux(mmc_data[0]); 630 omap242x_mmc_mux(mmc_data[0]);
627 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, 631
628 INT_24XX_MMC_IRQ, mmc_data[0]); 632 oh = omap_hwmod_lookup(oh_name);
633 if (!oh) {
634 pr_err("Could not look up %s\n", oh_name);
635 return;
636 }
637 pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
638 sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
639 if (IS_ERR(pdev))
640 WARN(1, "Can'd build omap_device for %s:%s.\n",
641 dev_name, oh->name);
629} 642}
630 643
631#endif 644#endif
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fc56745676fa..f0f10beeffe8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
142 142
143 ai = omap3_dpll_autoidle_read(clk); 143 ai = omap3_dpll_autoidle_read(clk);
144 144
145 omap3_dpll_deny_idle(clk); 145 if (ai)
146 omap3_dpll_deny_idle(clk);
146 147
147 _omap3_dpll_write_clken(clk, DPLL_LOCKED); 148 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
148 149
@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
186 187
187 if (ai) 188 if (ai)
188 omap3_dpll_allow_idle(clk); 189 omap3_dpll_allow_idle(clk);
189 else
190 omap3_dpll_deny_idle(clk);
191 190
192 return r; 191 return r;
193} 192}
@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
216 215
217 if (ai) 216 if (ai)
218 omap3_dpll_allow_idle(clk); 217 omap3_dpll_allow_idle(clk);
219 else
220 omap3_dpll_deny_idle(clk);
221 218
222 return 0; 219 return 0;
223} 220}
@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
519 516
520 dd = clk->dpll_data; 517 dd = clk->dpll_data;
521 518
519 if (!dd->autoidle_reg)
520 return -EINVAL;
521
522 v = __raw_readl(dd->autoidle_reg); 522 v = __raw_readl(dd->autoidle_reg);
523 v &= dd->autoidle_mask; 523 v &= dd->autoidle_mask;
524 v >>= __ffs(dd->autoidle_mask); 524 v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
545 545
546 dd = clk->dpll_data; 546 dd = clk->dpll_data;
547 547
548 if (!dd->autoidle_reg) {
549 pr_debug("clock: DPLL %s: autoidle not supported\n",
550 clk->name);
551 return;
552 }
553
548 /* 554 /*
549 * REVISIT: CORE DPLL can optionally enter low-power bypass 555 * REVISIT: CORE DPLL can optionally enter low-power bypass
550 * by writing 0x5 instead of 0x1. Add some mechanism to 556 * by writing 0x5 instead of 0x1. Add some mechanism to
@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
554 v &= ~dd->autoidle_mask; 560 v &= ~dd->autoidle_mask;
555 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); 561 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
556 __raw_writel(v, dd->autoidle_reg); 562 __raw_writel(v, dd->autoidle_reg);
563
557} 564}
558 565
559/** 566/**
@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
572 579
573 dd = clk->dpll_data; 580 dd = clk->dpll_data;
574 581
582 if (!dd->autoidle_reg) {
583 pr_debug("clock: DPLL %s: autoidle not supported\n",
584 clk->name);
585 return;
586 }
587
575 v = __raw_readl(dd->autoidle_reg); 588 v = __raw_readl(dd->autoidle_reg);
576 v &= ~dd->autoidle_mask; 589 v &= ~dd->autoidle_mask;
577 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); 590 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 3376388b317a..845309f146fe 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -28,8 +28,6 @@
28 28
29#include <plat/dsp.h> 29#include <plat/dsp.h>
30 30
31extern phys_addr_t omap_dsp_get_mempool_base(void);
32
33static struct platform_device *omap_dsp_pdev; 31static struct platform_device *omap_dsp_pdev;
34 32
35static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { 33static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
@@ -47,6 +45,31 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
47 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, 45 .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
48}; 46};
49 47
48static phys_addr_t omap_dsp_phys_mempool_base;
49
50void __init omap_dsp_reserve_sdram_memblock(void)
51{
52 phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
53 phys_addr_t paddr;
54
55 if (!size)
56 return;
57
58 paddr = arm_memblock_steal(size, SZ_1M);
59 if (!paddr) {
60 pr_err("%s: failed to reserve %llx bytes\n",
61 __func__, (unsigned long long)size);
62 return;
63 }
64
65 omap_dsp_phys_mempool_base = paddr;
66}
67
68static phys_addr_t omap_dsp_get_mempool_base(void)
69{
70 return omap_dsp_phys_mempool_base;
71}
72
50static int __init omap_dsp_init(void) 73static int __init omap_dsp_init(void)
51{ 74{
52 struct platform_device *pdev; 75 struct platform_device *pdev;
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
new file mode 100644
index 000000000000..297ebe03f09c
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -0,0 +1,72 @@
1/*
2 * IP block integration code for the HDQ1W/1-wire IP block
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
8 * Avinash.H.M <avinashhm@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 */
24
25#include <plat/omap_hwmod.h>
26#include <plat/hdq1w.h>
27
28#include "common.h"
29
30/* Maximum microseconds to wait for OMAP module to softreset */
31#define MAX_MODULE_SOFTRESET_WAIT 10000
32
33/**
34 * omap_hdq1w_reset - reset the OMAP HDQ1W module
35 * @oh: struct omap_hwmod *
36 *
37 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
38 * Software Reset" of the OMAP34xx Technical Reference Manual Revision
39 * ZR (SWPU223R) does not include the rather important fact that, for
40 * the reset to succeed, the HDQ1W module's internal clock gate must be
41 * programmed to allow the clock to propagate to the rest of the
42 * module. In this sense, it's rather similar to the I2C custom reset
43 * function. Returns 0.
44 */
45int omap_hdq1w_reset(struct omap_hwmod *oh)
46{
47 u32 v;
48 int c = 0;
49
50 /* Write to the SOFTRESET bit */
51 omap_hwmod_softreset(oh);
52
53 /* Enable the module's internal clocks */
54 v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
55 v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
56 omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
57
58 /* Poll on RESETDONE bit */
59 omap_test_timeout((omap_hwmod_read(oh,
60 oh->class->sysc->syss_offs)
61 & SYSS_RESETDONE_MASK),
62 MAX_MODULE_SOFTRESET_WAIT, c);
63
64 if (c == MAX_MODULE_SOFTRESET_WAIT)
65 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
66 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
67 else
68 pr_debug("%s: %s: softreset in %d usec\n", __func__,
69 oh->name, c);
70
71 return 0;
72}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bafa5928efdb..86a16d34662c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -333,24 +333,6 @@ static void __init omap_hwmod_init_postsetup(void)
333#endif 333#endif
334 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 334 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
335 335
336 /*
337 * Set the default postsetup state for unusual modules (like
338 * MPU WDT).
339 *
340 * The postsetup_state is not actually used until
341 * omap_hwmod_late_init(), so boards that desire full watchdog
342 * coverage of kernel initialization can reprogram the
343 * postsetup_state between the calls to
344 * omap2_init_common_infra() and omap_sdrc_init().
345 *
346 * XXX ideally we could detect whether the MPU WDT was currently
347 * enabled here and make this conditional
348 */
349 postsetup_state = _HWMOD_STATE_DISABLED;
350 omap_hwmod_for_each_by_class("wd_timer",
351 _set_hwmod_postsetup_state,
352 &postsetup_state);
353
354 omap_pm_if_early_init(); 336 omap_pm_if_early_init();
355} 337}
356 338
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
new file mode 100644
index 000000000000..ef2a6924731a
--- /dev/null
+++ b/arch/arm/mach-omap2/msdi.c
@@ -0,0 +1,88 @@
1/*
2 * MSDI IP block reset
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * XXX What about pad muxing?
22 */
23
24#include <linux/kernel.h>
25
26#include <plat/omap_hwmod.h>
27#include <plat/mmc.h>
28
29#include "common.h"
30
31/*
32 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
33 * from the IP block's base address
34 */
35#define MSDI_CON_OFFSET 0x0c
36
37/* Register bitfields in the CON register */
38#define MSDI_CON_POW_MASK BIT(11)
39#define MSDI_CON_CLKD_MASK (0x3f << 0)
40#define MSDI_CON_CLKD_SHIFT 0
41
42/* Maximum microseconds to wait for OMAP module to softreset */
43#define MAX_MODULE_SOFTRESET_WAIT 10000
44
45/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
46#define MSDI_TARGET_RESET_CLKD 0x3ff
47
48/**
49 * omap_msdi_reset - reset the MSDI IP block
50 * @oh: struct omap_hwmod *
51 *
52 * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
53 * fields set inside its CON register for a reset to complete
54 * successfully. This is not documented in the TRM. For CLKD, we use
55 * the value that results in the lowest possible clock rate, to attempt
56 * to avoid disturbing any cards.
57 */
58int omap_msdi_reset(struct omap_hwmod *oh)
59{
60 u16 v = 0;
61 int c = 0;
62
63 /* Write to the SOFTRESET bit */
64 omap_hwmod_softreset(oh);
65
66 /* Enable the MSDI core and internal clock */
67 v |= MSDI_CON_POW_MASK;
68 v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
69 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
70
71 /* Poll on RESETDONE bit */
72 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
73 & SYSS_RESETDONE_MASK),
74 MAX_MODULE_SOFTRESET_WAIT, c);
75
76 if (c == MAX_MODULE_SOFTRESET_WAIT)
77 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
78 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
79 else
80 pr_debug("%s: %s: softreset in %d usec\n", __func__,
81 oh->name, c);
82
83 /* Disable the MSDI internal clock */
84 v &= ~MSDI_CON_CLKD_MASK;
85 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
86
87 return 0;
88}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 2c087ffc6a92..a7640d1b215e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -23,6 +23,7 @@
23#include <plat/dmtimer.h> 23#include <plat/dmtimer.h>
24#include <plat/l3_2xxx.h> 24#include <plat/l3_2xxx.h>
25#include <plat/l4_2xxx.h> 25#include <plat/l4_2xxx.h>
26#include <plat/mmc.h>
26 27
27#include "omap_hwmod_common_data.h" 28#include "omap_hwmod_common_data.h"
28 29
@@ -239,6 +240,67 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
239 }, 240 },
240}; 241};
241 242
243static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
244 .rev_offs = 0x3c,
245 .sysc_offs = 0x64,
246 .syss_offs = 0x68,
247 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
248 .sysc_fields = &omap_hwmod_sysc_type1,
249};
250
251static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
252 .name = "msdi",
253 .sysc = &omap2420_msdi_sysc,
254 .reset = &omap_msdi_reset,
255};
256
257/* msdi1 */
258static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
259 { .irq = 83 },
260 { .irq = -1 }
261};
262
263static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
264 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
265 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
266 { .dma_req = -1 }
267};
268
269static struct omap_hwmod omap2420_msdi1_hwmod = {
270 .name = "msdi1",
271 .class = &omap2420_msdi_hwmod_class,
272 .mpu_irqs = omap2420_msdi1_irqs,
273 .sdma_reqs = omap2420_msdi1_sdma_reqs,
274 .main_clk = "mmc_fck",
275 .prcm = {
276 .omap2 = {
277 .prcm_reg_id = 1,
278 .module_bit = OMAP2420_EN_MMC_SHIFT,
279 .module_offs = CORE_MOD,
280 .idlest_reg_id = 1,
281 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
282 },
283 },
284 .flags = HWMOD_16BIT_REG,
285};
286
287/* HDQ1W/1-wire */
288static struct omap_hwmod omap2420_hdq1w_hwmod = {
289 .name = "hdq1w",
290 .mpu_irqs = omap2_hdq1w_mpu_irqs,
291 .main_clk = "hdq_fck",
292 .prcm = {
293 .omap2 = {
294 .module_offs = CORE_MOD,
295 .prcm_reg_id = 1,
296 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
297 .idlest_reg_id = 1,
298 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
299 },
300 },
301 .class = &omap2_hdq1w_class,
302};
303
242/* 304/*
243 * interfaces 305 * interfaces
244 */ 306 */
@@ -428,6 +490,53 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
428 .user = OCP_USER_MPU | OCP_USER_SDMA, 490 .user = OCP_USER_MPU | OCP_USER_SDMA,
429}; 491};
430 492
493static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
494 {
495 .pa_start = 0x4809c000,
496 .pa_end = 0x4809c000 + SZ_128 - 1,
497 .flags = ADDR_TYPE_RT,
498 },
499 { }
500};
501
502/* l4_core -> msdi1 */
503static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
504 .master = &omap2xxx_l4_core_hwmod,
505 .slave = &omap2420_msdi1_hwmod,
506 .clk = "mmc_ick",
507 .addr = omap2420_msdi1_addrs,
508 .user = OCP_USER_MPU | OCP_USER_SDMA,
509};
510
511/* l4_core -> hdq1w interface */
512static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
513 .master = &omap2xxx_l4_core_hwmod,
514 .slave = &omap2420_hdq1w_hwmod,
515 .clk = "hdq_ick",
516 .addr = omap2_hdq1w_addr_space,
517 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
519};
520
521
522/* l4_wkup -> 32ksync_counter */
523static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
524 {
525 .pa_start = 0x48004000,
526 .pa_end = 0x4800401f,
527 .flags = ADDR_TYPE_RT
528 },
529 { }
530};
531
532static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
533 .master = &omap2xxx_l4_wkup_hwmod,
534 .slave = &omap2xxx_counter_32k_hwmod,
535 .clk = "sync_32k_ick",
536 .addr = omap2420_counter_32k_addrs,
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
538};
539
431static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { 540static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
432 &omap2xxx_l3_main__l4_core, 541 &omap2xxx_l3_main__l4_core,
433 &omap2xxx_mpu__l3_main, 542 &omap2xxx_mpu__l3_main,
@@ -468,6 +577,9 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
468 &omap2420_l4_core__mailbox, 577 &omap2420_l4_core__mailbox,
469 &omap2420_l4_core__mcbsp1, 578 &omap2420_l4_core__mcbsp1,
470 &omap2420_l4_core__mcbsp2, 579 &omap2420_l4_core__mcbsp2,
580 &omap2420_l4_core__msdi1,
581 &omap2420_l4_core__hdq1w,
582 &omap2420_l4_wkup__counter_32k,
471 NULL, 583 NULL,
472}; 584};
473 585
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 71d9f8824f9d..4d7264981230 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -528,6 +528,23 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
528 .class = &omap2430_mmc_class, 528 .class = &omap2430_mmc_class,
529}; 529};
530 530
531/* HDQ1W/1-wire */
532static struct omap_hwmod omap2430_hdq1w_hwmod = {
533 .name = "hdq1w",
534 .mpu_irqs = omap2_hdq1w_mpu_irqs,
535 .main_clk = "hdq_fck",
536 .prcm = {
537 .omap2 = {
538 .module_offs = CORE_MOD,
539 .prcm_reg_id = 1,
540 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
541 .idlest_reg_id = 1,
542 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
543 },
544 },
545 .class = &omap2_hdq1w_class,
546};
547
531/* 548/*
532 * interfaces 549 * interfaces
533 */ 550 */
@@ -838,6 +855,34 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
838 .user = OCP_USER_MPU | OCP_USER_SDMA, 855 .user = OCP_USER_MPU | OCP_USER_SDMA,
839}; 856};
840 857
858/* l4_core -> hdq1w */
859static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
860 .master = &omap2xxx_l4_core_hwmod,
861 .slave = &omap2430_hdq1w_hwmod,
862 .clk = "hdq_ick",
863 .addr = omap2_hdq1w_addr_space,
864 .user = OCP_USER_MPU | OCP_USER_SDMA,
865 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
866};
867
868/* l4_wkup -> 32ksync_counter */
869static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
870 {
871 .pa_start = 0x49020000,
872 .pa_end = 0x4902001f,
873 .flags = ADDR_TYPE_RT
874 },
875 { }
876};
877
878static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
879 .master = &omap2xxx_l4_wkup_hwmod,
880 .slave = &omap2xxx_counter_32k_hwmod,
881 .clk = "sync_32k_ick",
882 .addr = omap2430_counter_32k_addrs,
883 .user = OCP_USER_MPU | OCP_USER_SDMA,
884};
885
841static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { 886static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
842 &omap2xxx_l3_main__l4_core, 887 &omap2xxx_l3_main__l4_core,
843 &omap2xxx_mpu__l3_main, 888 &omap2xxx_mpu__l3_main,
@@ -886,6 +931,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
886 &omap2430_l4_core__mcbsp3, 931 &omap2430_l4_core__mcbsp3,
887 &omap2430_l4_core__mcbsp4, 932 &omap2430_l4_core__mcbsp4,
888 &omap2430_l4_core__mcbsp5, 933 &omap2430_l4_core__mcbsp5,
934 &omap2430_l4_core__hdq1w,
935 &omap2430_l4_wkup__counter_32k,
889 NULL, 936 NULL,
890}; 937};
891 938
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 04637fabadd2..cbb4ef6544ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -171,3 +171,12 @@ struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
171 }, 171 },
172 { } 172 { }
173}; 173};
174
175struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
176 {
177 .pa_start = 0x480b2000,
178 .pa_end = 0x480b2fff,
179 .flags = ADDR_TYPE_RT,
180 },
181 { }
182};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index f08e442af397..102d76e9e9ea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3 2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
3 * 3 *
4 * Copyright (C) 2011 Nokia Corporation 4 * Copyright (C) 2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -12,6 +13,7 @@
12#include <plat/serial.h> 13#include <plat/serial.h>
13#include <plat/dma.h> 14#include <plat/dma.h>
14#include <plat/common.h> 15#include <plat/common.h>
16#include <plat/hdq1w.h>
15 17
16#include <mach/irqs.h> 18#include <mach/irqs.h>
17 19
@@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
302 { .irq = -1 } 304 { .irq = -1 }
303}; 305};
304 306
307struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
308 .rev_offs = 0x0,
309 .sysc_offs = 0x14,
310 .syss_offs = 0x18,
311 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
312 SYSS_HAS_RESET_STATUS),
313 .sysc_fields = &omap_hwmod_sysc_type1,
314};
315
316struct omap_hwmod_class omap2_hdq1w_class = {
317 .name = "hdq1w",
318 .sysc = &omap2_hdq1w_sysc,
319 .reset = &omap_hdq1w_reset,
320};
321
322struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
323 { .irq = 58, },
324 { .irq = -1 }
325};
326
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 45aaa07e3025..83eafd96ecaa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -89,7 +89,8 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
89struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { 89struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
90 .name = "wd_timer", 90 .name = "wd_timer",
91 .sysc = &omap2xxx_wd_timer_sysc, 91 .sysc = &omap2xxx_wd_timer_sysc,
92 .pre_shutdown = &omap2_wd_timer_disable 92 .pre_shutdown = &omap2_wd_timer_disable,
93 .reset = &omap2_wd_timer_reset,
93}; 94};
94 95
95/* 96/*
@@ -732,3 +733,23 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
732 .class = &omap2xxx_mcspi_class, 733 .class = &omap2xxx_mcspi_class,
733 .dev_attr = &omap_mcspi2_dev_attr, 734 .dev_attr = &omap_mcspi2_dev_attr,
734}; 735};
736
737
738static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
739 .name = "counter",
740};
741
742struct omap_hwmod omap2xxx_counter_32k_hwmod = {
743 .name = "counter_32k",
744 .main_clk = "func_32k_ck",
745 .prcm = {
746 .omap2 = {
747 .module_offs = WKUP_MOD,
748 .prcm_reg_id = 1,
749 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
750 .idlest_reg_id = 1,
751 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
752 },
753 },
754 .class = &omap2xxx_counter_hwmod_class,
755};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 43d288066d06..b26d3c9bca16 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -418,7 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
418static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 418static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
419 .name = "wd_timer", 419 .name = "wd_timer",
420 .sysc = &omap3xxx_wd_timer_sysc, 420 .sysc = &omap3xxx_wd_timer_sysc,
421 .pre_shutdown = &omap2_wd_timer_disable 421 .pre_shutdown = &omap2_wd_timer_disable,
422 .reset = &omap2_wd_timer_reset,
422}; 423};
423 424
424static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 425static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
@@ -1075,7 +1076,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1075 1076
1076/* mcbsp1 */ 1077/* mcbsp1 */
1077static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1078 { .name = "irq", .irq = 16 }, 1079 { .name = "common", .irq = 16 },
1079 { .name = "tx", .irq = 59 }, 1080 { .name = "tx", .irq = 59 },
1080 { .name = "rx", .irq = 60 }, 1081 { .name = "rx", .irq = 60 },
1081 { .irq = -1 } 1082 { .irq = -1 }
@@ -1100,7 +1101,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1100 1101
1101/* mcbsp2 */ 1102/* mcbsp2 */
1102static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1103static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1103 { .name = "irq", .irq = 17 }, 1104 { .name = "common", .irq = 17 },
1104 { .name = "tx", .irq = 62 }, 1105 { .name = "tx", .irq = 62 },
1105 { .name = "rx", .irq = 63 }, 1106 { .name = "rx", .irq = 63 },
1106 { .irq = -1 } 1107 { .irq = -1 }
@@ -1130,7 +1131,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1130 1131
1131/* mcbsp3 */ 1132/* mcbsp3 */
1132static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1133static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1133 { .name = "irq", .irq = 22 }, 1134 { .name = "common", .irq = 22 },
1134 { .name = "tx", .irq = 89 }, 1135 { .name = "tx", .irq = 89 },
1135 { .name = "rx", .irq = 90 }, 1136 { .name = "rx", .irq = 90 },
1136 { .irq = -1 } 1137 { .irq = -1 }
@@ -1160,7 +1161,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1160 1161
1161/* mcbsp4 */ 1162/* mcbsp4 */
1162static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1163static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1163 { .name = "irq", .irq = 23 }, 1164 { .name = "common", .irq = 23 },
1164 { .name = "tx", .irq = 54 }, 1165 { .name = "tx", .irq = 54 },
1165 { .name = "rx", .irq = 55 }, 1166 { .name = "rx", .irq = 55 },
1166 { .irq = -1 } 1167 { .irq = -1 }
@@ -1191,7 +1192,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1191 1192
1192/* mcbsp5 */ 1193/* mcbsp5 */
1193static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1194static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1194 { .name = "irq", .irq = 27 }, 1195 { .name = "common", .irq = 27 },
1195 { .name = "tx", .irq = 81 }, 1196 { .name = "tx", .irq = 81 },
1196 { .name = "rx", .irq = 82 }, 1197 { .name = "rx", .irq = 82 },
1197 { .irq = -1 } 1198 { .irq = -1 }
@@ -1980,6 +1981,56 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1980 }, 1981 },
1981}; 1982};
1982 1983
1984static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1985 .name = "hdq1w",
1986 .mpu_irqs = omap2_hdq1w_mpu_irqs,
1987 .main_clk = "hdq_fck",
1988 .prcm = {
1989 .omap2 = {
1990 .module_offs = CORE_MOD,
1991 .prcm_reg_id = 1,
1992 .module_bit = OMAP3430_EN_HDQ_SHIFT,
1993 .idlest_reg_id = 1,
1994 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1995 },
1996 },
1997 .class = &omap2_hdq1w_class,
1998};
1999
2000/*
2001 * '32K sync counter' class
2002 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2003 */
2004static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2005 .rev_offs = 0x0000,
2006 .sysc_offs = 0x0004,
2007 .sysc_flags = SYSC_HAS_SIDLEMODE,
2008 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2009 .sysc_fields = &omap_hwmod_sysc_type1,
2010};
2011
2012static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2013 .name = "counter",
2014 .sysc = &omap3xxx_counter_sysc,
2015};
2016
2017static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2018 .name = "counter_32k",
2019 .class = &omap3xxx_counter_hwmod_class,
2020 .clkdm_name = "wkup_clkdm",
2021 .flags = HWMOD_SWSUP_SIDLE,
2022 .main_clk = "wkup_32k_fck",
2023 .prcm = {
2024 .omap2 = {
2025 .module_offs = WKUP_MOD,
2026 .prcm_reg_id = 1,
2027 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2028 .idlest_reg_id = 1,
2029 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2030 },
2031 },
2032};
2033
1983/* 2034/*
1984 * interfaces 2035 * interfaces
1985 */ 2036 */
@@ -3059,6 +3110,34 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3059 .user = OCP_USER_MPU | OCP_USER_SDMA, 3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060}; 3111};
3061 3112
3113/* l4_core -> hdq1w interface */
3114static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3115 .master = &omap3xxx_l4_core_hwmod,
3116 .slave = &omap3xxx_hdq1w_hwmod,
3117 .clk = "hdq_ick",
3118 .addr = omap2_hdq1w_addr_space,
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3121};
3122
3123/* l4_wkup -> 32ksync_counter */
3124static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3125 {
3126 .pa_start = 0x48320000,
3127 .pa_end = 0x4832001f,
3128 .flags = ADDR_TYPE_RT
3129 },
3130 { }
3131};
3132
3133static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3134 .master = &omap3xxx_l4_wkup_hwmod,
3135 .slave = &omap3xxx_counter_32k_hwmod,
3136 .clk = "omap_32ksync_ick",
3137 .addr = omap3xxx_counter_32k_addrs,
3138 .user = OCP_USER_MPU | OCP_USER_SDMA,
3139};
3140
3062static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3141static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3063 &omap3xxx_l3_main__l4_core, 3142 &omap3xxx_l3_main__l4_core,
3064 &omap3xxx_l3_main__l4_per, 3143 &omap3xxx_l3_main__l4_per,
@@ -3103,6 +3182,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3103 &omap34xx_l4_core__mcspi2, 3182 &omap34xx_l4_core__mcspi2,
3104 &omap34xx_l4_core__mcspi3, 3183 &omap34xx_l4_core__mcspi3,
3105 &omap34xx_l4_core__mcspi4, 3184 &omap34xx_l4_core__mcspi4,
3185 &omap3xxx_l4_wkup__counter_32k,
3106 NULL, 3186 NULL,
3107}; 3187};
3108 3188
@@ -3151,6 +3231,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3151 &omap34xx_l4_core__sr1, 3231 &omap34xx_l4_core__sr1,
3152 &omap34xx_l4_core__sr2, 3232 &omap34xx_l4_core__sr2,
3153 &omap3xxx_l4_core__mailbox, 3233 &omap3xxx_l4_core__mailbox,
3234 &omap3xxx_l4_core__hdq1w,
3154 NULL 3235 NULL
3155}; 3236};
3156 3237
@@ -3170,6 +3251,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3170 &omap3xxx_l4_core__usb_tll_hs, 3251 &omap3xxx_l4_core__usb_tll_hs,
3171 &omap3xxx_l4_core__es3plus_mmc1, 3252 &omap3xxx_l4_core__es3plus_mmc1,
3172 &omap3xxx_l4_core__es3plus_mmc2, 3253 &omap3xxx_l4_core__es3plus_mmc2,
3254 &omap3xxx_l4_core__hdq1w,
3173 NULL 3255 NULL
3174}; 3256};
3175 3257
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 49061295475c..950454a3fa31 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1487,7 +1487,8 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1487}; 1487};
1488 1488
1489static struct omap_i2c_dev_attr i2c_dev_attr = { 1489static struct omap_i2c_dev_attr i2c_dev_attr = {
1490 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, 1490 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1491 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1491}; 1492};
1492 1493
1493/* i2c1 */ 1494/* i2c1 */
@@ -1911,7 +1912,7 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1911 1912
1912/* mcbsp1 */ 1913/* mcbsp1 */
1913static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 1914static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1914 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 1915 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1915 { .irq = -1 } 1916 { .irq = -1 }
1916}; 1917};
1917 1918
@@ -1946,7 +1947,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1946 1947
1947/* mcbsp2 */ 1948/* mcbsp2 */
1948static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 1949static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1949 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 1950 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1950 { .irq = -1 } 1951 { .irq = -1 }
1951}; 1952};
1952 1953
@@ -1981,7 +1982,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1981 1982
1982/* mcbsp3 */ 1983/* mcbsp3 */
1983static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 1984static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
1984 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 1985 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
1985 { .irq = -1 } 1986 { .irq = -1 }
1986}; 1987};
1987 1988
@@ -2016,7 +2017,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2016 2017
2017/* mcbsp4 */ 2018/* mcbsp4 */
2018static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 2019static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2019 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 2020 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2020 { .irq = -1 } 2021 { .irq = -1 }
2021}; 2022};
2022 2023
@@ -3534,6 +3535,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3534 .name = "wd_timer", 3535 .name = "wd_timer",
3535 .sysc = &omap44xx_wd_timer_sysc, 3536 .sysc = &omap44xx_wd_timer_sysc,
3536 .pre_shutdown = &omap2_wd_timer_disable, 3537 .pre_shutdown = &omap2_wd_timer_disable,
3538 .reset = &omap2_wd_timer_reset,
3537}; 3539};
3538 3540
3539/* wd_timer2 */ 3541/* wd_timer2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index 7aa9156d50ab..e7e8eeae95e5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -38,6 +38,7 @@ extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
38extern struct omap_hwmod_addr_space omap2_dma_system_addrs[]; 38extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
39extern struct omap_hwmod_addr_space omap2_mailbox_addrs[]; 39extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
40extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[]; 40extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
41extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
41 42
42/* Common IP block data across OMAP2xxx */ 43/* Common IP block data across OMAP2xxx */
43extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[]; 44extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
@@ -74,6 +75,7 @@ extern struct omap_hwmod omap2xxx_gpio3_hwmod;
74extern struct omap_hwmod omap2xxx_gpio4_hwmod; 75extern struct omap_hwmod omap2xxx_gpio4_hwmod;
75extern struct omap_hwmod omap2xxx_mcspi1_hwmod; 76extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
76extern struct omap_hwmod omap2xxx_mcspi2_hwmod; 77extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
78extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
77 79
78/* Common interface data across OMAP2xxx */ 80/* Common interface data across OMAP2xxx */
79extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core; 81extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -141,6 +143,7 @@ extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
141extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[]; 143extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
142extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[]; 144extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
143extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[]; 145extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
146extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[];
144 147
145/* OMAP hwmod classes - forward declarations */ 148/* OMAP hwmod classes - forward declarations */
146extern struct omap_hwmod_class l3_hwmod_class; 149extern struct omap_hwmod_class l3_hwmod_class;
@@ -152,6 +155,8 @@ extern struct omap_hwmod_class omap2_dss_hwmod_class;
152extern struct omap_hwmod_class omap2_dispc_hwmod_class; 155extern struct omap_hwmod_class omap2_dispc_hwmod_class;
153extern struct omap_hwmod_class omap2_rfbi_hwmod_class; 156extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
154extern struct omap_hwmod_class omap2_venc_hwmod_class; 157extern struct omap_hwmod_class omap2_venc_hwmod_class;
158extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
159extern struct omap_hwmod_class omap2_hdq1w_class;
155 160
156extern struct omap_hwmod_class omap2xxx_timer_hwmod_class; 161extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
157extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class; 162extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbeac34..96114901b932 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
981 return ret; 981 return ret;
982} 982}
983 983
984int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
985{
986 if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
987 pwrdm_wait_transition(clkdm->pwrdm.ptr);
988 return pwrdm_state_switch(clkdm->pwrdm.ptr);
989 }
990
991 return -EINVAL;
992}
993
994int pwrdm_pre_transition(void) 984int pwrdm_pre_transition(void)
995{ 985{
996 pwrdm_for_each(_pwrdm_pre_transition_cb, NULL); 986 pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a8ce4d..8f88d65c46ea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
213int pwrdm_wait_transition(struct powerdomain *pwrdm); 213int pwrdm_wait_transition(struct powerdomain *pwrdm);
214 214
215int pwrdm_state_switch(struct powerdomain *pwrdm); 215int pwrdm_state_switch(struct powerdomain *pwrdm);
216int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
217int pwrdm_pre_transition(void); 216int pwrdm_pre_transition(void);
218int pwrdm_post_transition(void); 217int pwrdm_post_transition(void);
219int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); 218int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435e3ff1..6da3ba483ad1 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
177/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 177/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
178#define OMAP24XX_ST_GPIOS_SHIFT 2 178#define OMAP24XX_ST_GPIOS_SHIFT 2
179#define OMAP24XX_ST_GPIOS_MASK (1 << 2) 179#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
180#define OMAP24XX_ST_32KSYNC_SHIFT 1
181#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
180#define OMAP24XX_ST_GPT1_SHIFT 0 182#define OMAP24XX_ST_GPT1_SHIFT 0
181#define OMAP24XX_ST_GPT1_MASK (1 << 0) 183#define OMAP24XX_ST_GPT1_MASK (1 << 0)
182 184
@@ -307,6 +309,8 @@
307#define OMAP3430_ST_SR1_MASK (1 << 6) 309#define OMAP3430_ST_SR1_MASK (1 << 6)
308#define OMAP3430_ST_GPIO1_SHIFT 3 310#define OMAP3430_ST_GPIO1_SHIFT 3
309#define OMAP3430_ST_GPIO1_MASK (1 << 3) 311#define OMAP3430_ST_GPIO1_MASK (1 << 3)
312#define OMAP3430_ST_32KSYNC_SHIFT 2
313#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
310#define OMAP3430_ST_GPT12_SHIFT 1 314#define OMAP3430_ST_GPT12_SHIFT 1
311#define OMAP3430_ST_GPT12_MASK (1 << 1) 315#define OMAP3430_ST_GPT12_MASK (1 << 1)
312#define OMAP3430_ST_GPT1_SHIFT 0 316#define OMAP3430_ST_GPT1_SHIFT 0
@@ -410,6 +414,19 @@
410extern void __iomem *prm_base; 414extern void __iomem *prm_base;
411extern void __iomem *cm_base; 415extern void __iomem *cm_base;
412extern void __iomem *cm2_base; 416extern void __iomem *cm2_base;
417extern void __iomem *prcm_mpu_base;
418
419#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
420extern void omap_prm_base_init(void);
421extern void omap_cm_base_init(void);
422#else
423static inline void omap_prm_base_init(void)
424{
425}
426static inline void omap_cm_base_init(void)
427{
428}
429#endif
413 430
414/** 431/**
415 * struct omap_prcm_irq - describes a PRCM interrupt bit 432 * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 626acfad7190..480f40a5ee42 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -42,6 +42,7 @@
42void __iomem *prm_base; 42void __iomem *prm_base;
43void __iomem *cm_base; 43void __iomem *cm_base;
44void __iomem *cm2_base; 44void __iomem *cm2_base;
45void __iomem *prcm_mpu_base;
45 46
46#define MAX_MODULE_ENABLE_WAIT 100000 47#define MAX_MODULE_ENABLE_WAIT 100000
47 48
@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
155 cm_base = omap2_globals->cm; 156 cm_base = omap2_globals->cm;
156 if (omap2_globals->cm2) 157 if (omap2_globals->cm2)
157 cm2_base = omap2_globals->cm2; 158 cm2_base = omap2_globals->cm2;
159 if (omap2_globals->prcm_mpu)
160 prcm_mpu_base = omap2_globals->prcm_mpu;
161
162 if (cpu_is_omap44xx()) {
163 omap_prm_base_init();
164 omap_cm_base_init();
165 }
158} 166}
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 9b3898a3ac9b..c12320c0ae95 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -18,20 +18,26 @@
18 18
19#include "iomap.h" 19#include "iomap.h"
20#include "common.h" 20#include "common.h"
21#include "prcm-common.h"
21#include "prm44xx.h" 22#include "prm44xx.h"
22#include "prminst44xx.h" 23#include "prminst44xx.h"
23#include "prm-regbits-44xx.h" 24#include "prm-regbits-44xx.h"
24#include "prcm44xx.h" 25#include "prcm44xx.h"
25#include "prcm_mpu44xx.h" 26#include "prcm_mpu44xx.h"
26 27
27static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { 28static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
28 [OMAP4430_INVALID_PRCM_PARTITION] = 0, 29
29 [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, 30/**
30 [OMAP4430_CM1_PARTITION] = 0, 31 * omap_prm_base_init - Populates the prm partitions
31 [OMAP4430_CM2_PARTITION] = 0, 32 *
32 [OMAP4430_SCRM_PARTITION] = 0, 33 * Populates the base addresses of the _prm_bases
33 [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, 34 * array used for read/write of prm module registers.
34}; 35 */
36void omap_prm_base_init(void)
37{
38 _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
39 _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
40}
35 41
36/* Read a register in a PRM instance */ 42/* Read a register in a PRM instance */
37u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) 43u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
39 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 45 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
40 part == OMAP4430_INVALID_PRCM_PARTITION || 46 part == OMAP4430_INVALID_PRCM_PARTITION ||
41 !_prm_bases[part]); 47 !_prm_bases[part]);
42 return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + 48 return __raw_readl(_prm_bases[part] + inst + idx);
43 idx));
44} 49}
45 50
46/* Write into a register in a PRM instance */ 51/* Write into a register in a PRM instance */
@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
49 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || 54 BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
50 part == OMAP4430_INVALID_PRCM_PARTITION || 55 part == OMAP4430_INVALID_PRCM_PARTITION ||
51 !_prm_bases[part]); 56 !_prm_bases[part]);
52 __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); 57 __raw_writel(val, _prm_bases[part] + inst + idx);
53} 58}
54 59
55/* Read-modify-write a register in PRM. Caller must lock */ 60/* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ecec873e78cd..1b7835865c83 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -178,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
178 if (IS_ERR(timer->fclk)) 178 if (IS_ERR(timer->fclk))
179 return -ENODEV; 179 return -ENODEV;
180 180
181 sprintf(name, "gpt%d_ick", gptimer_id);
182 timer->iclk = clk_get(NULL, name);
183 if (IS_ERR(timer->iclk)) {
184 clk_put(timer->fclk);
185 return -ENODEV;
186 }
187
188 omap_hwmod_enable(oh); 181 omap_hwmod_enable(oh);
189 182
190 sys_timer_reserved |= (1 << (gptimer_id - 1)); 183 sys_timer_reserved |= (1 << (gptimer_id - 1));
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 4067669d96c4..b2f1c67043a2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -14,6 +14,7 @@
14#include <plat/omap_hwmod.h> 14#include <plat/omap_hwmod.h>
15 15
16#include "wd_timer.h" 16#include "wd_timer.h"
17#include "common.h"
17 18
18/* 19/*
19 * In order to avoid any assumptions from bootloader regarding WDT 20 * In order to avoid any assumptions from bootloader regarding WDT
@@ -25,6 +26,8 @@
25#define OMAP_WDT_WPS 0x34 26#define OMAP_WDT_WPS 0x34
26#define OMAP_WDT_SPR 0x48 27#define OMAP_WDT_SPR 0x48
27 28
29/* Maximum microseconds to wait for OMAP module to softreset */
30#define MAX_MODULE_SOFTRESET_WAIT 10000
28 31
29int omap2_wd_timer_disable(struct omap_hwmod *oh) 32int omap2_wd_timer_disable(struct omap_hwmod *oh)
30{ 33{
@@ -54,3 +57,45 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
54 return 0; 57 return 0;
55} 58}
56 59
60/**
61 * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
62 * @oh: struct omap_hwmod *
63 *
64 * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
65 * care to execute the special watchdog disable sequence. This is
66 * because the watchdog is re-armed upon OCP softreset. (On OMAP4,
67 * this behavior was apparently changed and the watchdog is no longer
68 * re-armed after an OCP soft-reset.) Returns -ETIMEDOUT if the reset
69 * did not complete, or 0 upon success.
70 *
71 * XXX Most of this code should be moved to the omap_hwmod.c layer
72 * during a normal merge window. omap_hwmod_softreset() should be
73 * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
74 * should call the hwmod _ocp_softreset() code.
75 */
76int omap2_wd_timer_reset(struct omap_hwmod *oh)
77{
78 int c = 0;
79
80 /* Write to the SOFTRESET bit */
81 omap_hwmod_softreset(oh);
82
83 /* Poll on RESETDONE bit */
84 omap_test_timeout((omap_hwmod_read(oh,
85 oh->class->sysc->syss_offs)
86 & SYSS_RESETDONE_MASK),
87 MAX_MODULE_SOFTRESET_WAIT, c);
88
89 if (oh->class->sysc->srst_udelay)
90 udelay(oh->class->sysc->srst_udelay);
91
92 if (c == MAX_MODULE_SOFTRESET_WAIT)
93 pr_warning("%s: %s: softreset failed (waited %d usec)\n",
94 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
95 else
96 pr_debug("%s: %s: softreset in %d usec\n", __func__,
97 oh->name, c);
98
99 return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
100 omap2_wd_timer_disable(oh);
101}
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index e0054a2d5505..f6bbba73b535 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -13,5 +13,6 @@
13#include <plat/omap_hwmod.h> 13#include <plat/omap_hwmod.h>
14 14
15extern int omap2_wd_timer_disable(struct omap_hwmod *oh); 15extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
16extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
16 17
17#endif 18#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 23:55:33 -0500