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authorJoel Fernandes <joelf@ti.com>2014-04-22 15:40:39 -0400
committerTony Lindgren <tony@atomide.com>2014-04-25 12:48:20 -0400
commitda0159fdb57d6fab54ce3179659a1f9e5b593752 (patch)
tree1dee6050e4e7543e0373de5c143c310aedbd6e9f /arch/arm/mach-omap2
parent1ff3859e7ea134c09512498aa2251fd3a57d250d (diff)
ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU
On my DRA7 system, when the kernel is built in Thumb-2 mode, the secondary CPU (Cortex A15) fails to come up causing SMP boot on second CPU to timeout. This seems to be because the CPU is in ARM mode once the ROM hands over control to the kernel. Switch to Thumb-2 mode if required once the kernel is control of secondary CPU. On OMAP4 on the other hand, it appears to be in Thumb-2 mode on entry so this is not required and SMP boot works as is. Also corrected a spurious '+' and updated copyright information. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Joel Fernandes <joelf@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e92952c18e..40c5d5f1451c 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Secondary CPU startup routine source file. 2 * Secondary CPU startup routine source file.
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2014 Texas Instruments, Inc.
5 * 5 *
6 * Author: 6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
@@ -28,9 +28,13 @@
28 * code. This routine also provides a holding flag into which 28 * code. This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise. 29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware 30 * The primary core will update this flag using a hardware
31+ * register AuxCoreBoot0. 31 * register AuxCoreBoot0.
32 */ 32 */
33ENTRY(omap5_secondary_startup) 33ENTRY(omap5_secondary_startup)
34.arm
35THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
36THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
37THUMB( .thumb ) @ switch to Thumb now.
34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 38wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
35 ldr r0, [r2] 39 ldr r0, [r2]
36 mov r0, r0, lsr #5 40 mov r0, r0, lsr #5