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authorPaul Walmsley <paul@pwsan.com>2011-02-25 17:39:30 -0500
committerPaul Walmsley <paul@pwsan.com>2011-03-07 22:03:44 -0500
commita1d5562315a1e911c8448b7fac33c966f9cb6294 (patch)
tree24b2ca962644000ea86b6ae641548afe08869f27 /arch/arm/mach-omap2
parente892b2528b8dc9eef8ca3f9af7b5b650b4e90bea (diff)
OMAP2430: clock: use autoidle clkops for all autoidle-controllable interface clocks
Mark each interface clock with a corresponding CM_AUTOIDLE bit with a clkops that has the allow_idle/deny_idle function pointers populated. This allows the OMAP clock framework to enable and disable autoidle for these clocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c125
1 files changed, 69 insertions, 56 deletions
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 1ff150a0f304..34daed9cd56f 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -2,7 +2,7 @@
2 * linux/arch/arm/mach-omap2/clock2430_data.c 2 * linux/arch/arm/mach-omap2/clock2430_data.c
3 * 3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation 5 * Copyright (C) 2004-2011 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
@@ -525,7 +525,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
525/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ 525/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
526static struct clk usb_l4_ick = { /* FS-USB interface clock */ 526static struct clk usb_l4_ick = { /* FS-USB interface clock */
527 .name = "usb_l4_ick", 527 .name = "usb_l4_ick",
528 .ops = &clkops_omap2_dflt_wait, 528 .ops = &clkops_omap2_iclk_dflt_wait,
529 .parent = &core_l3_ck, 529 .parent = &core_l3_ck,
530 .clkdm_name = "core_l4_clkdm", 530 .clkdm_name = "core_l4_clkdm",
531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -606,7 +606,7 @@ static struct clk ssi_ssr_sst_fck = {
606 */ 606 */
607static struct clk ssi_l4_ick = { 607static struct clk ssi_l4_ick = {
608 .name = "ssi_l4_ick", 608 .name = "ssi_l4_ick",
609 .ops = &clkops_omap2_dflt_wait, 609 .ops = &clkops_omap2_iclk_dflt_wait,
610 .parent = &l4_ck, 610 .parent = &l4_ck,
611 .clkdm_name = "core_l4_clkdm", 611 .clkdm_name = "core_l4_clkdm",
612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 612 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,6 +661,7 @@ static struct clk gfx_2d_fck = {
661 .recalc = &omap2_clksel_recalc, 661 .recalc = &omap2_clksel_recalc,
662}; 662};
663 663
664/* This interface clock does not have a CM_AUTOIDLE bit */
664static struct clk gfx_ick = { 665static struct clk gfx_ick = {
665 .name = "gfx_ick", /* From l3 */ 666 .name = "gfx_ick", /* From l3 */
666 .ops = &clkops_omap2_dflt_wait, 667 .ops = &clkops_omap2_dflt_wait,
@@ -693,7 +694,7 @@ static const struct clksel mdm_ick_clksel[] = {
693 694
694static struct clk mdm_ick = { /* used both as a ick and fck */ 695static struct clk mdm_ick = { /* used both as a ick and fck */
695 .name = "mdm_ick", 696 .name = "mdm_ick",
696 .ops = &clkops_omap2_dflt_wait, 697 .ops = &clkops_omap2_iclk_dflt_wait,
697 .parent = &core_ck, 698 .parent = &core_ck,
698 .clkdm_name = "mdm_clkdm", 699 .clkdm_name = "mdm_clkdm",
699 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 700 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -706,7 +707,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
706 707
707static struct clk mdm_osc_ck = { 708static struct clk mdm_osc_ck = {
708 .name = "mdm_osc_ck", 709 .name = "mdm_osc_ck",
709 .ops = &clkops_omap2_dflt_wait, 710 .ops = &clkops_omap2_mdmclk_dflt_wait,
710 .parent = &osc_ck, 711 .parent = &osc_ck,
711 .clkdm_name = "mdm_clkdm", 712 .clkdm_name = "mdm_clkdm",
712 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), 713 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -751,7 +752,7 @@ static const struct clksel dss1_fck_clksel[] = {
751 752
752static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ 753static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
753 .name = "dss_ick", 754 .name = "dss_ick",
754 .ops = &clkops_omap2_dflt, 755 .ops = &clkops_omap2_iclk_dflt,
755 .parent = &l4_ck, /* really both l3 and l4 */ 756 .parent = &l4_ck, /* really both l3 and l4 */
756 .clkdm_name = "dss_clkdm", 757 .clkdm_name = "dss_clkdm",
757 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 758 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -833,7 +834,7 @@ static const struct clksel omap24xx_gpt_clksel[] = {
833 834
834static struct clk gpt1_ick = { 835static struct clk gpt1_ick = {
835 .name = "gpt1_ick", 836 .name = "gpt1_ick",
836 .ops = &clkops_omap2_dflt_wait, 837 .ops = &clkops_omap2_iclk_dflt_wait,
837 .parent = &l4_ck, 838 .parent = &l4_ck,
838 .clkdm_name = "core_l4_clkdm", 839 .clkdm_name = "core_l4_clkdm",
839 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 840 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -859,7 +860,7 @@ static struct clk gpt1_fck = {
859 860
860static struct clk gpt2_ick = { 861static struct clk gpt2_ick = {
861 .name = "gpt2_ick", 862 .name = "gpt2_ick",
862 .ops = &clkops_omap2_dflt_wait, 863 .ops = &clkops_omap2_iclk_dflt_wait,
863 .parent = &l4_ck, 864 .parent = &l4_ck,
864 .clkdm_name = "core_l4_clkdm", 865 .clkdm_name = "core_l4_clkdm",
865 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -883,7 +884,7 @@ static struct clk gpt2_fck = {
883 884
884static struct clk gpt3_ick = { 885static struct clk gpt3_ick = {
885 .name = "gpt3_ick", 886 .name = "gpt3_ick",
886 .ops = &clkops_omap2_dflt_wait, 887 .ops = &clkops_omap2_iclk_dflt_wait,
887 .parent = &l4_ck, 888 .parent = &l4_ck,
888 .clkdm_name = "core_l4_clkdm", 889 .clkdm_name = "core_l4_clkdm",
889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 890 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -907,7 +908,7 @@ static struct clk gpt3_fck = {
907 908
908static struct clk gpt4_ick = { 909static struct clk gpt4_ick = {
909 .name = "gpt4_ick", 910 .name = "gpt4_ick",
910 .ops = &clkops_omap2_dflt_wait, 911 .ops = &clkops_omap2_iclk_dflt_wait,
911 .parent = &l4_ck, 912 .parent = &l4_ck,
912 .clkdm_name = "core_l4_clkdm", 913 .clkdm_name = "core_l4_clkdm",
913 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 914 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -931,7 +932,7 @@ static struct clk gpt4_fck = {
931 932
932static struct clk gpt5_ick = { 933static struct clk gpt5_ick = {
933 .name = "gpt5_ick", 934 .name = "gpt5_ick",
934 .ops = &clkops_omap2_dflt_wait, 935 .ops = &clkops_omap2_iclk_dflt_wait,
935 .parent = &l4_ck, 936 .parent = &l4_ck,
936 .clkdm_name = "core_l4_clkdm", 937 .clkdm_name = "core_l4_clkdm",
937 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 938 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -955,7 +956,7 @@ static struct clk gpt5_fck = {
955 956
956static struct clk gpt6_ick = { 957static struct clk gpt6_ick = {
957 .name = "gpt6_ick", 958 .name = "gpt6_ick",
958 .ops = &clkops_omap2_dflt_wait, 959 .ops = &clkops_omap2_iclk_dflt_wait,
959 .parent = &l4_ck, 960 .parent = &l4_ck,
960 .clkdm_name = "core_l4_clkdm", 961 .clkdm_name = "core_l4_clkdm",
961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 962 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -979,7 +980,7 @@ static struct clk gpt6_fck = {
979 980
980static struct clk gpt7_ick = { 981static struct clk gpt7_ick = {
981 .name = "gpt7_ick", 982 .name = "gpt7_ick",
982 .ops = &clkops_omap2_dflt_wait, 983 .ops = &clkops_omap2_iclk_dflt_wait,
983 .parent = &l4_ck, 984 .parent = &l4_ck,
984 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 985 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
985 .enable_bit = OMAP24XX_EN_GPT7_SHIFT, 986 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
@@ -1002,7 +1003,7 @@ static struct clk gpt7_fck = {
1002 1003
1003static struct clk gpt8_ick = { 1004static struct clk gpt8_ick = {
1004 .name = "gpt8_ick", 1005 .name = "gpt8_ick",
1005 .ops = &clkops_omap2_dflt_wait, 1006 .ops = &clkops_omap2_iclk_dflt_wait,
1006 .parent = &l4_ck, 1007 .parent = &l4_ck,
1007 .clkdm_name = "core_l4_clkdm", 1008 .clkdm_name = "core_l4_clkdm",
1008 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1009 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1026,7 +1027,7 @@ static struct clk gpt8_fck = {
1026 1027
1027static struct clk gpt9_ick = { 1028static struct clk gpt9_ick = {
1028 .name = "gpt9_ick", 1029 .name = "gpt9_ick",
1029 .ops = &clkops_omap2_dflt_wait, 1030 .ops = &clkops_omap2_iclk_dflt_wait,
1030 .parent = &l4_ck, 1031 .parent = &l4_ck,
1031 .clkdm_name = "core_l4_clkdm", 1032 .clkdm_name = "core_l4_clkdm",
1032 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1033 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1050,7 +1051,7 @@ static struct clk gpt9_fck = {
1050 1051
1051static struct clk gpt10_ick = { 1052static struct clk gpt10_ick = {
1052 .name = "gpt10_ick", 1053 .name = "gpt10_ick",
1053 .ops = &clkops_omap2_dflt_wait, 1054 .ops = &clkops_omap2_iclk_dflt_wait,
1054 .parent = &l4_ck, 1055 .parent = &l4_ck,
1055 .clkdm_name = "core_l4_clkdm", 1056 .clkdm_name = "core_l4_clkdm",
1056 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1057 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1074,7 +1075,7 @@ static struct clk gpt10_fck = {
1074 1075
1075static struct clk gpt11_ick = { 1076static struct clk gpt11_ick = {
1076 .name = "gpt11_ick", 1077 .name = "gpt11_ick",
1077 .ops = &clkops_omap2_dflt_wait, 1078 .ops = &clkops_omap2_iclk_dflt_wait,
1078 .parent = &l4_ck, 1079 .parent = &l4_ck,
1079 .clkdm_name = "core_l4_clkdm", 1080 .clkdm_name = "core_l4_clkdm",
1080 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1098,7 +1099,7 @@ static struct clk gpt11_fck = {
1098 1099
1099static struct clk gpt12_ick = { 1100static struct clk gpt12_ick = {
1100 .name = "gpt12_ick", 1101 .name = "gpt12_ick",
1101 .ops = &clkops_omap2_dflt_wait, 1102 .ops = &clkops_omap2_iclk_dflt_wait,
1102 .parent = &l4_ck, 1103 .parent = &l4_ck,
1103 .clkdm_name = "core_l4_clkdm", 1104 .clkdm_name = "core_l4_clkdm",
1104 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1122,7 +1123,7 @@ static struct clk gpt12_fck = {
1122 1123
1123static struct clk mcbsp1_ick = { 1124static struct clk mcbsp1_ick = {
1124 .name = "mcbsp1_ick", 1125 .name = "mcbsp1_ick",
1125 .ops = &clkops_omap2_dflt_wait, 1126 .ops = &clkops_omap2_iclk_dflt_wait,
1126 .parent = &l4_ck, 1127 .parent = &l4_ck,
1127 .clkdm_name = "core_l4_clkdm", 1128 .clkdm_name = "core_l4_clkdm",
1128 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1162,7 +1163,7 @@ static struct clk mcbsp1_fck = {
1162 1163
1163static struct clk mcbsp2_ick = { 1164static struct clk mcbsp2_ick = {
1164 .name = "mcbsp2_ick", 1165 .name = "mcbsp2_ick",
1165 .ops = &clkops_omap2_dflt_wait, 1166 .ops = &clkops_omap2_iclk_dflt_wait,
1166 .parent = &l4_ck, 1167 .parent = &l4_ck,
1167 .clkdm_name = "core_l4_clkdm", 1168 .clkdm_name = "core_l4_clkdm",
1168 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1169 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1186,7 +1187,7 @@ static struct clk mcbsp2_fck = {
1186 1187
1187static struct clk mcbsp3_ick = { 1188static struct clk mcbsp3_ick = {
1188 .name = "mcbsp3_ick", 1189 .name = "mcbsp3_ick",
1189 .ops = &clkops_omap2_dflt_wait, 1190 .ops = &clkops_omap2_iclk_dflt_wait,
1190 .parent = &l4_ck, 1191 .parent = &l4_ck,
1191 .clkdm_name = "core_l4_clkdm", 1192 .clkdm_name = "core_l4_clkdm",
1192 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1193 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1210,7 +1211,7 @@ static struct clk mcbsp3_fck = {
1210 1211
1211static struct clk mcbsp4_ick = { 1212static struct clk mcbsp4_ick = {
1212 .name = "mcbsp4_ick", 1213 .name = "mcbsp4_ick",
1213 .ops = &clkops_omap2_dflt_wait, 1214 .ops = &clkops_omap2_iclk_dflt_wait,
1214 .parent = &l4_ck, 1215 .parent = &l4_ck,
1215 .clkdm_name = "core_l4_clkdm", 1216 .clkdm_name = "core_l4_clkdm",
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1217 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1234,7 +1235,7 @@ static struct clk mcbsp4_fck = {
1234 1235
1235static struct clk mcbsp5_ick = { 1236static struct clk mcbsp5_ick = {
1236 .name = "mcbsp5_ick", 1237 .name = "mcbsp5_ick",
1237 .ops = &clkops_omap2_dflt_wait, 1238 .ops = &clkops_omap2_iclk_dflt_wait,
1238 .parent = &l4_ck, 1239 .parent = &l4_ck,
1239 .clkdm_name = "core_l4_clkdm", 1240 .clkdm_name = "core_l4_clkdm",
1240 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1241 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1258,7 +1259,7 @@ static struct clk mcbsp5_fck = {
1258 1259
1259static struct clk mcspi1_ick = { 1260static struct clk mcspi1_ick = {
1260 .name = "mcspi1_ick", 1261 .name = "mcspi1_ick",
1261 .ops = &clkops_omap2_dflt_wait, 1262 .ops = &clkops_omap2_iclk_dflt_wait,
1262 .parent = &l4_ck, 1263 .parent = &l4_ck,
1263 .clkdm_name = "core_l4_clkdm", 1264 .clkdm_name = "core_l4_clkdm",
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1265 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1279,7 @@ static struct clk mcspi1_fck = {
1278 1279
1279static struct clk mcspi2_ick = { 1280static struct clk mcspi2_ick = {
1280 .name = "mcspi2_ick", 1281 .name = "mcspi2_ick",
1281 .ops = &clkops_omap2_dflt_wait, 1282 .ops = &clkops_omap2_iclk_dflt_wait,
1282 .parent = &l4_ck, 1283 .parent = &l4_ck,
1283 .clkdm_name = "core_l4_clkdm", 1284 .clkdm_name = "core_l4_clkdm",
1284 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1285 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1298,7 +1299,7 @@ static struct clk mcspi2_fck = {
1298 1299
1299static struct clk mcspi3_ick = { 1300static struct clk mcspi3_ick = {
1300 .name = "mcspi3_ick", 1301 .name = "mcspi3_ick",
1301 .ops = &clkops_omap2_dflt_wait, 1302 .ops = &clkops_omap2_iclk_dflt_wait,
1302 .parent = &l4_ck, 1303 .parent = &l4_ck,
1303 .clkdm_name = "core_l4_clkdm", 1304 .clkdm_name = "core_l4_clkdm",
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1305 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1318,7 +1319,7 @@ static struct clk mcspi3_fck = {
1318 1319
1319static struct clk uart1_ick = { 1320static struct clk uart1_ick = {
1320 .name = "uart1_ick", 1321 .name = "uart1_ick",
1321 .ops = &clkops_omap2_dflt_wait, 1322 .ops = &clkops_omap2_iclk_dflt_wait,
1322 .parent = &l4_ck, 1323 .parent = &l4_ck,
1323 .clkdm_name = "core_l4_clkdm", 1324 .clkdm_name = "core_l4_clkdm",
1324 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1325 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1338,7 +1339,7 @@ static struct clk uart1_fck = {
1338 1339
1339static struct clk uart2_ick = { 1340static struct clk uart2_ick = {
1340 .name = "uart2_ick", 1341 .name = "uart2_ick",
1341 .ops = &clkops_omap2_dflt_wait, 1342 .ops = &clkops_omap2_iclk_dflt_wait,
1342 .parent = &l4_ck, 1343 .parent = &l4_ck,
1343 .clkdm_name = "core_l4_clkdm", 1344 .clkdm_name = "core_l4_clkdm",
1344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1345 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1358,7 +1359,7 @@ static struct clk uart2_fck = {
1358 1359
1359static struct clk uart3_ick = { 1360static struct clk uart3_ick = {
1360 .name = "uart3_ick", 1361 .name = "uart3_ick",
1361 .ops = &clkops_omap2_dflt_wait, 1362 .ops = &clkops_omap2_iclk_dflt_wait,
1362 .parent = &l4_ck, 1363 .parent = &l4_ck,
1363 .clkdm_name = "core_l4_clkdm", 1364 .clkdm_name = "core_l4_clkdm",
1364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1365 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1378,7 +1379,7 @@ static struct clk uart3_fck = {
1378 1379
1379static struct clk gpios_ick = { 1380static struct clk gpios_ick = {
1380 .name = "gpios_ick", 1381 .name = "gpios_ick",
1381 .ops = &clkops_omap2_dflt_wait, 1382 .ops = &clkops_omap2_iclk_dflt_wait,
1382 .parent = &l4_ck, 1383 .parent = &l4_ck,
1383 .clkdm_name = "core_l4_clkdm", 1384 .clkdm_name = "core_l4_clkdm",
1384 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1385 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1398,7 +1399,7 @@ static struct clk gpios_fck = {
1398 1399
1399static struct clk mpu_wdt_ick = { 1400static struct clk mpu_wdt_ick = {
1400 .name = "mpu_wdt_ick", 1401 .name = "mpu_wdt_ick",
1401 .ops = &clkops_omap2_dflt_wait, 1402 .ops = &clkops_omap2_iclk_dflt_wait,
1402 .parent = &l4_ck, 1403 .parent = &l4_ck,
1403 .clkdm_name = "core_l4_clkdm", 1404 .clkdm_name = "core_l4_clkdm",
1404 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1405 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1418,7 +1419,7 @@ static struct clk mpu_wdt_fck = {
1418 1419
1419static struct clk sync_32k_ick = { 1420static struct clk sync_32k_ick = {
1420 .name = "sync_32k_ick", 1421 .name = "sync_32k_ick",
1421 .ops = &clkops_omap2_dflt_wait, 1422 .ops = &clkops_omap2_iclk_dflt_wait,
1422 .parent = &l4_ck, 1423 .parent = &l4_ck,
1423 .flags = ENABLE_ON_INIT, 1424 .flags = ENABLE_ON_INIT,
1424 .clkdm_name = "core_l4_clkdm", 1425 .clkdm_name = "core_l4_clkdm",
@@ -1429,7 +1430,7 @@ static struct clk sync_32k_ick = {
1429 1430
1430static struct clk wdt1_ick = { 1431static struct clk wdt1_ick = {
1431 .name = "wdt1_ick", 1432 .name = "wdt1_ick",
1432 .ops = &clkops_omap2_dflt_wait, 1433 .ops = &clkops_omap2_iclk_dflt_wait,
1433 .parent = &l4_ck, 1434 .parent = &l4_ck,
1434 .clkdm_name = "core_l4_clkdm", 1435 .clkdm_name = "core_l4_clkdm",
1435 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1436 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1439,7 +1440,7 @@ static struct clk wdt1_ick = {
1439 1440
1440static struct clk omapctrl_ick = { 1441static struct clk omapctrl_ick = {
1441 .name = "omapctrl_ick", 1442 .name = "omapctrl_ick",
1442 .ops = &clkops_omap2_dflt_wait, 1443 .ops = &clkops_omap2_iclk_dflt_wait,
1443 .parent = &l4_ck, 1444 .parent = &l4_ck,
1444 .flags = ENABLE_ON_INIT, 1445 .flags = ENABLE_ON_INIT,
1445 .clkdm_name = "core_l4_clkdm", 1446 .clkdm_name = "core_l4_clkdm",
@@ -1450,7 +1451,7 @@ static struct clk omapctrl_ick = {
1450 1451
1451static struct clk icr_ick = { 1452static struct clk icr_ick = {
1452 .name = "icr_ick", 1453 .name = "icr_ick",
1453 .ops = &clkops_omap2_dflt_wait, 1454 .ops = &clkops_omap2_iclk_dflt_wait,
1454 .parent = &l4_ck, 1455 .parent = &l4_ck,
1455 .clkdm_name = "core_l4_clkdm", 1456 .clkdm_name = "core_l4_clkdm",
1456 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 1457 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
@@ -1460,7 +1461,7 @@ static struct clk icr_ick = {
1460 1461
1461static struct clk cam_ick = { 1462static struct clk cam_ick = {
1462 .name = "cam_ick", 1463 .name = "cam_ick",
1463 .ops = &clkops_omap2_dflt, 1464 .ops = &clkops_omap2_iclk_dflt,
1464 .parent = &l4_ck, 1465 .parent = &l4_ck,
1465 .clkdm_name = "core_l4_clkdm", 1466 .clkdm_name = "core_l4_clkdm",
1466 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1467 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1486,7 @@ static struct clk cam_fck = {
1485 1486
1486static struct clk mailboxes_ick = { 1487static struct clk mailboxes_ick = {
1487 .name = "mailboxes_ick", 1488 .name = "mailboxes_ick",
1488 .ops = &clkops_omap2_dflt_wait, 1489 .ops = &clkops_omap2_iclk_dflt_wait,
1489 .parent = &l4_ck, 1490 .parent = &l4_ck,
1490 .clkdm_name = "core_l4_clkdm", 1491 .clkdm_name = "core_l4_clkdm",
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1492 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1495,7 +1496,7 @@ static struct clk mailboxes_ick = {
1495 1496
1496static struct clk wdt4_ick = { 1497static struct clk wdt4_ick = {
1497 .name = "wdt4_ick", 1498 .name = "wdt4_ick",
1498 .ops = &clkops_omap2_dflt_wait, 1499 .ops = &clkops_omap2_iclk_dflt_wait,
1499 .parent = &l4_ck, 1500 .parent = &l4_ck,
1500 .clkdm_name = "core_l4_clkdm", 1501 .clkdm_name = "core_l4_clkdm",
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1502 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1515,7 +1516,7 @@ static struct clk wdt4_fck = {
1515 1516
1516static struct clk mspro_ick = { 1517static struct clk mspro_ick = {
1517 .name = "mspro_ick", 1518 .name = "mspro_ick",
1518 .ops = &clkops_omap2_dflt_wait, 1519 .ops = &clkops_omap2_iclk_dflt_wait,
1519 .parent = &l4_ck, 1520 .parent = &l4_ck,
1520 .clkdm_name = "core_l4_clkdm", 1521 .clkdm_name = "core_l4_clkdm",
1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1535,7 +1536,7 @@ static struct clk mspro_fck = {
1535 1536
1536static struct clk fac_ick = { 1537static struct clk fac_ick = {
1537 .name = "fac_ick", 1538 .name = "fac_ick",
1538 .ops = &clkops_omap2_dflt_wait, 1539 .ops = &clkops_omap2_iclk_dflt_wait,
1539 .parent = &l4_ck, 1540 .parent = &l4_ck,
1540 .clkdm_name = "core_l4_clkdm", 1541 .clkdm_name = "core_l4_clkdm",
1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1555,7 +1556,7 @@ static struct clk fac_fck = {
1555 1556
1556static struct clk hdq_ick = { 1557static struct clk hdq_ick = {
1557 .name = "hdq_ick", 1558 .name = "hdq_ick",
1558 .ops = &clkops_omap2_dflt_wait, 1559 .ops = &clkops_omap2_iclk_dflt_wait,
1559 .parent = &l4_ck, 1560 .parent = &l4_ck,
1560 .clkdm_name = "core_l4_clkdm", 1561 .clkdm_name = "core_l4_clkdm",
1561 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1562 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1579,7 +1580,7 @@ static struct clk hdq_fck = {
1579 */ 1580 */
1580static struct clk i2c2_ick = { 1581static struct clk i2c2_ick = {
1581 .name = "i2c2_ick", 1582 .name = "i2c2_ick",
1582 .ops = &clkops_omap2_dflt_wait, 1583 .ops = &clkops_omap2_iclk_dflt_wait,
1583 .parent = &l4_ck, 1584 .parent = &l4_ck,
1584 .clkdm_name = "core_l4_clkdm", 1585 .clkdm_name = "core_l4_clkdm",
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1603,7 +1604,7 @@ static struct clk i2chs2_fck = {
1603 */ 1604 */
1604static struct clk i2c1_ick = { 1605static struct clk i2c1_ick = {
1605 .name = "i2c1_ick", 1606 .name = "i2c1_ick",
1606 .ops = &clkops_omap2_dflt_wait, 1607 .ops = &clkops_omap2_iclk_dflt_wait,
1607 .parent = &l4_ck, 1608 .parent = &l4_ck,
1608 .clkdm_name = "core_l4_clkdm", 1609 .clkdm_name = "core_l4_clkdm",
1609 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1621,12 +1622,18 @@ static struct clk i2chs1_fck = {
1621 .recalc = &followparent_recalc, 1622 .recalc = &followparent_recalc,
1622}; 1623};
1623 1624
1625/*
1626 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1627 * accesses derived from this data.
1628 */
1624static struct clk gpmc_fck = { 1629static struct clk gpmc_fck = {
1625 .name = "gpmc_fck", 1630 .name = "gpmc_fck",
1626 .ops = &clkops_null, /* RMK: missing? */ 1631 .ops = &clkops_omap2_iclk_idle_only,
1627 .parent = &core_l3_ck, 1632 .parent = &core_l3_ck,
1628 .flags = ENABLE_ON_INIT, 1633 .flags = ENABLE_ON_INIT,
1629 .clkdm_name = "core_l3_clkdm", 1634 .clkdm_name = "core_l3_clkdm",
1635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1636 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
1630 .recalc = &followparent_recalc, 1637 .recalc = &followparent_recalc,
1631}; 1638};
1632 1639
@@ -1638,17 +1645,23 @@ static struct clk sdma_fck = {
1638 .recalc = &followparent_recalc, 1645 .recalc = &followparent_recalc,
1639}; 1646};
1640 1647
1648/*
1649 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1650 * accesses derived from this data.
1651 */
1641static struct clk sdma_ick = { 1652static struct clk sdma_ick = {
1642 .name = "sdma_ick", 1653 .name = "sdma_ick",
1643 .ops = &clkops_null, /* RMK: missing? */ 1654 .ops = &clkops_omap2_iclk_idle_only,
1644 .parent = &l4_ck, 1655 .parent = &l4_ck,
1645 .clkdm_name = "core_l3_clkdm", 1656 .clkdm_name = "core_l3_clkdm",
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1658 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1646 .recalc = &followparent_recalc, 1659 .recalc = &followparent_recalc,
1647}; 1660};
1648 1661
1649static struct clk sdrc_ick = { 1662static struct clk sdrc_ick = {
1650 .name = "sdrc_ick", 1663 .name = "sdrc_ick",
1651 .ops = &clkops_omap2_dflt_wait, 1664 .ops = &clkops_omap2_iclk_idle_only,
1652 .parent = &l4_ck, 1665 .parent = &l4_ck,
1653 .flags = ENABLE_ON_INIT, 1666 .flags = ENABLE_ON_INIT,
1654 .clkdm_name = "core_l4_clkdm", 1667 .clkdm_name = "core_l4_clkdm",
@@ -1659,7 +1672,7 @@ static struct clk sdrc_ick = {
1659 1672
1660static struct clk des_ick = { 1673static struct clk des_ick = {
1661 .name = "des_ick", 1674 .name = "des_ick",
1662 .ops = &clkops_omap2_dflt_wait, 1675 .ops = &clkops_omap2_iclk_dflt_wait,
1663 .parent = &l4_ck, 1676 .parent = &l4_ck,
1664 .clkdm_name = "core_l4_clkdm", 1677 .clkdm_name = "core_l4_clkdm",
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1678 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1682,7 @@ static struct clk des_ick = {
1669 1682
1670static struct clk sha_ick = { 1683static struct clk sha_ick = {
1671 .name = "sha_ick", 1684 .name = "sha_ick",
1672 .ops = &clkops_omap2_dflt_wait, 1685 .ops = &clkops_omap2_iclk_dflt_wait,
1673 .parent = &l4_ck, 1686 .parent = &l4_ck,
1674 .clkdm_name = "core_l4_clkdm", 1687 .clkdm_name = "core_l4_clkdm",
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1692,7 @@ static struct clk sha_ick = {
1679 1692
1680static struct clk rng_ick = { 1693static struct clk rng_ick = {
1681 .name = "rng_ick", 1694 .name = "rng_ick",
1682 .ops = &clkops_omap2_dflt_wait, 1695 .ops = &clkops_omap2_iclk_dflt_wait,
1683 .parent = &l4_ck, 1696 .parent = &l4_ck,
1684 .clkdm_name = "core_l4_clkdm", 1697 .clkdm_name = "core_l4_clkdm",
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1702,7 @@ static struct clk rng_ick = {
1689 1702
1690static struct clk aes_ick = { 1703static struct clk aes_ick = {
1691 .name = "aes_ick", 1704 .name = "aes_ick",
1692 .ops = &clkops_omap2_dflt_wait, 1705 .ops = &clkops_omap2_iclk_dflt_wait,
1693 .parent = &l4_ck, 1706 .parent = &l4_ck,
1694 .clkdm_name = "core_l4_clkdm", 1707 .clkdm_name = "core_l4_clkdm",
1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1712,7 @@ static struct clk aes_ick = {
1699 1712
1700static struct clk pka_ick = { 1713static struct clk pka_ick = {
1701 .name = "pka_ick", 1714 .name = "pka_ick",
1702 .ops = &clkops_omap2_dflt_wait, 1715 .ops = &clkops_omap2_iclk_dflt_wait,
1703 .parent = &l4_ck, 1716 .parent = &l4_ck,
1704 .clkdm_name = "core_l4_clkdm", 1717 .clkdm_name = "core_l4_clkdm",
1705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), 1718 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1719,7 +1732,7 @@ static struct clk usb_fck = {
1719 1732
1720static struct clk usbhs_ick = { 1733static struct clk usbhs_ick = {
1721 .name = "usbhs_ick", 1734 .name = "usbhs_ick",
1722 .ops = &clkops_omap2_dflt_wait, 1735 .ops = &clkops_omap2_iclk_dflt_wait,
1723 .parent = &core_l3_ck, 1736 .parent = &core_l3_ck,
1724 .clkdm_name = "core_l3_clkdm", 1737 .clkdm_name = "core_l3_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1738 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1729,7 +1742,7 @@ static struct clk usbhs_ick = {
1729 1742
1730static struct clk mmchs1_ick = { 1743static struct clk mmchs1_ick = {
1731 .name = "mmchs1_ick", 1744 .name = "mmchs1_ick",
1732 .ops = &clkops_omap2_dflt_wait, 1745 .ops = &clkops_omap2_iclk_dflt_wait,
1733 .parent = &l4_ck, 1746 .parent = &l4_ck,
1734 .clkdm_name = "core_l4_clkdm", 1747 .clkdm_name = "core_l4_clkdm",
1735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1748 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1749,7 +1762,7 @@ static struct clk mmchs1_fck = {
1749 1762
1750static struct clk mmchs2_ick = { 1763static struct clk mmchs2_ick = {
1751 .name = "mmchs2_ick", 1764 .name = "mmchs2_ick",
1752 .ops = &clkops_omap2_dflt_wait, 1765 .ops = &clkops_omap2_iclk_dflt_wait,
1753 .parent = &l4_ck, 1766 .parent = &l4_ck,
1754 .clkdm_name = "core_l4_clkdm", 1767 .clkdm_name = "core_l4_clkdm",
1755 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1768 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1768,7 +1781,7 @@ static struct clk mmchs2_fck = {
1768 1781
1769static struct clk gpio5_ick = { 1782static struct clk gpio5_ick = {
1770 .name = "gpio5_ick", 1783 .name = "gpio5_ick",
1771 .ops = &clkops_omap2_dflt_wait, 1784 .ops = &clkops_omap2_iclk_dflt_wait,
1772 .parent = &l4_ck, 1785 .parent = &l4_ck,
1773 .clkdm_name = "core_l4_clkdm", 1786 .clkdm_name = "core_l4_clkdm",
1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1788,7 +1801,7 @@ static struct clk gpio5_fck = {
1788 1801
1789static struct clk mdm_intc_ick = { 1802static struct clk mdm_intc_ick = {
1790 .name = "mdm_intc_ick", 1803 .name = "mdm_intc_ick",
1791 .ops = &clkops_omap2_dflt_wait, 1804 .ops = &clkops_omap2_iclk_dflt_wait,
1792 .parent = &l4_ck, 1805 .parent = &l4_ck,
1793 .clkdm_name = "core_l4_clkdm", 1806 .clkdm_name = "core_l4_clkdm",
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),