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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:24 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 14:29:42 -0500
commit8c34974ab0ecbbcdabd343f8cd0013cd2d2b0fa8 (patch)
tree5d64fc187d5dcee6d82c20f09f4b1a6ff2abef5c /arch/arm/mach-omap2
parent5173804fbbbff82a2fd40bc1c46655b272167af5 (diff)
OMAP2 clock: drop DELAYED_APP clock flag
All of the clocks that are marked with DELAYED_APP are changed as part of the virt_prcm_set OPP virtual clock. On 24xx, these clocks all need to be changed as part of a group to keep the clock tree functional - hence the need for the VALID_CONFIG bit, which is not present on later OMAPs. These clocks should not be rate-changed independently. So prevent these clocks from being changed independently by dropping their .round_rate and .set_rate function pointers. It then turns out that the DELAYED_APP clock flag is no longer useful, so drop it and the associated code and renumber the clock flags. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/clkt_clksel.c4
-rw-r--r--arch/arm/mach-omap2/clock.c27
-rw-r--r--arch/arm/mach-omap2/clock.h1
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c20
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c17
5 files changed, 1 insertions, 68 deletions
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 25a2363106de..ade19f6369df 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -377,8 +377,6 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
377 377
378 clk->rate = clk->parent->rate / new_div; 378 clk->rate = clk->parent->rate / new_div;
379 379
380 omap2xxx_clk_commit(clk);
381
382 return 0; 380 return 0;
383} 381}
384 382
@@ -400,8 +398,6 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
400 __raw_writel(v, clk->clksel_reg); 398 __raw_writel(v, clk->clksel_reg);
401 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 399 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
402 400
403 omap2xxx_clk_commit(clk);
404
405 clk_reparent(clk, new_parent); 401 clk_reparent(clk, new_parent);
406 402
407 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 403 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 82b17ef17dbe..426d76f564e7 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -2,7 +2,7 @@
2 * linux/arch/arm/mach-omap2/clock.c 2 * linux/arch/arm/mach-omap2/clock.c
3 * 3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation 5 * Copyright (C) 2004-2010 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
@@ -14,12 +14,9 @@
14 */ 14 */
15#undef DEBUG 15#undef DEBUG
16 16
17#include <linux/module.h>
18#include <linux/kernel.h> 17#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/list.h> 18#include <linux/list.h>
21#include <linux/errno.h> 19#include <linux/errno.h>
22#include <linux/delay.h>
23#include <linux/clk.h> 20#include <linux/clk.h>
24#include <linux/io.h> 21#include <linux/io.h>
25#include <linux/bitops.h> 22#include <linux/bitops.h>
@@ -89,28 +86,6 @@ static void _omap2_clk_disable(struct clk *clk)
89/* Public functions */ 86/* Public functions */
90 87
91/** 88/**
92 * omap2xxx_clk_commit - commit clock parent/rate changes in hardware
93 * @clk: struct clk *
94 *
95 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
96 * don't take effect until the VALID_CONFIG bit is written, write the
97 * VALID_CONFIG bit and wait for the write to complete. No return value.
98 */
99void omap2xxx_clk_commit(struct clk *clk)
100{
101 if (!cpu_is_omap24xx())
102 return;
103
104 if (!(clk->flags & DELAYED_APP))
105 return;
106
107 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
108 OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
109 /* OCP barrier */
110 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
111}
112
113/**
114 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 89 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
115 * @clk: OMAP clock struct ptr to use 90 * @clk: OMAP clock struct ptr to use
116 * 91 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index f98dd0407e7e..7bf02534a4ff 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -119,7 +119,6 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
119 u8 *other_bit); 119 u8 *other_bit);
120void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 120void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
121 u8 *idlest_bit, u8 *idlest_val); 121 u8 *idlest_bit, u8 *idlest_val);
122void omap2xxx_clk_commit(struct clk *clk);
123 122
124extern u8 cpu_mask; 123extern u8 cpu_mask;
125 124
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 49adb0eec428..d5913f01e5d6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -404,7 +404,6 @@ static struct clk mpu_ck = { /* Control cpu */
404 .name = "mpu_ck", 404 .name = "mpu_ck",
405 .ops = &clkops_null, 405 .ops = &clkops_null,
406 .parent = &core_ck, 406 .parent = &core_ck,
407 .flags = DELAYED_APP,
408 .clkdm_name = "mpu_clkdm", 407 .clkdm_name = "mpu_clkdm",
409 .init = &omap2_init_clksel_parent, 408 .init = &omap2_init_clksel_parent,
410 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 409 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -443,7 +442,6 @@ static struct clk dsp_fck = {
443 .name = "dsp_fck", 442 .name = "dsp_fck",
444 .ops = &clkops_omap2_dflt_wait, 443 .ops = &clkops_omap2_dflt_wait,
445 .parent = &core_ck, 444 .parent = &core_ck,
446 .flags = DELAYED_APP,
447 .clkdm_name = "dsp_clkdm", 445 .clkdm_name = "dsp_clkdm",
448 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 446 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
449 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 447 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -470,7 +468,6 @@ static struct clk dsp_irate_ick = {
470 .name = "dsp_irate_ick", 468 .name = "dsp_irate_ick",
471 .ops = &clkops_null, 469 .ops = &clkops_null,
472 .parent = &dsp_fck, 470 .parent = &dsp_fck,
473 .flags = DELAYED_APP,
474 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 471 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
475 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 472 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
476 .clksel = dsp_irate_ick_clksel, 473 .clksel = dsp_irate_ick_clksel,
@@ -495,7 +492,6 @@ static struct clk iva1_ifck = {
495 .name = "iva1_ifck", 492 .name = "iva1_ifck",
496 .ops = &clkops_omap2_dflt_wait, 493 .ops = &clkops_omap2_dflt_wait,
497 .parent = &core_ck, 494 .parent = &core_ck,
498 .flags = DELAYED_APP,
499 .clkdm_name = "iva1_clkdm", 495 .clkdm_name = "iva1_clkdm",
500 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 496 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
501 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, 497 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
@@ -556,7 +552,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
556 .name = "core_l3_ck", 552 .name = "core_l3_ck",
557 .ops = &clkops_null, 553 .ops = &clkops_null,
558 .parent = &core_ck, 554 .parent = &core_ck,
559 .flags = DELAYED_APP,
560 .clkdm_name = "core_l3_clkdm", 555 .clkdm_name = "core_l3_clkdm",
561 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 556 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
562 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 557 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -582,7 +577,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
582 .name = "usb_l4_ick", 577 .name = "usb_l4_ick",
583 .ops = &clkops_omap2_dflt_wait, 578 .ops = &clkops_omap2_dflt_wait,
584 .parent = &core_l3_ck, 579 .parent = &core_l3_ck,
585 .flags = DELAYED_APP,
586 .clkdm_name = "core_l4_clkdm", 580 .clkdm_name = "core_l4_clkdm",
587 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 581 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
588 .enable_bit = OMAP24XX_EN_USB_SHIFT, 582 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -614,14 +608,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */
614 .name = "l4_ck", 608 .name = "l4_ck",
615 .ops = &clkops_null, 609 .ops = &clkops_null,
616 .parent = &core_l3_ck, 610 .parent = &core_l3_ck,
617 .flags = DELAYED_APP,
618 .clkdm_name = "core_l4_clkdm", 611 .clkdm_name = "core_l4_clkdm",
619 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 612 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
620 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 613 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
621 .clksel = l4_clksel, 614 .clksel = l4_clksel,
622 .recalc = &omap2_clksel_recalc, 615 .recalc = &omap2_clksel_recalc,
623 .round_rate = &omap2_clksel_round_rate,
624 .set_rate = &omap2_clksel_set_rate
625}; 616};
626 617
627/* 618/*
@@ -651,7 +642,6 @@ static struct clk ssi_ssr_sst_fck = {
651 .name = "ssi_fck", 642 .name = "ssi_fck",
652 .ops = &clkops_omap2_dflt_wait, 643 .ops = &clkops_omap2_dflt_wait,
653 .parent = &core_ck, 644 .parent = &core_ck,
654 .flags = DELAYED_APP,
655 .clkdm_name = "core_l3_clkdm", 645 .clkdm_name = "core_l3_clkdm",
656 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 646 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
657 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 647 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -659,8 +649,6 @@ static struct clk ssi_ssr_sst_fck = {
659 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, 649 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
660 .clksel = ssi_ssr_sst_fck_clksel, 650 .clksel = ssi_ssr_sst_fck_clksel,
661 .recalc = &omap2_clksel_recalc, 651 .recalc = &omap2_clksel_recalc,
662 .round_rate = &omap2_clksel_round_rate,
663 .set_rate = &omap2_clksel_set_rate
664}; 652};
665 653
666/* 654/*
@@ -715,7 +703,6 @@ static struct clk gfx_2d_fck = {
715 .name = "gfx_2d_fck", 703 .name = "gfx_2d_fck",
716 .ops = &clkops_omap2_dflt_wait, 704 .ops = &clkops_omap2_dflt_wait,
717 .parent = &core_l3_ck, 705 .parent = &core_l3_ck,
718 .flags = DELAYED_APP,
719 .clkdm_name = "gfx_clkdm", 706 .clkdm_name = "gfx_clkdm",
720 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 707 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
721 .enable_bit = OMAP24XX_EN_2D_SHIFT, 708 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -784,7 +771,6 @@ static struct clk dss1_fck = {
784 .name = "dss1_fck", 771 .name = "dss1_fck",
785 .ops = &clkops_omap2_dflt, 772 .ops = &clkops_omap2_dflt,
786 .parent = &core_ck, /* Core or sys */ 773 .parent = &core_ck, /* Core or sys */
787 .flags = DELAYED_APP,
788 .clkdm_name = "dss_clkdm", 774 .clkdm_name = "dss_clkdm",
789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 775 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
790 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 776 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -793,8 +779,6 @@ static struct clk dss1_fck = {
793 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, 779 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
794 .clksel = dss1_fck_clksel, 780 .clksel = dss1_fck_clksel,
795 .recalc = &omap2_clksel_recalc, 781 .recalc = &omap2_clksel_recalc,
796 .round_rate = &omap2_clksel_round_rate,
797 .set_rate = &omap2_clksel_set_rate
798}; 782};
799 783
800static const struct clksel_rate dss2_fck_sys_rates[] = { 784static const struct clksel_rate dss2_fck_sys_rates[] = {
@@ -817,7 +801,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
817 .name = "dss2_fck", 801 .name = "dss2_fck",
818 .ops = &clkops_omap2_dflt, 802 .ops = &clkops_omap2_dflt,
819 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 803 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
820 .flags = DELAYED_APP,
821 .clkdm_name = "dss_clkdm", 804 .clkdm_name = "dss_clkdm",
822 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
823 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 806 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
@@ -1636,7 +1619,6 @@ static struct clk vlynq_fck = {
1636 .name = "vlynq_fck", 1619 .name = "vlynq_fck",
1637 .ops = &clkops_omap2_dflt_wait, 1620 .ops = &clkops_omap2_dflt_wait,
1638 .parent = &func_96m_ck, 1621 .parent = &func_96m_ck,
1639 .flags = DELAYED_APP,
1640 .clkdm_name = "core_l3_clkdm", 1622 .clkdm_name = "core_l3_clkdm",
1641 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1623 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, 1624 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
@@ -1645,8 +1627,6 @@ static struct clk vlynq_fck = {
1645 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK, 1627 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1646 .clksel = vlynq_fck_clksel, 1628 .clksel = vlynq_fck_clksel,
1647 .recalc = &omap2_clksel_recalc, 1629 .recalc = &omap2_clksel_recalc,
1648 .round_rate = &omap2_clksel_round_rate,
1649 .set_rate = &omap2_clksel_set_rate
1650}; 1630};
1651 1631
1652static struct clk des_ick = { 1632static struct clk des_ick = {
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index daf643928c26..b3895840dc41 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -386,7 +386,6 @@ static struct clk mpu_ck = { /* Control cpu */
386 .name = "mpu_ck", 386 .name = "mpu_ck",
387 .ops = &clkops_null, 387 .ops = &clkops_null,
388 .parent = &core_ck, 388 .parent = &core_ck,
389 .flags = DELAYED_APP,
390 .clkdm_name = "mpu_clkdm", 389 .clkdm_name = "mpu_clkdm",
391 .init = &omap2_init_clksel_parent, 390 .init = &omap2_init_clksel_parent,
392 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 391 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -422,7 +421,6 @@ static struct clk dsp_fck = {
422 .name = "dsp_fck", 421 .name = "dsp_fck",
423 .ops = &clkops_omap2_dflt_wait, 422 .ops = &clkops_omap2_dflt_wait,
424 .parent = &core_ck, 423 .parent = &core_ck,
425 .flags = DELAYED_APP,
426 .clkdm_name = "dsp_clkdm", 424 .clkdm_name = "dsp_clkdm",
427 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 425 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
428 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 426 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -450,7 +448,6 @@ static struct clk dsp_irate_ick = {
450 .name = "dsp_irate_ick", 448 .name = "dsp_irate_ick",
451 .ops = &clkops_null, 449 .ops = &clkops_null,
452 .parent = &dsp_fck, 450 .parent = &dsp_fck,
453 .flags = DELAYED_APP,
454 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 451 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
455 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 452 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
456 .clksel = dsp_irate_ick_clksel, 453 .clksel = dsp_irate_ick_clksel,
@@ -501,7 +498,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
501 .name = "core_l3_ck", 498 .name = "core_l3_ck",
502 .ops = &clkops_null, 499 .ops = &clkops_null,
503 .parent = &core_ck, 500 .parent = &core_ck,
504 .flags = DELAYED_APP,
505 .clkdm_name = "core_l3_clkdm", 501 .clkdm_name = "core_l3_clkdm",
506 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 502 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
507 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 503 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -527,7 +523,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
527 .name = "usb_l4_ick", 523 .name = "usb_l4_ick",
528 .ops = &clkops_omap2_dflt_wait, 524 .ops = &clkops_omap2_dflt_wait,
529 .parent = &core_l3_ck, 525 .parent = &core_l3_ck,
530 .flags = DELAYED_APP,
531 .clkdm_name = "core_l4_clkdm", 526 .clkdm_name = "core_l4_clkdm",
532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
533 .enable_bit = OMAP24XX_EN_USB_SHIFT, 528 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -559,14 +554,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */
559 .name = "l4_ck", 554 .name = "l4_ck",
560 .ops = &clkops_null, 555 .ops = &clkops_null,
561 .parent = &core_l3_ck, 556 .parent = &core_l3_ck,
562 .flags = DELAYED_APP,
563 .clkdm_name = "core_l4_clkdm", 557 .clkdm_name = "core_l4_clkdm",
564 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 558 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
565 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 559 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
566 .clksel = l4_clksel, 560 .clksel = l4_clksel,
567 .recalc = &omap2_clksel_recalc, 561 .recalc = &omap2_clksel_recalc,
568 .round_rate = &omap2_clksel_round_rate,
569 .set_rate = &omap2_clksel_set_rate
570}; 562};
571 563
572/* 564/*
@@ -595,7 +587,6 @@ static struct clk ssi_ssr_sst_fck = {
595 .name = "ssi_fck", 587 .name = "ssi_fck",
596 .ops = &clkops_omap2_dflt_wait, 588 .ops = &clkops_omap2_dflt_wait,
597 .parent = &core_ck, 589 .parent = &core_ck,
598 .flags = DELAYED_APP,
599 .clkdm_name = "core_l3_clkdm", 590 .clkdm_name = "core_l3_clkdm",
600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
601 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 592 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -603,8 +594,6 @@ static struct clk ssi_ssr_sst_fck = {
603 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, 594 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
604 .clksel = ssi_ssr_sst_fck_clksel, 595 .clksel = ssi_ssr_sst_fck_clksel,
605 .recalc = &omap2_clksel_recalc, 596 .recalc = &omap2_clksel_recalc,
606 .round_rate = &omap2_clksel_round_rate,
607 .set_rate = &omap2_clksel_set_rate
608}; 597};
609 598
610/* 599/*
@@ -659,7 +648,6 @@ static struct clk gfx_2d_fck = {
659 .name = "gfx_2d_fck", 648 .name = "gfx_2d_fck",
660 .ops = &clkops_omap2_dflt_wait, 649 .ops = &clkops_omap2_dflt_wait,
661 .parent = &core_l3_ck, 650 .parent = &core_l3_ck,
662 .flags = DELAYED_APP,
663 .clkdm_name = "gfx_clkdm", 651 .clkdm_name = "gfx_clkdm",
664 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 652 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
665 .enable_bit = OMAP24XX_EN_2D_SHIFT, 653 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -703,7 +691,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
703 .name = "mdm_ick", 691 .name = "mdm_ick",
704 .ops = &clkops_omap2_dflt_wait, 692 .ops = &clkops_omap2_dflt_wait,
705 .parent = &core_ck, 693 .parent = &core_ck,
706 .flags = DELAYED_APP,
707 .clkdm_name = "mdm_clkdm", 694 .clkdm_name = "mdm_clkdm",
708 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 695 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
709 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 696 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -772,7 +759,6 @@ static struct clk dss1_fck = {
772 .name = "dss1_fck", 759 .name = "dss1_fck",
773 .ops = &clkops_omap2_dflt, 760 .ops = &clkops_omap2_dflt,
774 .parent = &core_ck, /* Core or sys */ 761 .parent = &core_ck, /* Core or sys */
775 .flags = DELAYED_APP,
776 .clkdm_name = "dss_clkdm", 762 .clkdm_name = "dss_clkdm",
777 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
778 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 764 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -781,8 +767,6 @@ static struct clk dss1_fck = {
781 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, 767 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
782 .clksel = dss1_fck_clksel, 768 .clksel = dss1_fck_clksel,
783 .recalc = &omap2_clksel_recalc, 769 .recalc = &omap2_clksel_recalc,
784 .round_rate = &omap2_clksel_round_rate,
785 .set_rate = &omap2_clksel_set_rate
786}; 770};
787 771
788static const struct clksel_rate dss2_fck_sys_rates[] = { 772static const struct clksel_rate dss2_fck_sys_rates[] = {
@@ -805,7 +789,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
805 .name = "dss2_fck", 789 .name = "dss2_fck",
806 .ops = &clkops_omap2_dflt, 790 .ops = &clkops_omap2_dflt,
807 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 791 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
808 .flags = DELAYED_APP,
809 .clkdm_name = "dss_clkdm", 792 .clkdm_name = "dss_clkdm",
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
811 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 794 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,