diff options
author | Sanjeev Premi <premi@ti.com> | 2009-09-03 13:13:58 -0400 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-09-03 13:13:58 -0400 |
commit | 11b66383aa722a3321d2aeec09808c5b140ad396 (patch) | |
tree | c75f53811d72ad9f58b4e57ef9f5a5af56391702 /arch/arm/mach-omap2 | |
parent | 6dda2d4b1306c19e39496e9bb305424d1d547013 (diff) |
OMAP3 clock: Fixed processing of bootarg 'mpurate'
The argument 'mpurate' had no effect on the MPU
frequency. This patch fixes the same.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index cd7819cc0c9e..fafcd32e6907 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/limits.h> | 27 | #include <linux/limits.h> |
28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
29 | 29 | ||
30 | #include <mach/cpu.h> | ||
30 | #include <mach/clock.h> | 31 | #include <mach/clock.h> |
31 | #include <mach/sram.h> | 32 | #include <mach/sram.h> |
32 | #include <asm/div64.h> | 33 | #include <asm/div64.h> |
@@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void) | |||
1067 | return -EINVAL; | 1068 | return -EINVAL; |
1068 | 1069 | ||
1069 | /* REVISIT: not yet ready for 343x */ | 1070 | /* REVISIT: not yet ready for 343x */ |
1070 | #if 0 | 1071 | if (clk_set_rate(&dpll1_ck, mpurate)) |
1071 | if (clk_set_rate(&virt_prcm_set, mpurate)) | 1072 | printk(KERN_ERR "*** Unable to set MPU rate\n"); |
1072 | printk(KERN_ERR "Could not find matching MPU rate\n"); | ||
1073 | #endif | ||
1074 | 1073 | ||
1075 | recalculate_root_clocks(); | 1074 | recalculate_root_clocks(); |
1076 | 1075 | ||
1077 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): " | 1076 | printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): " |
1078 | "%ld.%01ld/%ld/%ld MHz\n", | 1077 | "%ld.%01ld/%ld/%ld MHz\n", |
1079 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | 1078 | (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10), |
1080 | (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ; | 1079 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ; |
1080 | |||
1081 | calibrate_delay(); | ||
1081 | 1082 | ||
1082 | return 0; | 1083 | return 0; |
1083 | } | 1084 | } |
@@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void) | |||
1136 | 1137 | ||
1137 | recalculate_root_clocks(); | 1138 | recalculate_root_clocks(); |
1138 | 1139 | ||
1139 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " | 1140 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " |
1140 | "%ld.%01ld/%ld/%ld MHz\n", | 1141 | "%ld.%01ld/%ld/%ld MHz\n", |
1141 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | 1142 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, |
1142 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | 1143 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); |