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authorLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-07-02 18:04:12 -0400
commita8c4c20dfa8b28a3c99e33c639d9c2ea5657741e (patch)
tree887b64d29b5a46d9ab2ca1267d8a2f05b5845561 /arch/arm/mach-omap2
parent168d04b3b4de7723eb73b3cffc9cb75224e0f393 (diff)
parent2dc7667b9d0674db6572723356fe3857031101a4 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig1
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/clock.c37
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/devices.c46
-rw-r--r--arch/arm/mach-omap2/gpmc.c209
-rw-r--r--arch/arm/mach-omap2/io.c2
-rw-r--r--arch/arm/mach-omap2/mux.c38
-rw-r--r--arch/arm/mach-omap2/pm-domain.c300
-rw-r--r--arch/arm/mach-omap2/pm.c271
-rw-r--r--arch/arm/mach-omap2/timer-gp.c86
11 files changed, 900 insertions, 97 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 537dd2e6d380..aab97ccf1e63 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -8,6 +8,7 @@ config ARCH_OMAP24XX
8config ARCH_OMAP2420 8config ARCH_OMAP2420
9 bool "OMAP2420 support" 9 bool "OMAP2420 support"
10 depends on ARCH_OMAP24XX 10 depends on ARCH_OMAP24XX
11 select OMAP_DM_TIMER
11 12
12comment "OMAP Board Type" 13comment "OMAP Board Type"
13 depends on ARCH_OMAP2 14 depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 111eaa64258f..266d88e77bdc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,12 +3,13 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o serial.o 6obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
7 serial.o gpmc.o
7 8
8obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o 9obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
9 10
10# Power Management 11# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o 12obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
12 13
13# Specific board support 14# Specific board support
14obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o 15obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 7edf0f69da1e..d1b648a4efbf 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -659,26 +659,35 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
659 659
660 /* Isolate control register */ 660 /* Isolate control register */
661 div_sel = (SRC_RATE_SEL_MASK & clk->flags); 661 div_sel = (SRC_RATE_SEL_MASK & clk->flags);
662 div_off = clk->src_offset; 662 div_off = clk->rate_offset;
663 663
664 validrate = omap2_clksel_round_rate(clk, rate, &new_div); 664 validrate = omap2_clksel_round_rate(clk, rate, &new_div);
665 if(validrate != rate) 665 if (validrate != rate)
666 return(ret); 666 return(ret);
667 667
668 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 668 field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
669 if (div_sel == 0) 669 if (div_sel == 0)
670 return ret; 670 return ret;
671 671
672 if(clk->flags & CM_SYSCLKOUT_SEL1){ 672 if (clk->flags & CM_SYSCLKOUT_SEL1) {
673 switch(new_div){ 673 switch (new_div) {
674 case 16: field_val = 4; break; 674 case 16:
675 case 8: field_val = 3; break; 675 field_val = 4;
676 case 4: field_val = 2; break; 676 break;
677 case 2: field_val = 1; break; 677 case 8:
678 case 1: field_val = 0; break; 678 field_val = 3;
679 break;
680 case 4:
681 field_val = 2;
682 break;
683 case 2:
684 field_val = 1;
685 break;
686 case 1:
687 field_val = 0;
688 break;
679 } 689 }
680 } 690 } else
681 else
682 field_val = new_div; 691 field_val = new_div;
683 692
684 reg = (void __iomem *)div_sel; 693 reg = (void __iomem *)div_sel;
@@ -743,7 +752,7 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
743 val = 0x2; 752 val = 0x2;
744 break; 753 break;
745 case CM_WKUP_SEL1: 754 case CM_WKUP_SEL1:
746 src_reg_addr = (u32)&CM_CLKSEL2_CORE; 755 src_reg_addr = (u32)&CM_CLKSEL_WKUP;
747 mask = 0x3; 756 mask = 0x3;
748 if (src_clk == &func_32k_ck) 757 if (src_clk == &func_32k_ck)
749 val = 0x0; 758 val = 0x0;
@@ -783,9 +792,9 @@ static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset,
783 val = 0; 792 val = 0;
784 if (src_clk == &sys_ck) 793 if (src_clk == &sys_ck)
785 val = 1; 794 val = 1;
786 if (src_clk == &func_54m_ck)
787 val = 2;
788 if (src_clk == &func_96m_ck) 795 if (src_clk == &func_96m_ck)
796 val = 2;
797 if (src_clk == &func_54m_ck)
789 val = 3; 798 val = 3;
790 break; 799 break;
791 } 800 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 6c78d471fab7..2781dfbc5164 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1062,7 +1062,7 @@ static struct clk gpt2_ick = {
1062 .parent = &l4_ck, 1062 .parent = &l4_ck,
1063 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1063 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1064 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */ 1064 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1065 .enable_bit = 0, 1065 .enable_bit = 4,
1066 .recalc = &omap2_followparent_recalc, 1066 .recalc = &omap2_followparent_recalc,
1067}; 1067};
1068 1068
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4842ffe26705..aa4322451e8b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -104,6 +104,51 @@ static inline void omap_init_sti(void)
104static inline void omap_init_sti(void) {} 104static inline void omap_init_sti(void) {}
105#endif 105#endif
106 106
107#if defined(CONFIG_SPI_OMAP24XX)
108
109#include <asm/arch/mcspi.h>
110
111#define OMAP2_MCSPI1_BASE 0x48098000
112#define OMAP2_MCSPI2_BASE 0x4809a000
113
114/* FIXME: use resources instead */
115
116static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
117 .base = io_p2v(OMAP2_MCSPI1_BASE),
118 .num_cs = 4,
119};
120
121struct platform_device omap2_mcspi1 = {
122 .name = "omap2_mcspi",
123 .id = 1,
124 .dev = {
125 .platform_data = &omap2_mcspi1_config,
126 },
127};
128
129static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
130 .base = io_p2v(OMAP2_MCSPI2_BASE),
131 .num_cs = 2,
132};
133
134struct platform_device omap2_mcspi2 = {
135 .name = "omap2_mcspi",
136 .id = 2,
137 .dev = {
138 .platform_data = &omap2_mcspi2_config,
139 },
140};
141
142static void omap_init_mcspi(void)
143{
144 platform_device_register(&omap2_mcspi1);
145 platform_device_register(&omap2_mcspi2);
146}
147
148#else
149static inline void omap_init_mcspi(void) {}
150#endif
151
107/*-------------------------------------------------------------------------*/ 152/*-------------------------------------------------------------------------*/
108 153
109static int __init omap2_init_devices(void) 154static int __init omap2_init_devices(void)
@@ -112,6 +157,7 @@ static int __init omap2_init_devices(void)
112 * in alphabetical order so they're easier to sort through. 157 * in alphabetical order so they're easier to sort through.
113 */ 158 */
114 omap_init_i2c(); 159 omap_init_i2c();
160 omap_init_mcspi();
115 omap_init_sti(); 161 omap_init_sti();
116 162
117 return 0; 163 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
new file mode 100644
index 000000000000..c7a48f921fef
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -0,0 +1,209 @@
1/*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16
17#include <asm/io.h>
18#include <asm/arch/gpmc.h>
19
20#undef DEBUG
21
22#define GPMC_BASE 0x6800a000
23#define GPMC_REVISION 0x00
24#define GPMC_SYSCONFIG 0x10
25#define GPMC_SYSSTATUS 0x14
26#define GPMC_IRQSTATUS 0x18
27#define GPMC_IRQENABLE 0x1c
28#define GPMC_TIMEOUT_CONTROL 0x40
29#define GPMC_ERR_ADDRESS 0x44
30#define GPMC_ERR_TYPE 0x48
31#define GPMC_CONFIG 0x50
32#define GPMC_STATUS 0x54
33#define GPMC_PREFETCH_CONFIG1 0x1e0
34#define GPMC_PREFETCH_CONFIG2 0x1e4
35#define GPMC_PREFETCH_CONTROL 0x1e8
36#define GPMC_PREFETCH_STATUS 0x1f0
37#define GPMC_ECC_CONFIG 0x1f4
38#define GPMC_ECC_CONTROL 0x1f8
39#define GPMC_ECC_SIZE_CONFIG 0x1fc
40
41#define GPMC_CS0 0x60
42#define GPMC_CS_SIZE 0x30
43
44static void __iomem *gpmc_base =
45 (void __iomem *) IO_ADDRESS(GPMC_BASE);
46static void __iomem *gpmc_cs_base =
47 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
48
49static struct clk *gpmc_l3_clk;
50
51static void gpmc_write_reg(int idx, u32 val)
52{
53 __raw_writel(val, gpmc_base + idx);
54}
55
56static u32 gpmc_read_reg(int idx)
57{
58 return __raw_readl(gpmc_base + idx);
59}
60
61void gpmc_cs_write_reg(int cs, int idx, u32 val)
62{
63 void __iomem *reg_addr;
64
65 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
66 __raw_writel(val, reg_addr);
67}
68
69u32 gpmc_cs_read_reg(int cs, int idx)
70{
71 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
72}
73
74/* TODO: Add support for gpmc_fck to clock framework and use it */
75static unsigned long gpmc_get_fclk_period(void)
76{
77 /* In picoseconds */
78 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
79}
80
81unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
82{
83 unsigned long tick_ps;
84
85 /* Calculate in picosecs to yield more exact results */
86 tick_ps = gpmc_get_fclk_period();
87
88 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
89}
90
91#ifdef DEBUG
92static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
93 int time, const char *name)
94#else
95static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
96 int time)
97#endif
98{
99 u32 l;
100 int ticks, mask, nr_bits;
101
102 if (time == 0)
103 ticks = 0;
104 else
105 ticks = gpmc_ns_to_ticks(time);
106 nr_bits = end_bit - st_bit + 1;
107 if (ticks >= 1 << nr_bits)
108 return -1;
109
110 mask = (1 << nr_bits) - 1;
111 l = gpmc_cs_read_reg(cs, reg);
112#ifdef DEBUG
113 printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
114 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
115 (l >> st_bit) & mask);
116#endif
117 l &= ~(mask << st_bit);
118 l |= ticks << st_bit;
119 gpmc_cs_write_reg(cs, reg, l);
120
121 return 0;
122}
123
124#ifdef DEBUG
125#define GPMC_SET_ONE(reg, st, end, field) \
126 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
127 t->field, #field) < 0) \
128 return -1
129#else
130#define GPMC_SET_ONE(reg, st, end, field) \
131 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
132 return -1
133#endif
134
135int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
136{
137 int div;
138 u32 l;
139
140 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
141 div = l / gpmc_get_fclk_period();
142 if (div > 4)
143 return -1;
144 if (div < 0)
145 div = 1;
146
147 return div;
148}
149
150int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
151{
152 int div;
153 u32 l;
154
155 div = gpmc_cs_calc_divider(cs, t->sync_clk);
156 if (div < 0)
157 return -1;
158
159 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
160 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
161 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
162
163 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
164 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
165 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
166
167 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
168 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
169 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
170 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
171
172 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
173 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
174 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
175
176 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
177
178#ifdef DEBUG
179 printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
180 cs, gpmc_get_fclk_period(), div);
181#endif
182
183 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
184 l &= ~0x03;
185 l |= (div - 1);
186
187 return 0;
188}
189
190unsigned long gpmc_cs_get_base_addr(int cs)
191{
192 return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24;
193}
194
195void __init gpmc_init(void)
196{
197 u32 l;
198
199 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
200 BUG_ON(IS_ERR(gpmc_l3_clk));
201
202 l = gpmc_read_reg(GPMC_REVISION);
203 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
204 /* Set smart idle mode and automatic L3 clock gating */
205 l = gpmc_read_reg(GPMC_SYSCONFIG);
206 l &= 0x03 << 3;
207 l |= (0x02 << 3) | (1 << 0);
208 gpmc_write_reg(GPMC_SYSCONFIG, l);
209}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 20dd6e74e91d..a0728c33e5d9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -26,6 +26,7 @@
26extern void omap_sram_init(void); 26extern void omap_sram_init(void);
27extern int omap2_clk_init(void); 27extern int omap2_clk_init(void);
28extern void omap2_check_revision(void); 28extern void omap2_check_revision(void);
29extern void gpmc_init(void);
29 30
30/* 31/*
31 * The machine specific code may provide the extra mapping besides the 32 * The machine specific code may provide the extra mapping besides the
@@ -66,4 +67,5 @@ void __init omap2_init_common_hw(void)
66{ 67{
67 omap2_mux_init(); 68 omap2_mux_init();
68 omap2_clk_init(); 69 omap2_clk_init();
70 gpmc_init();
69} 71}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 4c5f2c04883e..60ef084faffd 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -52,6 +52,12 @@ MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
52/* 24xx clocks */ 52/* 24xx clocks */
53MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1) 53MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
54 54
55/* 24xx GPMC wait pin monitoring */
56MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
57MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
58MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
59MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
60
55/* 24xx McBSP */ 61/* 24xx McBSP */
56MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1) 62MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
57MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1) 63MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
@@ -59,18 +65,38 @@ MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
59MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1) 65MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
60 66
61/* 24xx GPIO */ 67/* 24xx GPIO */
62MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1) 68MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
63MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1) 69MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
64MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1) 70MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
65MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1) 71MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
66MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1) 72MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
67MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1) 73MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
68MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1) 74MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
69MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1) 75MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
70MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1) 76MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
71MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1) 77MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
72MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1) 78MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
73 79
80/* 242x DBG GPIO */
81MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
82MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
83MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
84MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
85MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
86MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
87MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
88MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
89MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
90MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
91
92/* 24xx external DMA requests */
93MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
94MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
95MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
96MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
97MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
98MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
99
74/* TSC IRQ */ 100/* TSC IRQ */
75MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1) 101MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
76 102
diff --git a/arch/arm/mach-omap2/pm-domain.c b/arch/arm/mach-omap2/pm-domain.c
new file mode 100644
index 000000000000..5e20e740cde5
--- /dev/null
+++ b/arch/arm/mach-omap2/pm-domain.c
@@ -0,0 +1,300 @@
1/*
2 * linux/arch/arm/mach-omap2/pm-domain.c
3 *
4 * Power domain functions for OMAP2
5 *
6 * Copyright (C) 2006 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
8 *
9 * Some code based on earlier OMAP2 sample PM code
10 * Copyright (C) 2005 Texas Instruments, Inc.
11 * Richard Woodruff <r-woodruff2@ti.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22
23#include <asm/io.h>
24
25#include "prcm-regs.h"
26
27/* Power domain offsets */
28#define PM_MPU_OFFSET 0x100
29#define PM_CORE_OFFSET 0x200
30#define PM_GFX_OFFSET 0x300
31#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
32#define PM_PLL_OFFSET 0x500 /* Autoidle only */
33#define PM_DSP_OFFSET 0x800
34#define PM_MDM_OFFSET 0xc00
35
36/* Power domain wake-up dependency control register */
37#define PM_WKDEP_OFFSET 0xc8
38#define EN_MDM (1 << 5)
39#define EN_WKUP (1 << 4)
40#define EN_GFX (1 << 3)
41#define EN_DSP (1 << 2)
42#define EN_MPU (1 << 1)
43#define EN_CORE (1 << 0)
44
45/* Core power domain state transition control register */
46#define PM_PWSTCTRL_OFFSET 0xe0
47#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
48#define MEM4RETSTATE (1 << 6)
49#define MEM3RETSTATE (1 << 5)
50#define MEM2RETSTATE (1 << 4)
51#define MEM1RETSTATE (1 << 3)
52#define LOGICRETSTATE (1 << 2) /* Logic is retained */
53#define POWERSTATE_OFF 0x3
54#define POWERSTATE_RETENTION 0x1
55#define POWERSTATE_ON 0x0
56
57/* Power domain state register */
58#define PM_PWSTST_OFFSET 0xe4
59
60/* Hardware supervised state transition control register */
61#define CM_CLKSTCTRL_OFFSET 0x48
62#define AUTOSTAT_MPU (1 << 0) /* MPU */
63#define AUTOSTAT_DSS (1 << 2) /* Core */
64#define AUTOSTAT_L4 (1 << 1) /* Core */
65#define AUTOSTAT_L3 (1 << 0) /* Core */
66#define AUTOSTAT_GFX (1 << 0) /* GFX */
67#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
68#define AUTOSTAT_DSP (1 << 0) /* DSP */
69#define AUTOSTAT_MDM (1 << 0) /* MDM */
70
71/* Automatic control of interface clock idling */
72#define CM_AUTOIDLE1_OFFSET 0x30
73#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
74#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
75#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
76#define AUTO_54M(x) (((x) & 0x3) << 6)
77#define AUTO_96M(x) (((x) & 0x3) << 2)
78#define AUTO_DPLL(x) (((x) & 0x3) << 0)
79#define AUTO_STOPPED 0x3
80#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
81#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
82#define AUTO_DISABLED 0x0
83
84/* Voltage control PRCM_VOLTCTRL bits */
85#define AUTO_EXTVOLT (1 << 15)
86#define FORCE_EXTVOLT (1 << 14)
87#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
88#define MEMRETCTRL (1 << 8)
89#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
90#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
91
92#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
93#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
94#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
95
96static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
97{
98 return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
99}
100
101static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
102{
103 prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
104}
105
106static u32 pmdomain_get_powerstate(int domain_offset)
107{
108 return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
109}
110
111static void pmdomain_set_powerstate(u32 state, int domain_offset)
112{
113 prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
114}
115
116static u32 pmdomain_get_clock_autocontrol(int domain_offset)
117{
118 return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
119}
120
121static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
122{
123 prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
124}
125
126static u32 pmdomain_get_clock_autoidle1(int domain_offset)
127{
128 return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
129}
130
131/* Core domain only */
132static u32 pmdomain_get_clock_autoidle2(int domain_offset)
133{
134 return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
135}
136
137/* Core domain only */
138static u32 pmdomain_get_clock_autoidle3(int domain_offset)
139{
140 return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
141}
142
143/* Core domain only */
144static u32 pmdomain_get_clock_autoidle4(int domain_offset)
145{
146 return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
147}
148
149static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
150{
151 prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
152}
153
154/* Core domain only */
155static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
156{
157 prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
158}
159
160/* Core domain only */
161static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
162{
163 prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
164}
165
166/* Core domain only */
167static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
168{
169 prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
170}
171
172/*
173 * Configures power management domains to idle clocks automatically.
174 */
175void pmdomain_set_autoidle(void)
176{
177 u32 val;
178
179 /* Set PLL auto stop for 54M, 96M & DPLL */
180 pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
181 AUTO_96M(AUTO_STOPPED) |
182 AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
183
184 /* External clock input control
185 * REVISIT: Should this be in clock framework?
186 */
187 PRCM_CLKSRC_CTRL |= (0x3 << 3);
188
189 /* Configure number of 32KHz clock cycles for sys_clk */
190 PRCM_CLKSSETUP = 0x00ff;
191
192 /* Configure automatic voltage transition */
193 PRCM_VOLTSETUP = 0;
194 val = PRCM_VOLTCTRL;
195 val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
196 val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
197 PRCM_VOLTCTRL = val;
198
199 /* Disable emulation tools functional clock */
200 PRCM_CLKEMUL_CTRL = 0x0;
201
202 /* Set core memory retention state */
203 val = pmdomain_get_powerstate(PM_CORE_OFFSET);
204 if (cpu_is_omap2420()) {
205 val &= ~(0x7 << 3);
206 val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
207 } else {
208 val &= ~(0xf << 3);
209 val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
210 MEM1RETSTATE);
211 }
212 pmdomain_set_powerstate(val, PM_CORE_OFFSET);
213
214 /* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
215 val = SMS_SYSCONFIG;
216 val &= ~(0x3 << 3);
217 val |= (0x2 << 3) | (1 << 0);
218 SMS_SYSCONFIG |= val;
219
220 val = SDRC_SYSCONFIG;
221 val &= ~(0x3 << 3);
222 val |= (0x2 << 3);
223 SDRC_SYSCONFIG = val;
224
225 /* Configure L3 interface for smart idle.
226 * REVISIT: Enable autoidle bit0 ?
227 */
228 val = GPMC_SYSCONFIG;
229 val &= ~(0x3 << 3);
230 val |= (0x2 << 3) | (1 << 0);
231 GPMC_SYSCONFIG = val;
232
233 pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
234 PM_MPU_OFFSET);
235 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
236 if (!cpu_is_omap2420())
237 pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
238
239 /* Assume suspend function has saved the state for DSP and GFX */
240 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
241 pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
242
243#if 0
244 /* REVISIT: Internal USB needs special handling */
245 force_standby_usb();
246 if (cpu_is_omap2430())
247 force_hsmmc();
248 sdram_self_refresh_on_idle_req(1);
249#endif
250
251 /* Enable clock auto control for all domains.
252 * Note that CORE domain includes also DSS, L4 & L3.
253 */
254 pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
255 pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
256 pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
257 PM_CORE_OFFSET);
258 if (cpu_is_omap2420())
259 pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
260 PM_DSP_OFFSET);
261 else {
262 pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
263 pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
264 }
265
266 /* Enable clock autoidle for all domains */
267 pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
268 if (cpu_is_omap2420()) {
269 pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
270 pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
271 pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
272 } else {
273 pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
274 pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
275 pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
276 pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
277 }
278 pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
279 pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
280}
281
282/*
283 * Initializes power domains by removing wake-up dependencies and powering
284 * down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
285 * must re-enable DSP and GFX when used.
286 */
287void __init pmdomain_init(void)
288{
289 /* Remove all domain wakeup dependencies */
290 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
291 pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
292 pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
293 pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
294 if (cpu_is_omap2430())
295 pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
296
297 /* Power down DSP and GFX */
298 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
299 pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
300}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 562168fa2b16..d7eee99b7e3f 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -23,6 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/sysfs.h> 24#include <linux/sysfs.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/delay.h>
26 27
27#include <asm/io.h> 28#include <asm/io.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
@@ -36,11 +37,18 @@
36#include <asm/arch/sram.h> 37#include <asm/arch/sram.h>
37#include <asm/arch/pm.h> 38#include <asm/arch/pm.h>
38 39
40#include "prcm-regs.h"
41
39static struct clk *vclk; 42static struct clk *vclk;
40static void (*omap2_sram_idle)(void); 43static void (*omap2_sram_idle)(void);
41static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev); 44static void (*omap2_sram_suspend)(int dllctrl, int cpu_rev);
42static void (*saved_idle)(void); 45static void (*saved_idle)(void);
43 46
47extern void __init pmdomain_init(void);
48extern void pmdomain_set_autoidle(void);
49
50static unsigned int omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_SIZE];
51
44void omap2_pm_idle(void) 52void omap2_pm_idle(void)
45{ 53{
46 local_irq_disable(); 54 local_irq_disable();
@@ -87,23 +95,272 @@ static int omap2_pm_prepare(suspend_state_t state)
87 return error; 95 return error;
88} 96}
89 97
98#define INT0_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK1) | \
99 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK2) | \
100 OMAP_IRQ_BIT(INT_24XX_GPIO_BANK3))
101
102#define INT1_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_GPIO_BANK4))
103
104#define INT2_WAKE_MASK (OMAP_IRQ_BIT(INT_24XX_UART1_IRQ) | \
105 OMAP_IRQ_BIT(INT_24XX_UART2_IRQ) | \
106 OMAP_IRQ_BIT(INT_24XX_UART3_IRQ))
107
108#define preg(reg) printk("%s\t(0x%p):\t0x%08x\n", #reg, &reg, reg);
109
110static void omap2_pm_debug(char * desc)
111{
112 printk("%s:\n", desc);
113
114 preg(CM_CLKSTCTRL_MPU);
115 preg(CM_CLKSTCTRL_CORE);
116 preg(CM_CLKSTCTRL_GFX);
117 preg(CM_CLKSTCTRL_DSP);
118 preg(CM_CLKSTCTRL_MDM);
119
120 preg(PM_PWSTCTRL_MPU);
121 preg(PM_PWSTCTRL_CORE);
122 preg(PM_PWSTCTRL_GFX);
123 preg(PM_PWSTCTRL_DSP);
124 preg(PM_PWSTCTRL_MDM);
125
126 preg(PM_PWSTST_MPU);
127 preg(PM_PWSTST_CORE);
128 preg(PM_PWSTST_GFX);
129 preg(PM_PWSTST_DSP);
130 preg(PM_PWSTST_MDM);
131
132 preg(CM_AUTOIDLE1_CORE);
133 preg(CM_AUTOIDLE2_CORE);
134 preg(CM_AUTOIDLE3_CORE);
135 preg(CM_AUTOIDLE4_CORE);
136 preg(CM_AUTOIDLE_WKUP);
137 preg(CM_AUTOIDLE_PLL);
138 preg(CM_AUTOIDLE_DSP);
139 preg(CM_AUTOIDLE_MDM);
140
141 preg(CM_ICLKEN1_CORE);
142 preg(CM_ICLKEN2_CORE);
143 preg(CM_ICLKEN3_CORE);
144 preg(CM_ICLKEN4_CORE);
145 preg(CM_ICLKEN_GFX);
146 preg(CM_ICLKEN_WKUP);
147 preg(CM_ICLKEN_DSP);
148 preg(CM_ICLKEN_MDM);
149
150 preg(CM_IDLEST1_CORE);
151 preg(CM_IDLEST2_CORE);
152 preg(CM_IDLEST3_CORE);
153 preg(CM_IDLEST4_CORE);
154 preg(CM_IDLEST_GFX);
155 preg(CM_IDLEST_WKUP);
156 preg(CM_IDLEST_CKGEN);
157 preg(CM_IDLEST_DSP);
158 preg(CM_IDLEST_MDM);
159
160 preg(RM_RSTST_MPU);
161 preg(RM_RSTST_GFX);
162 preg(RM_RSTST_WKUP);
163 preg(RM_RSTST_DSP);
164 preg(RM_RSTST_MDM);
165
166 preg(PM_WKDEP_MPU);
167 preg(PM_WKDEP_CORE);
168 preg(PM_WKDEP_GFX);
169 preg(PM_WKDEP_DSP);
170 preg(PM_WKDEP_MDM);
171
172 preg(CM_FCLKEN_WKUP);
173 preg(CM_ICLKEN_WKUP);
174 preg(CM_IDLEST_WKUP);
175 preg(CM_AUTOIDLE_WKUP);
176 preg(CM_CLKSEL_WKUP);
177
178 preg(PM_WKEN_WKUP);
179 preg(PM_WKST_WKUP);
180}
181
182static inline void omap2_pm_save_registers(void)
183{
184 /* Save interrupt registers */
185 OMAP24XX_SAVE(INTC_MIR0);
186 OMAP24XX_SAVE(INTC_MIR1);
187 OMAP24XX_SAVE(INTC_MIR2);
188
189 /* Save power control registers */
190 OMAP24XX_SAVE(CM_CLKSTCTRL_MPU);
191 OMAP24XX_SAVE(CM_CLKSTCTRL_CORE);
192 OMAP24XX_SAVE(CM_CLKSTCTRL_GFX);
193 OMAP24XX_SAVE(CM_CLKSTCTRL_DSP);
194 OMAP24XX_SAVE(CM_CLKSTCTRL_MDM);
195
196 /* Save power state registers */
197 OMAP24XX_SAVE(PM_PWSTCTRL_MPU);
198 OMAP24XX_SAVE(PM_PWSTCTRL_CORE);
199 OMAP24XX_SAVE(PM_PWSTCTRL_GFX);
200 OMAP24XX_SAVE(PM_PWSTCTRL_DSP);
201 OMAP24XX_SAVE(PM_PWSTCTRL_MDM);
202
203 /* Save autoidle registers */
204 OMAP24XX_SAVE(CM_AUTOIDLE1_CORE);
205 OMAP24XX_SAVE(CM_AUTOIDLE2_CORE);
206 OMAP24XX_SAVE(CM_AUTOIDLE3_CORE);
207 OMAP24XX_SAVE(CM_AUTOIDLE4_CORE);
208 OMAP24XX_SAVE(CM_AUTOIDLE_WKUP);
209 OMAP24XX_SAVE(CM_AUTOIDLE_PLL);
210 OMAP24XX_SAVE(CM_AUTOIDLE_DSP);
211 OMAP24XX_SAVE(CM_AUTOIDLE_MDM);
212
213 /* Save idle state registers */
214 OMAP24XX_SAVE(CM_IDLEST1_CORE);
215 OMAP24XX_SAVE(CM_IDLEST2_CORE);
216 OMAP24XX_SAVE(CM_IDLEST3_CORE);
217 OMAP24XX_SAVE(CM_IDLEST4_CORE);
218 OMAP24XX_SAVE(CM_IDLEST_GFX);
219 OMAP24XX_SAVE(CM_IDLEST_WKUP);
220 OMAP24XX_SAVE(CM_IDLEST_CKGEN);
221 OMAP24XX_SAVE(CM_IDLEST_DSP);
222 OMAP24XX_SAVE(CM_IDLEST_MDM);
223
224 /* Save clock registers */
225 OMAP24XX_SAVE(CM_FCLKEN1_CORE);
226 OMAP24XX_SAVE(CM_FCLKEN2_CORE);
227 OMAP24XX_SAVE(CM_ICLKEN1_CORE);
228 OMAP24XX_SAVE(CM_ICLKEN2_CORE);
229 OMAP24XX_SAVE(CM_ICLKEN3_CORE);
230 OMAP24XX_SAVE(CM_ICLKEN4_CORE);
231}
232
233static inline void omap2_pm_restore_registers(void)
234{
235 /* Restore clock state registers */
236 OMAP24XX_RESTORE(CM_CLKSTCTRL_MPU);
237 OMAP24XX_RESTORE(CM_CLKSTCTRL_CORE);
238 OMAP24XX_RESTORE(CM_CLKSTCTRL_GFX);
239 OMAP24XX_RESTORE(CM_CLKSTCTRL_DSP);
240 OMAP24XX_RESTORE(CM_CLKSTCTRL_MDM);
241
242 /* Restore power state registers */
243 OMAP24XX_RESTORE(PM_PWSTCTRL_MPU);
244 OMAP24XX_RESTORE(PM_PWSTCTRL_CORE);
245 OMAP24XX_RESTORE(PM_PWSTCTRL_GFX);
246 OMAP24XX_RESTORE(PM_PWSTCTRL_DSP);
247 OMAP24XX_RESTORE(PM_PWSTCTRL_MDM);
248
249 /* Restore idle state registers */
250 OMAP24XX_RESTORE(CM_IDLEST1_CORE);
251 OMAP24XX_RESTORE(CM_IDLEST2_CORE);
252 OMAP24XX_RESTORE(CM_IDLEST3_CORE);
253 OMAP24XX_RESTORE(CM_IDLEST4_CORE);
254 OMAP24XX_RESTORE(CM_IDLEST_GFX);
255 OMAP24XX_RESTORE(CM_IDLEST_WKUP);
256 OMAP24XX_RESTORE(CM_IDLEST_CKGEN);
257 OMAP24XX_RESTORE(CM_IDLEST_DSP);
258 OMAP24XX_RESTORE(CM_IDLEST_MDM);
259
260 /* Restore autoidle registers */
261 OMAP24XX_RESTORE(CM_AUTOIDLE1_CORE);
262 OMAP24XX_RESTORE(CM_AUTOIDLE2_CORE);
263 OMAP24XX_RESTORE(CM_AUTOIDLE3_CORE);
264 OMAP24XX_RESTORE(CM_AUTOIDLE4_CORE);
265 OMAP24XX_RESTORE(CM_AUTOIDLE_WKUP);
266 OMAP24XX_RESTORE(CM_AUTOIDLE_PLL);
267 OMAP24XX_RESTORE(CM_AUTOIDLE_DSP);
268 OMAP24XX_RESTORE(CM_AUTOIDLE_MDM);
269
270 /* Restore clock registers */
271 OMAP24XX_RESTORE(CM_FCLKEN1_CORE);
272 OMAP24XX_RESTORE(CM_FCLKEN2_CORE);
273 OMAP24XX_RESTORE(CM_ICLKEN1_CORE);
274 OMAP24XX_RESTORE(CM_ICLKEN2_CORE);
275 OMAP24XX_RESTORE(CM_ICLKEN3_CORE);
276 OMAP24XX_RESTORE(CM_ICLKEN4_CORE);
277
278 /* REVISIT: Clear interrupts here */
279
280 /* Restore interrupt registers */
281 OMAP24XX_RESTORE(INTC_MIR0);
282 OMAP24XX_RESTORE(INTC_MIR1);
283 OMAP24XX_RESTORE(INTC_MIR2);
284}
285
286static int omap2_pm_suspend(void)
287{
288 int processor_type = 0;
289
290 /* REVISIT: 0x21 or 0x26? */
291 if (cpu_is_omap2420())
292 processor_type = 0x21;
293
294 if (!processor_type)
295 return -ENOTSUPP;
296
297 local_irq_disable();
298 local_fiq_disable();
299
300 omap2_pm_save_registers();
301
302 /* Disable interrupts except for the wake events */
303 INTC_MIR_SET0 = 0xffffffff & ~INT0_WAKE_MASK;
304 INTC_MIR_SET1 = 0xffffffff & ~INT1_WAKE_MASK;
305 INTC_MIR_SET2 = 0xffffffff & ~INT2_WAKE_MASK;
306
307 pmdomain_set_autoidle();
308
309 /* Clear old wake-up events */
310 PM_WKST1_CORE = 0;
311 PM_WKST2_CORE = 0;
312 PM_WKST_WKUP = 0;
313
314 /* Enable wake-up events */
315 PM_WKEN1_CORE = (1 << 22) | (1 << 21); /* UART1 & 2 */
316 PM_WKEN2_CORE = (1 << 2); /* UART3 */
317 PM_WKEN_WKUP = (1 << 2) | (1 << 0); /* GPIO & GPT1 */
318
319 /* Disable clocks except for CM_ICLKEN2_CORE. It gets disabled
320 * in the SRAM suspend code */
321 CM_FCLKEN1_CORE = 0;
322 CM_FCLKEN2_CORE = 0;
323 CM_ICLKEN1_CORE = 0;
324 CM_ICLKEN3_CORE = 0;
325 CM_ICLKEN4_CORE = 0;
326
327 omap2_pm_debug("Status before suspend");
328
329 /* Must wait for serial buffers to clear */
330 mdelay(200);
331
332 /* Jump to SRAM suspend code
333 * REVISIT: When is this SDRC_DLLB_CTRL?
334 */
335 omap2_sram_suspend(SDRC_DLLA_CTRL, processor_type);
336
337 /* Back from sleep */
338 omap2_pm_restore_registers();
339
340 local_fiq_enable();
341 local_irq_enable();
342
343 return 0;
344}
345
90static int omap2_pm_enter(suspend_state_t state) 346static int omap2_pm_enter(suspend_state_t state)
91{ 347{
348 int ret = 0;
349
92 switch (state) 350 switch (state)
93 { 351 {
94 case PM_SUSPEND_STANDBY: 352 case PM_SUSPEND_STANDBY:
95 case PM_SUSPEND_MEM: 353 case PM_SUSPEND_MEM:
96 /* FIXME: Add suspend */ 354 ret = omap2_pm_suspend();
97 break; 355 break;
98
99 case PM_SUSPEND_DISK: 356 case PM_SUSPEND_DISK:
100 return -ENOTSUPP; 357 ret = -ENOTSUPP;
101 358 break;
102 default: 359 default:
103 return -EINVAL; 360 ret = -EINVAL;
104 } 361 }
105 362
106 return 0; 363 return ret;
107} 364}
108 365
109static int omap2_pm_finish(suspend_state_t state) 366static int omap2_pm_finish(suspend_state_t state)
@@ -143,6 +400,8 @@ int __init omap2_pm_init(void)
143 pm_set_ops(&omap_pm_ops); 400 pm_set_ops(&omap_pm_ops);
144 pm_idle = omap2_pm_idle; 401 pm_idle = omap2_pm_idle;
145 402
403 pmdomain_init();
404
146 return 0; 405 return 0;
147} 406}
148 407
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 1d2f5ac2f69b..cf78e6c5a277 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -6,6 +6,7 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * Juha Yrjölä <juha.yrjola@nokia.com> 8 * Juha Yrjölä <juha.yrjola@nokia.com>
9 * OMAP Dual-mode timer framework support by Timo Teras
9 * 10 *
10 * Some parts based off of TI's 24xx code: 11 * Some parts based off of TI's 24xx code:
11 * 12 *
@@ -22,54 +23,18 @@
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
23#include <linux/err.h> 24#include <linux/err.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/delay.h>
25 27
26#include <asm/mach/time.h> 28#include <asm/mach/time.h>
27#include <asm/delay.h> 29#include <asm/arch/dmtimer.h>
28#include <asm/io.h>
29 30
30#define OMAP2_GP_TIMER1_BASE 0x48028000 31static struct omap_dm_timer *gptimer;
31#define OMAP2_GP_TIMER2_BASE 0x4802a000
32#define OMAP2_GP_TIMER3_BASE 0x48078000
33#define OMAP2_GP_TIMER4_BASE 0x4807a000
34 32
35#define GP_TIMER_TIDR 0x00 33static inline void omap2_gp_timer_start(unsigned long load_val)
36#define GP_TIMER_TISR 0x18
37#define GP_TIMER_TIER 0x1c
38#define GP_TIMER_TCLR 0x24
39#define GP_TIMER_TCRR 0x28
40#define GP_TIMER_TLDR 0x2c
41#define GP_TIMER_TSICR 0x40
42
43#define OS_TIMER_NR 1 /* GP timer 2 */
44
45static unsigned long timer_base[] = {
46 IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
47 IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
48 IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
49 IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
50};
51
52static inline unsigned int timer_read_reg(int nr, unsigned int reg)
53{
54 return __raw_readl(timer_base[nr] + reg);
55}
56
57static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
58{
59 __raw_writel(val, timer_base[nr] + reg);
60}
61
62/* Note that we always enable the clock prescale divider bit */
63static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
64{ 34{
65 unsigned int tmp; 35 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
66 36 omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
67 tmp = 0xffffffff - load_val; 37 omap_dm_timer_start(gptimer);
68
69 timer_write_reg(nr, GP_TIMER_TLDR, tmp);
70 timer_write_reg(nr, GP_TIMER_TCRR, tmp);
71 timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
72 timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
73} 38}
74 39
75static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id, 40static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
@@ -77,7 +42,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
77{ 42{
78 write_seqlock(&xtime_lock); 43 write_seqlock(&xtime_lock);
79 44
80 timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1); 45 omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
81 timer_tick(regs); 46 timer_tick(regs);
82 47
83 write_sequnlock(&xtime_lock); 48 write_sequnlock(&xtime_lock);
@@ -87,41 +52,26 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
87 52
88static struct irqaction omap2_gp_timer_irq = { 53static struct irqaction omap2_gp_timer_irq = {
89 .name = "gp timer", 54 .name = "gp timer",
90 .flags = SA_INTERRUPT, 55 .flags = SA_INTERRUPT | SA_TIMER,
91 .handler = omap2_gp_timer_interrupt, 56 .handler = omap2_gp_timer_interrupt,
92}; 57};
93 58
94static void __init omap2_gp_timer_init(void) 59static void __init omap2_gp_timer_init(void)
95{ 60{
96 struct clk * sys_ck; 61 u32 tick_period;
97 u32 tick_period = 120000;
98 u32 l;
99 62
100 /* Reset clock and prescale value */ 63 omap_dm_timer_init();
101 timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0); 64 gptimer = omap_dm_timer_request_specific(1);
65 BUG_ON(gptimer == NULL);
102 66
103 sys_ck = clk_get(NULL, "sys_ck"); 67 omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
104 if (IS_ERR(sys_ck)) 68 tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100;
105 printk(KERN_ERR "Could not get sys_ck\n");
106 else {
107 clk_enable(sys_ck);
108 tick_period = clk_get_rate(sys_ck) / 100;
109 clk_put(sys_ck);
110 }
111
112 tick_period /= 2; /* Minimum prescale divider is 2 */
113 tick_period -= 1; 69 tick_period -= 1;
114 70
115 l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR); 71 setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
116 printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n", 72 omap2_gp_timer_start(tick_period);
117 (l >> 4) & 0x0f, l & 0x0f);
118
119 setup_irq(38, &omap2_gp_timer_irq);
120
121 omap2_gp_timer_start(OS_TIMER_NR, tick_period);
122} 73}
123 74
124struct sys_timer omap_timer = { 75struct sys_timer omap_timer = {
125 .init = omap2_gp_timer_init, 76 .init = omap2_gp_timer_init,
126}; 77};
127
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 21:00:13 -0500