omap: gpmc: enable irq mode in gpmc

add support the irq mode in GPMC.
gpmc_init() function move after omap_init_irq() as it has dependecy on irq.

Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

2 files changed, 42 insertions, 5 deletions

diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..382dea83e4f0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
  */
 #undef DEBUG
 
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/err.h>
@@ -22,6 +23,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -100,6 +102,8 @@ static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
 
+static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+
 static void gpmc_write_reg(int idx, u32 val)
 {
         __raw_writel(val, gpmc_base + idx);
@@ -497,6 +501,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
         u32 regval = 0;
 
         switch (cmd) {
+        case GPMC_ENABLE_IRQ:
+                gpmc_write_reg(GPMC_IRQENABLE, wval);
+                break;
+
         case GPMC_SET_IRQ_STATUS:
                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
                 break;
@@ -678,9 +686,10 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-void __init gpmc_init(void)
+static int __init gpmc_init(void)
 {
-        u32 l;
+        u32 l, irq;
+        int cs, ret = -EINVAL;
         char *ck = NULL;
 
         if (cpu_is_omap24xx()) {
@@ -698,7 +707,7 @@ void __init gpmc_init(void)
         }
 
         if (WARN_ON(!ck))
-                return;
+                return ret;
 
         gpmc_l3_clk = clk_get(NULL, ck);
         if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +732,36 @@ void __init gpmc_init(void)
         l |= (0x02 << 3) | (1 << 0);
         gpmc_write_reg(GPMC_SYSCONFIG, l);
         gpmc_mem_init();
+
+        /* initalize the irq_chained */
+        irq = OMAP_GPMC_IRQ_BASE;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                set_irq_handler(irq, handle_simple_irq);
+                set_irq_flags(irq, IRQF_VALID);
+                irq++;
+        }
+
+        ret = request_irq(INT_34XX_GPMC_IRQ,
+                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+        if (ret)
+                pr_err("gpmc: irq-%d could not claim: err %d\n",
+                                                INT_34XX_GPMC_IRQ, ret);
+        return ret;
+}
+postcore_initcall(gpmc_init);
+
+static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+{
+        u8 cs;
+
+        if (irq != INT_34XX_GPMC_IRQ)
+                return IRQ_HANDLED;
+        /* check cs to invoke the irq */
+        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
+        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
+                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+
+        return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b8b49e4ae928..657f3c84687c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
-#include <plat/gpmc.h>
 #include <plat/serial.h>
 
 #include "clock2xxx.h"
@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
         }
-        gpmc_init();
 
         omap_irq_base_init();
 }