Merge branch 'omap2-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into omap-all

11 files changed, 570 insertions, 218 deletions

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e7cf1b4357ce..800639e7c6a4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -14,7 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420)		+= sram242x.o
 obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
+ifeq ($(CONFIG_PM),y)
+obj-y                                   += pm.o
+obj-$(CONFIG_ARCH_OMAP24XX)             += sleep24xx.o
+endif
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ea55f286f47d..1fb330e0847d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 /* The maximum error between a target DPLL rate and the rounded rate in Hz */
 #define DEFAULT_DPLL_RATE_TOLERANCE     50000
 
+int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7a7f02559075..7cca33e23fd1 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,50 +23,7 @@
 #include <mach/board.h>
 #include <mach/mux.h>
 #include <mach/gpio.h>
-
-#if     defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-
-#define OMAP2_I2C_BASE2         0x48072000
-#define OMAP2_I2C_INT2          57
-
-static struct resource i2c_resources2[] = {
-        {
-                .start          = OMAP2_I2C_BASE2,
-                .end            = OMAP2_I2C_BASE2 + 0x3f,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = OMAP2_I2C_INT2,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device omap_i2c_device2 = {
-        .name           = "i2c_omap",
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(i2c_resources2),
-        .resource       = i2c_resources2,
-};
-
-/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
-static void omap_init_i2c(void)
-{
-        /* REVISIT: Second I2C not in use on H4? */
-        if (machine_is_omap_h4())
-                return;
-
-        if (!cpu_is_omap2430()) {
-                omap_cfg_reg(J15_24XX_I2C2_SCL);
-                omap_cfg_reg(H19_24XX_I2C2_SDA);
-        }
-        (void) platform_device_register(&omap_i2c_device2);
-}
-
-#else
-
-static void omap_init_i2c(void) {}
-
-#endif
+#include <mach/eac.h>
 
 #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
 #define OMAP2_MBOX_BASE         IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
 
 #if defined(CONFIG_OMAP_STI)
 
-#define OMAP2_STI_BASE          IO_ADDRESS(0x48068000)
+#if defined(CONFIG_ARCH_OMAP2)
+
+#define OMAP2_STI_BASE          0x48068000
 #define OMAP2_STI_CHANNEL_BASE  0x54000000
 #define OMAP2_STI_IRQ           4
 
@@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
                 .flags          = IORESOURCE_IRQ,
         }
 };
+#elif defined(CONFIG_ARCH_OMAP3)
+
+#define OMAP3_SDTI_BASE         0x54500000
+#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
+
+static struct resource sti_resources[] = {
+        {
+                .start          = OMAP3_SDTI_BASE,
+                .end            = OMAP3_SDTI_BASE + 0xFFF,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = OMAP3_SDTI_CHANNEL_BASE,
+                .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+#endif
 
 static struct platform_device sti_device = {
         .name           = "sti",
@@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
 static inline void omap_init_sti(void) {}
 #endif
 
-#if defined(CONFIG_SPI_OMAP24XX)
+#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
 #include <mach/mcspi.h>
 
 #define OMAP2_MCSPI1_BASE               0x48098000
 #define OMAP2_MCSPI2_BASE               0x4809a000
+#define OMAP2_MCSPI3_BASE               0x480b8000
+#define OMAP2_MCSPI4_BASE               0x480ba000
 
 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
         .num_cs         = 4,
@@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
         },
 };
 
-struct platform_device omap2_mcspi1 = {
+static struct platform_device omap2_mcspi1 = {
         .name           = "omap2_mcspi",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
@@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
         },
 };
 
-struct platform_device omap2_mcspi2 = {
+static struct platform_device omap2_mcspi2 = {
         .name           = "omap2_mcspi",
         .id             = 2,
         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
@@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
         },
 };
 
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
+        .num_cs         = 2,
+};
+
+static struct resource omap2_mcspi3_resources[] = {
+        {
+        .start          = OMAP2_MCSPI3_BASE,
+        .end            = OMAP2_MCSPI3_BASE + 0xff,
+        .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap2_mcspi3 = {
+        .name           = "omap2_mcspi",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
+        .resource       = omap2_mcspi3_resources,
+        .dev            = {
+                .platform_data = &omap2_mcspi3_config,
+        },
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
+        .num_cs         = 1,
+};
+
+static struct resource omap2_mcspi4_resources[] = {
+        {
+                .start          = OMAP2_MCSPI4_BASE,
+                .end            = OMAP2_MCSPI4_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap2_mcspi4 = {
+        .name           = "omap2_mcspi",
+        .id             = 4,
+        .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
+        .resource       = omap2_mcspi4_resources,
+        .dev            = {
+                .platform_data = &omap2_mcspi4_config,
+        },
+};
+#endif
+
 static void omap_init_mcspi(void)
 {
         platform_device_register(&omap2_mcspi1);
         platform_device_register(&omap2_mcspi2);
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
+        platform_device_register(&omap2_mcspi3);
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+        platform_device_register(&omap2_mcspi4);
+#endif
 }
 
 #else
 static inline void omap_init_mcspi(void) {}
 #endif
 
+#ifdef CONFIG_SND_OMAP24XX_EAC
+
+#define OMAP2_EAC_BASE                  0x48090000
+
+static struct resource omap2_eac_resources[] = {
+        {
+                .start          = OMAP2_EAC_BASE,
+                .end            = OMAP2_EAC_BASE + 0x109,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap2_eac_device = {
+        .name           = "omap24xx-eac",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap2_eac_resources),
+        .resource       = omap2_eac_resources,
+        .dev = {
+                .platform_data = NULL,
+        },
+};
+
+void omap_init_eac(struct eac_platform_data *pdata)
+{
+        omap2_eac_device.dev.platform_data = pdata;
+        platform_device_register(&omap2_eac_device);
+}
+
+#else
+void omap_init_eac(struct eac_platform_data *pdata) {}
+#endif
+
+#ifdef CONFIG_OMAP_SHA1_MD5
+static struct resource sha1_md5_resources[] = {
+        {
+                .start  = OMAP24XX_SEC_SHA1MD5_BASE,
+                .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_24XX_SHA1MD5,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device sha1_md5_device = {
+        .name           = "OMAP SHA1/MD5",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(sha1_md5_resources),
+        .resource       = sha1_md5_resources,
+};
+
+static void omap_init_sha1_md5(void)
+{
+        platform_device_register(&sha1_md5_device);
+}
+#else
+static inline void omap_init_sha1_md5(void) { }
+#endif
+
+#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+#define OMAP_HDQ_BASE   0x480B2000
+#endif
+static struct resource omap_hdq_resources[] = {
+        {
+                .start          = OMAP_HDQ_BASE,
+                .end            = OMAP_HDQ_BASE + 0x1C,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = INT_24XX_HDQ_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device omap_hdq_dev = {
+        .name = "omap_hdq",
+        .id = 0,
+        .dev = {
+                .platform_data = NULL,
+        },
+        .num_resources  = ARRAY_SIZE(omap_hdq_resources),
+        .resource       = omap_hdq_resources,
+};
+static inline void omap_hdq_init(void)
+{
+        (void) platform_device_register(&omap_hdq_dev);
+}
+#else
+static inline void omap_hdq_init(void) {}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
-        omap_init_i2c();
         omap_init_mbox();
         omap_init_mcspi();
+        omap_hdq_init();
         omap_init_sti();
+        omap_init_sha1_md5();
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9b4e58ee2ca2..149bfba43cfe 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -9,27 +9,23 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#undef DEBUG
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
+#include <linux/module.h>
 
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <mach/gpmc.h>
 
-#undef DEBUG
-
-#ifdef CONFIG_ARCH_OMAP2420
-#define GPMC_BASE               0x6800a000
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2430
-#define GPMC_BASE               0x6E000000
-#endif
+#include <mach/sdrc.h>
 
+/* GPMC register offsets */
 #define GPMC_REVISION           0x00
 #define GPMC_SYSCONFIG          0x10
 #define GPMC_SYSSTATUS          0x14
@@ -51,7 +47,6 @@
 #define GPMC_CS0                0x60
 #define GPMC_CS_SIZE            0x30
 
-#define GPMC_CS_NUM             8
 #define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
@@ -64,10 +59,9 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned         gpmc_cs_map;
 
-static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE);
-static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
+static void __iomem *gpmc_base;
 
-static struct clk *gpmc_fck;
+static struct clk *gpmc_l3_clk;
 
 static void gpmc_write_reg(int idx, u32 val)
 {
@@ -83,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
 {
         void __iomem *reg_addr;
 
-        reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
+        reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
         __raw_writel(val, reg_addr);
 }
 
 u32 gpmc_cs_read_reg(int cs, int idx)
 {
-        return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
+        void __iomem *reg_addr;
+
+        reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
+        return __raw_readl(reg_addr);
 }
 
+/* TODO: Add support for gpmc_fck to clock framework and use it */
 unsigned long gpmc_get_fclk_period(void)
 {
-        /* In picoseconds */
-        return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
+        unsigned long rate = clk_get_rate(gpmc_l3_clk);
+
+        if (rate == 0) {
+                printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
+                return 0;
+        }
+
+        rate /= 1000;
+        rate = 1000000000 / rate;       /* In picoseconds */
+
+        return rate;
 }
 
 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -108,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
+unsigned int gpmc_ticks_to_ns(unsigned int ticks)
+{
+        return ticks * gpmc_get_fclk_period() / 1000;
+}
+
 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
@@ -348,6 +360,7 @@ out:
         spin_unlock(&gpmc_mem_lock);
         return r;
 }
+EXPORT_SYMBOL(gpmc_cs_request);
 
 void gpmc_cs_free(int cs)
 {
@@ -363,8 +376,9 @@ void gpmc_cs_free(int cs)
         gpmc_cs_set_reserved(cs, 0);
         spin_unlock(&gpmc_mem_lock);
 }
+EXPORT_SYMBOL(gpmc_cs_free);
 
-void __init gpmc_mem_init(void)
+static void __init gpmc_mem_init(void)
 {
         int cs;
         unsigned long boot_rom_space = 0;
@@ -394,12 +408,33 @@ void __init gpmc_mem_init(void)
 void __init gpmc_init(void)
 {
         u32 l;
+        char *ck;
+
+        if (cpu_is_omap24xx()) {
+                ck = "core_l3_ck";
+                if (cpu_is_omap2420())
+                        l = OMAP2420_GPMC_BASE;
+                else
+                        l = OMAP34XX_GPMC_BASE;
+        } else if (cpu_is_omap34xx()) {
+                ck = "gpmc_fck";
+                l = OMAP34XX_GPMC_BASE;
+        }
 
-        gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
-        if (IS_ERR(gpmc_fck))
-                WARN_ON(1);
-        else
-                clk_enable(gpmc_fck);
+        gpmc_l3_clk = clk_get(NULL, ck);
+        if (IS_ERR(gpmc_l3_clk)) {
+                printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
+                return -ENODEV;
+        }
+
+        gpmc_base = ioremap(l, SZ_4K);
+        if (!gpmc_base) {
+                clk_put(gpmc_l3_clk);
+                printk(KERN_ERR "Could not get GPMC register memory\n");
+                return -ENOMEM;
+        }
+
+        BUG_ON(IS_ERR(gpmc_l3_clk));
 
         l = gpmc_read_reg(GPMC_REVISION);
         printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index e53ebe7d58be..0670c8db010a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,24 +17,15 @@
 
 #include <asm/io.h>
 
+#include <mach/common.h>
 #include <mach/control.h>
 #include <mach/cpu.h>
 
-#if defined(CONFIG_ARCH_OMAP2420)
-#define TAP_BASE        IO_ADDRESS(0x48014000)
-#elif defined(CONFIG_ARCH_OMAP2430)
-#define TAP_BASE        IO_ADDRESS(0x4900A000)
-#elif defined(CONFIG_ARCH_OMAP34XX)
-#define TAP_BASE        IO_ADDRESS(0x4830A000)
-#endif
+static u32 class;
+static void __iomem *tap_base;
+static u16 tap_prod_id;
 
 #define OMAP_TAP_IDCODE         0x0204
-#if defined(CONFIG_ARCH_OMAP34XX)
-#define OMAP_TAP_PROD_ID        0x0210
-#else
-#define OMAP_TAP_PROD_ID        0x0208
-#endif
-
 #define OMAP_TAP_DIE_ID_0       0x0218
 #define OMAP_TAP_DIE_ID_1       0x021C
 #define OMAP_TAP_DIE_ID_2       0x0220
@@ -93,18 +84,24 @@ static u32 __init read_tap_reg(int reg)
          * it means its Cortex r0p0 which is 3430 ES1
          */
         if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
+
+                if (reg == tap_prod_id) {
+                        regval = 0x000F00F0;
+                        goto out;
+                }
+
                 switch (reg) {
                 case OMAP_TAP_IDCODE  : regval = 0x0B7AE02F; break;
                 /* Making DevType as 0xF in ES1 to differ from ES2 */
-                case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
                 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
                 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
                 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
                 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
                 }
         } else
-                regval = __raw_readl(TAP_BASE + reg);
+                regval = __raw_readl(tap_base + reg);
 
+out:
         return regval;
 
 }
@@ -203,7 +200,7 @@ void __init omap2_check_revision(void)
         u8  rev;
 
         idcode = read_tap_reg(OMAP_TAP_IDCODE);
-        prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
+        prod_id = read_tap_reg(tap_prod_id);
         hawkeye = (idcode >> 12) & 0xffff;
         rev = (idcode >> 28) & 0x0f;
         dev_type = (prod_id >> 16) & 0x0f;
@@ -268,3 +265,13 @@ void __init omap2_check_revision(void)
 
 }
 
+void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
+{
+        class = omap2_globals->class;
+        tap_base = omap2_globals->tap;
+
+        if (class == 0x3430)
+                tap_prod_id = 0x0210;
+        else
+                tap_prod_id = 0x0208;
+}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 371e5409fef0..03c6ab1a3b1f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -4,8 +4,11 @@
  * OMAP2 I/O mapping code
  *
  * Copyright (C) 2005 Nokia Corporation
- * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- * Updated map desc to add 2430 support : <x0khasim@ti.com>
+ * Copyright (C) 2007 Texas Instruments
+ *
+ * Author:
+ *      Juha Yrjola <juha.yrjola@nokia.com>
+ *      Syed Khasim <x0khasim@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,6 +26,11 @@
 
 #include <mach/mux.h>
 #include <mach/omapfb.h>
+#include <mach/sram.h>
+
+#include "memory.h"
+
+#include "clock.h"
 
 #include <mach/powerdomain.h>
 
@@ -31,13 +39,6 @@
 #include <mach/clockdomain.h>
 #include "clockdomains.h"
 
-extern void omap_sram_init(void);
-extern int omap2_clk_init(void);
-extern void omap2_check_revision(void);
-extern void omap2_init_memory(void);
-extern void gpmc_init(void);
-extern void omapfb_reserve_sdram(void);
-
 /*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 742bd0070e63..c39e26dc5ee3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -13,17 +13,23 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <asm/io.h>
 
-#define INTC_REVISION   0x0000
-#define INTC_SYSCONFIG  0x0010
-#define INTC_SYSSTATUS  0x0014
-#define INTC_CONTROL    0x0048
-#define INTC_MIR_CLEAR0 0x0088
-#define INTC_MIR_SET0   0x008c
+
+/* selected INTC register offsets */
+
+#define INTC_REVISION           0x0000
+#define INTC_SYSCONFIG          0x0010
+#define INTC_SYSSTATUS          0x0014
+#define INTC_CONTROL            0x0048
+#define INTC_MIR_CLEAR0         0x0088
+#define INTC_MIR_SET0           0x008c
+#define INTC_PENDING_IRQ0       0x0098
+
+/* Number of IRQ state bits in each MIR register */
+#define IRQ_BITS_PER_REG        32
 
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -37,43 +43,45 @@ static struct omap_irq_bank {
 } __attribute__ ((aligned(4))) irq_banks[] = {
         {
                 /* MPU INTC */
-                .base_reg       = IO_ADDRESS(OMAP24XX_IC_BASE),
+                .base_reg       = 0,
                 .nr_irqs        = 96,
-        }, {
-                /* XXX: DSP INTC */
-        }
+        },
 };
 
+/* INTC bank register get/set */
+
+static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
+{
+        __raw_writel(val, bank->base_reg + reg);
+}
+
+static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
+{
+        return __raw_readl(bank->base_reg + reg);
+}
+
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 static void omap_ack_irq(unsigned int irq)
 {
-        __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
+        intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 }
 
 static void omap_mask_irq(unsigned int irq)
 {
-        int offset = (irq >> 5) << 5;
+        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 
-        if (irq >= 64) {
-                irq %= 64;
-        } else if (irq >= 32) {
-                irq %= 32;
-        }
+        irq &= (IRQ_BITS_PER_REG - 1);
 
-        __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
+        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
 }
 
 static void omap_unmask_irq(unsigned int irq)
 {
-        int offset = (irq >> 5) << 5;
+        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 
-        if (irq >= 64) {
-                irq %= 64;
-        } else if (irq >= 32) {
-                irq %= 32;
-        }
+        irq &= (IRQ_BITS_PER_REG - 1);
 
-        __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
+        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
 }
 
 static void omap_mask_ack_irq(unsigned int irq)
@@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 {
         unsigned long tmp;
 
-        tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
+        tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
                          "(revision %ld.%ld) with %d interrupts\n",
                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 
-        tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
+        tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
         tmp |= 1 << 1;  /* soft reset */
-        __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
+        intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 
-        while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
+        while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
                 /* Wait for reset to complete */;
 
         /* Enable autoidle */
-        __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
+        intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 }
 
 void __init omap_init_irq(void)
@@ -118,9 +126,8 @@ void __init omap_init_irq(void)
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 struct omap_irq_bank *bank = irq_banks + i;
 
-                /* XXX */
-                if (!bank->base_reg)
-                        continue;
+                if (cpu_is_omap24xx())
+                        bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
 
                 omap_irq_bank_init_one(bank);
 
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index 9a280b50a893..bb3db80a7c46 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -14,6 +14,9 @@
  * published by the Free Software Foundation.
  */
 
+#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
+#define ARCH_ARM_MACH_OMAP2_MEMORY_H
+
 /* Memory timings */
 #define M_DDR           1
 #define M_LOCK_CTRL     (1 << 2)
@@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
 extern u32 omap2_memory_get_type(void);
 u32 omap2_dll_force_needed(void);
 u32 omap2_reprogram_sdrc(u32 level, u32 force);
+void __init omap2_init_memory(void);
+void __init gpmc_init(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 443d07fef7f3..6188e2f97854 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP2 pin multiplexing configurations
+ * OMAP2 and OMAP3 pin multiplexing configurations
  *
  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
  * Copyright (C) 2003 - 2008 Nokia Corporation
@@ -219,16 +219,179 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF",	0x0131,	0,	0,	0,	1)
 #define OMAP24XX_PINS_SZ        0
 #endif  /* CONFIG_ARCH_OMAP24XX */
 
-#define OMAP24XX_PULL_ENA       (1 << 3)
-#define OMAP24XX_PULL_UP        (1 << 4)
+#ifdef CONFIG_ARCH_OMAP34XX
+static struct pin_config __initdata_or_module omap34xx_pins[] = {
+/*
+ *              Name, reg-offset,
+ *              mux-mode | [active-mode | off-mode]
+ */
+
+/* 34xx I2C */
+MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
+MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
+MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
+                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+/* TLL - HSUSB: 12-pin TLL Port 1*/
+MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+/* TLL - HSUSB: 12-pin TLL Port 2*/
+MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
+                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
+                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
+
+/* TLL - HSUSB: 12-pin TLL Port 3*/
+MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
+                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
+};
+
+#define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
+
+#else
+#define omap34xx_pins           NULL
+#define OMAP34XX_PINS_SZ        0
+#endif  /* CONFIG_ARCH_OMAP34XX */
 
 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
-void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
+static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
 {
         u16 orig;
         u8 warn = 0, debug = 0;
 
-        orig = omap_ctrl_readb(cfg->mux_reg);
+        if (cpu_is_omap24xx())
+                orig = omap_ctrl_readb(cfg->mux_reg);
+        else
+                orig = omap_ctrl_readw(cfg->mux_reg);
 
 #ifdef  CONFIG_OMAP_MUX_DEBUG
         debug = cfg->debug;
@@ -254,9 +417,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
         spin_lock_irqsave(&mux_spin_lock, flags);
         reg |= cfg->mask & 0x7;
         if (cfg->pull_val)
-                reg |= OMAP24XX_PULL_ENA;
+                reg |= OMAP2_PULL_ENA;
         if (cfg->pu_pd_val)
-                reg |= OMAP24XX_PULL_UP;
+                reg |= OMAP2_PULL_UP;
         omap2_cfg_debug(cfg, reg);
         omap_ctrl_writeb(reg, cfg->mux_reg);
         spin_unlock_irqrestore(&mux_spin_lock, flags);
@@ -264,7 +427,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
         return 0;
 }
 #else
-#define omap24xx_cfg_reg        0
+#define omap24xx_cfg_reg        NULL
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
+{
+        static DEFINE_SPINLOCK(mux_spin_lock);
+        unsigned long flags;
+        u16 reg = 0;
+
+        spin_lock_irqsave(&mux_spin_lock, flags);
+        reg |= cfg->mux_val;
+        omap2_cfg_debug(cfg, reg);
+        omap_ctrl_writew(reg, cfg->mux_reg);
+        spin_unlock_irqrestore(&mux_spin_lock, flags);
+
+        return 0;
+}
+#else
+#define omap34xx_cfg_reg        NULL
 #endif
 
 int __init omap2_mux_init(void)
@@ -273,6 +455,10 @@ int __init omap2_mux_init(void)
                 arch_mux_cfg.pins       = omap24xx_pins;
                 arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
                 arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+        } else if (cpu_is_omap34xx()) {
+                arch_mux_cfg.pins       = omap34xx_pins;
+                arch_mux_cfg.size       = OMAP34XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap34xx_cfg_reg;
         }
 
         return omap_mux_register(&arch_mux_cfg);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 69651cf08305..78ab2be70241 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -3,7 +3,7 @@
  *
  * OMAP2 serial support.
  *
- * Copyright (C) 2005 Nokia Corporation
+ * Copyright (C) 2005-2008 Nokia Corporation
  * Author: Paul Mundt <paul.mundt@nokia.com>
  *
  * Based off of arch/arm/mach-omap/omap1/serial.c
@@ -23,12 +23,8 @@
 #include <mach/common.h>
 #include <mach/board.h>
 
-static struct clk * uart1_ick = NULL;
-static struct clk * uart1_fck = NULL;
-static struct clk * uart2_ick = NULL;
-static struct clk * uart2_fck = NULL;
-static struct clk * uart3_ick = NULL;
-static struct clk * uart3_fck = NULL;
+static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
+static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
 
 static struct plat_serial8250_port serial_platform_data[] = {
         {
@@ -38,7 +34,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags          = UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
@@ -46,7 +42,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags          = UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
@@ -54,7 +50,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .flags          = UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = OMAP16XX_BASE_BAUD * 16,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
                 .flags          = 0
         }
@@ -87,10 +83,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 }
 
-void __init omap_serial_init()
+void omap_serial_enable_clocks(int enable)
+{
+        int i;
+        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+                if (uart_ick[i] && uart_fck[i]) {
+                        if (enable) {
+                                clk_enable(uart_ick[i]);
+                                clk_enable(uart_fck[i]);
+                        } else {
+                                clk_disable(uart_ick[i]);
+                                clk_disable(uart_fck[i]);
+                        }
+                }
+        }
+}
+
+void __init omap_serial_init(void)
 {
         int i;
         const struct omap_uart_config *info;
+        char name[16];
 
         /*
          * Make sure the serial ports are muxed on at this point.
@@ -98,8 +111,7 @@ void __init omap_serial_init()
          * if not needed.
          */
 
-        info = omap_get_config(OMAP_TAG_UART,
-                               struct omap_uart_config);
+        info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
 
         if (info == NULL)
                 return;
@@ -113,53 +125,21 @@ void __init omap_serial_init()
                         continue;
                 }
 
-                switch (i) {
-                case 0:
-                        uart1_ick = clk_get(NULL, "uart1_ick");
-                        if (IS_ERR(uart1_ick))
-                                printk("Could not get uart1_ick\n");
-                        else {
-                                clk_enable(uart1_ick);
-                        }
-
-                        uart1_fck = clk_get(NULL, "uart1_fck");
-                        if (IS_ERR(uart1_fck))
-                                printk("Could not get uart1_fck\n");
-                        else {
-                                clk_enable(uart1_fck);
-                        }
-                        break;
-                case 1:
-                        uart2_ick = clk_get(NULL, "uart2_ick");
-                        if (IS_ERR(uart2_ick))
-                                printk("Could not get uart2_ick\n");
-                        else {
-                                clk_enable(uart2_ick);
-                        }
-
-                        uart2_fck = clk_get(NULL, "uart2_fck");
-                        if (IS_ERR(uart2_fck))
-                                printk("Could not get uart2_fck\n");
-                        else {
-                                clk_enable(uart2_fck);
-                        }
-                        break;
-                case 2:
-                        uart3_ick = clk_get(NULL, "uart3_ick");
-                        if (IS_ERR(uart3_ick))
-                                printk("Could not get uart3_ick\n");
-                        else {
-                                clk_enable(uart3_ick);
-                        }
-
-                        uart3_fck = clk_get(NULL, "uart3_fck");
-                        if (IS_ERR(uart3_fck))
-                                printk("Could not get uart3_fck\n");
-                        else {
-                                clk_enable(uart3_fck);
-                        }
-                        break;
-                }
+                sprintf(name, "uart%d_ick", i+1);
+                uart_ick[i] = clk_get(NULL, name);
+                if (IS_ERR(uart_ick[i])) {
+                        printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
+                        uart_ick[i] = NULL;
+                } else
+                        clk_enable(uart_ick[i]);
+
+                sprintf(name, "uart%d_fck", i+1);
+                uart_fck[i] = clk_get(NULL, name);
+                if (IS_ERR(uart_fck[i])) {
+                        printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
+                        uart_fck[i] = NULL;
+                } else
+                        clk_enable(uart_fck[i]);
 
                 omap_serial_reset(p);
         }
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep24xx.S
index 87a706fd5f82..43336b93b21c 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -5,6 +5,10 @@
  * Texas Instruments, <www.ti.com>
  * Richard Woodruff <r-woodruff2@ti.com>
  *
+ * (C) Copyright 2006 Nokia Corporation
+ * Fixed idle loop sleep
+ * Igor Stoppa <igor.stoppa@nokia.com>
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -26,6 +30,8 @@
 #include <mach/io.h>
 #include <mach/pm.h>
 
+#include <mach/omap24xx.h>
+
 #include "sdrc.h"
 
 /* First address of reserved address space?  apparently valid for OMAP2 & 3 */
@@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
         .word   . - omap24xx_idle_loop_suspend
 
 /*
- * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
+ * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
  * SDRC shutdown then ARM shutdown.  Upon wake MPU is back on so just restore
  * SDRC.
  *
  * Input:
  * R0 : DLL ctrl value pre-Sleep
- * R1 : Processor+Revision
- *      2420: 0x21 = 242xES1, 0x26 = 242xES2.2
- *      2430: 0x31 = 2430ES1, 0x32 = 2430ES2
+ * R1 : SDRC_DLLA_CTRL
+ * R2 : SDRC_POWER
  *
  * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
  * when we get called, but the DLL probably isn't.  We will wait a bit more in
@@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
  */
 ENTRY(omap24xx_cpu_suspend)
         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
-        mov     r3, #0x0                @ clear for mrc call
+        mov     r3, #0x0                @ clear for mcr call
         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, hope SDR/DDR finished
         nop
         nop
-        ldr     r3, A_SDRC_POWER        @ addr of sdrc power
-        ldr     r4, [r3]                @ value of sdrc power
+        ldr     r4, [r2]                @ read SDRC_POWER
         orr     r4, r4, #0x40           @ enable self refresh on idle req
         mov     r5, #0x2000             @ set delay (DPLL relock + DLL relock)
-        str     r4, [r3]                @ make it so
+        str     r4, [r2]                @ make it so
         mov     r2, #0
         nop
         mcr     p15, 0, r2, c7, c0, 4   @ wait for interrupt
@@ -97,14 +101,13 @@ loop:
         subs    r5, r5, #0x1            @ awake, wait just a bit
         bne     loop
 
-        /* The DPLL has on before we take the DDR out of self refresh */
+        /* The DPLL has to be on before we take the DDR out of self refresh */
         bic     r4, r4, #0x40           @ now clear self refresh bit.
-        str     r4, [r3]                @ put vlaue back.
+        str     r4, [r2]                @ write to SDRC_POWER
         ldr     r4, A_SDRC0             @ make a clock happen
-        ldr     r4, [r4]
+        ldr     r4, [r4]                @ read A_SDRC0
         nop                             @ start auto refresh only after clk ok
         movs    r0, r0                  @ see if DDR or SDR
-        ldrne   r1, A_SDRC_DLLA_CTRL_S  @ get addr of DLL ctrl
         strne   r0, [r1]                @ rewrite DLLA to force DLL reload
         addne   r1, r1, #0x8            @ move to DLLB
         strne   r0, [r1]                @ rewrite DLLB to force DLL reload
@@ -116,13 +119,8 @@ loop2:
         /* resume*/
         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
 
-A_SDRC_POWER:
-        .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
 A_SDRC0:
         .word A_SDRC0_V
-A_SDRC_DLLA_CTRL_S:
-        .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
 ENTRY(omap24xx_cpu_suspend_sz)
         .word   . - omap24xx_cpu_suspend
-