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authorTony Lindgren <tony@atomide.com>2009-11-22 13:08:43 -0500
committerTony Lindgren <tony@atomide.com>2009-11-22 13:08:43 -0500
commita76df42a675c9936e8bf3607226e74c8a5e2d847 (patch)
tree96d93706d884dea956393653452fa4d78d8d7f76 /arch/arm/mach-omap2
parent648f4e3e50c4793d9dbf9a09afa193631f76fa26 (diff)
parent8171d88089ad63fc442b2bf32af7c18653adc5cb (diff)
Merge 7xx-iosplit-plat-merge with omap-fixes
Merge branch '7xx-iosplit-plat-merge' into omap-for-linus
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Makefile2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c14
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c20
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c23
-rw-r--r--arch/arm/mach-omap2/board-apollon.c16
-rw-r--r--arch/arm/mach-omap2/board-generic.c10
-rw-r--r--arch/arm/mach-omap2/board-h4.c20
-rw-r--r--arch/arm/mach-omap2/board-ldp.c14
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c16
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c16
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c12
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c12
-rw-r--r--arch/arm/mach-omap2/board-overo.c16
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c16
-rw-r--r--arch/arm/mach-omap2/board-rx51.c16
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c6
-rw-r--r--arch/arm/mach-omap2/clock.c10
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/clock24xx.c8
-rw-r--r--arch/arm/mach-omap2/clock34xx.c8
-rw-r--r--arch/arm/mach-omap2/clock34xx.h2
-rw-r--r--arch/arm/mach-omap2/clockdomain.c6
-rw-r--r--arch/arm/mach-omap2/clockdomains.h2
-rw-r--r--arch/arm/mach-omap2/cm.h6
-rw-r--r--arch/arm/mach-omap2/control.c385
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c318
-rw-r--r--arch/arm/mach-omap2/devices.c12
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c6
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c6
-rw-r--r--arch/arm/mach-omap2/gpmc.c102
-rw-r--r--arch/arm/mach-omap2/id.c6
-rw-r--r--arch/arm/mach-omap2/include/mach/clkdev.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S59
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S124
-rw-r--r--arch/arm/mach-omap2/include/mach/gpio.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/io.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/memory.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/smp.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/system.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/timex.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/uncompress.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/vmalloc.h20
-rw-r--r--arch/arm/mach-omap2/io.c38
-rw-r--r--arch/arm/mach-omap2/iommu2.c2
-rw-r--r--arch/arm/mach-omap2/irq.c78
-rw-r--r--arch/arm/mach-omap2/mailbox.c2
-rw-r--r--arch/arm/mach-omap2/mcbsp.c8
-rw-r--r--arch/arm/mach-omap2/mmc-twl4030.c6
-rw-r--r--arch/arm/mach-omap2/mux.c4
-rw-r--r--arch/arm/mach-omap2/omap-smp.c29
-rw-r--r--arch/arm/mach-omap2/omap3-iommu.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c28
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420.h6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430.h6
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_34xx.h6
-rw-r--r--arch/arm/mach-omap2/pm-debug.c40
-rw-r--r--arch/arm/mach-omap2/pm.h16
-rw-r--r--arch/arm/mach-omap2/pm24xx.c16
-rw-r--r--arch/arm/mach-omap2/pm34xx.c419
-rw-r--r--arch/arm/mach-omap2/powerdomain.c6
-rw-r--r--arch/arm/mach-omap2/powerdomains.h2
-rw-r--r--arch/arm/mach-omap2/powerdomains24xx.h2
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h10
-rw-r--r--arch/arm/mach-omap2/prcm.c411
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h2
-rw-r--r--arch/arm/mach-omap2/prm.h6
-rw-r--r--arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h2
-rw-r--r--arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h2
-rw-r--r--arch/arm/mach-omap2/sdrc.c35
-rw-r--r--arch/arm/mach-omap2/sdrc.h11
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c8
-rw-r--r--arch/arm/mach-omap2/serial.c24
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S2
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S220
-rw-r--r--arch/arm/mach-omap2/sram242x.S4
-rw-r--r--arch/arm/mach-omap2/sram243x.S4
-rw-r--r--arch/arm/mach-omap2/timer-gp.c7
-rw-r--r--arch/arm/mach-omap2/usb-musb.c4
-rw-r--r--arch/arm/mach-omap2/usb-tusb6010.c4
82 files changed, 2480 insertions, 355 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 8cb16777661a..1d54ad349bfd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
31ifeq ($(CONFIG_PM),y) 31ifeq ($(CONFIG_PM),y)
32obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 32obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
33obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o 33obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
34obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 34obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
35obj-$(CONFIG_PM_DEBUG) += pm-debug.o 35obj-$(CONFIG_PM_DEBUG) += pm-debug.o
36endif 36endif
37 37
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 42217b32f835..db9374bc528b 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -31,12 +31,12 @@
31#include <asm/mach/flash.h> 31#include <asm/mach/flash.h>
32 32
33#include <mach/gpio.h> 33#include <mach/gpio.h>
34#include <mach/mux.h> 34#include <plat/mux.h>
35#include <mach/board.h> 35#include <plat/board.h>
36#include <mach/common.h> 36#include <plat/common.h>
37#include <mach/gpmc.h> 37#include <plat/gpmc.h>
38#include <mach/usb.h> 38#include <plat/usb.h>
39#include <mach/gpmc-smc91x.h> 39#include <plat/gpmc-smc91x.h>
40 40
41#include "mmc-twl4030.h" 41#include "mmc-twl4030.h"
42 42
@@ -221,7 +221,7 @@ static void __init omap_2430sdp_map_io(void)
221MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") 221MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
222 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 222 /* Maintainer: Syed Khasim - Texas Instruments Inc */
223 .phys_io = 0x48000000, 223 .phys_io = 0x48000000,
224 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 224 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
225 .boot_params = 0x80000100, 225 .boot_params = 0x80000100,
226 .map_io = omap_2430sdp_map_io, 226 .map_io = omap_2430sdp_map_io,
227 .init_irq = omap_2430sdp_init_irq, 227 .init_irq = omap_2430sdp_init_irq,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 0acb5560229c..a2abac98c569 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -30,16 +30,16 @@
30#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
31#include <asm/mach/map.h> 31#include <asm/mach/map.h>
32 32
33#include <mach/mcspi.h> 33#include <plat/mcspi.h>
34#include <mach/mux.h> 34#include <plat/mux.h>
35#include <mach/board.h> 35#include <plat/board.h>
36#include <mach/usb.h> 36#include <plat/usb.h>
37#include <mach/common.h> 37#include <plat/common.h>
38#include <mach/dma.h> 38#include <plat/dma.h>
39#include <mach/gpmc.h> 39#include <plat/gpmc.h>
40 40
41#include <mach/control.h> 41#include <plat/control.h>
42#include <mach/gpmc-smc91x.h> 42#include <plat/gpmc-smc91x.h>
43 43
44#include "sdram-qimonda-hyb18m512160af-6.h" 44#include "sdram-qimonda-hyb18m512160af-6.h"
45#include "mmc-twl4030.h" 45#include "mmc-twl4030.h"
@@ -511,7 +511,7 @@ static void __init omap_3430sdp_map_io(void)
511MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") 511MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
512 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 512 /* Maintainer: Syed Khasim - Texas Instruments Inc */
513 .phys_io = 0x48000000, 513 .phys_io = 0x48000000,
514 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 514 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
515 .boot_params = 0x80000100, 515 .boot_params = 0x80000100,
516 .map_io = omap_3430sdp_map_io, 516 .map_io = omap_3430sdp_map_io,
517 .init_irq = omap_3430sdp_init_irq, 517 .init_irq = omap_3430sdp_init_irq,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 609a5a4a7e29..0c6be6b4a7e2 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -23,10 +23,10 @@
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25 25
26#include <mach/board.h> 26#include <plat/board.h>
27#include <mach/common.h> 27#include <plat/common.h>
28#include <mach/control.h> 28#include <plat/control.h>
29#include <mach/timer-gp.h> 29#include <plat/timer-gp.h>
30#include <asm/hardware/gic.h> 30#include <asm/hardware/gic.h>
31 31
32static struct platform_device sdp4430_lcd_device = { 32static struct platform_device sdp4430_lcd_device = {
@@ -52,8 +52,17 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
52 52
53static void __init gic_init_irq(void) 53static void __init gic_init_irq(void)
54{ 54{
55 gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); 55 void __iomem *base;
56 gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); 56
57 /* Static mapping, never released */
58 base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
59 BUG_ON(!base);
60 gic_dist_init(0, base, 29);
61
62 /* Static mapping, never released */
63 gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
64 BUG_ON(!gic_cpu_base_addr);
65 gic_cpu_init(0, gic_cpu_base_addr);
57} 66}
58 67
59static void __init omap_4430sdp_init_irq(void) 68static void __init omap_4430sdp_init_irq(void)
@@ -84,7 +93,7 @@ static void __init omap_4430sdp_map_io(void)
84MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") 93MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
85 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ 94 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
86 .phys_io = 0x48000000, 95 .phys_io = 0x48000000,
87 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 96 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
88 .boot_params = 0x80000100, 97 .boot_params = 0x80000100,
89 .map_io = omap_4430sdp_map_io, 98 .map_io = omap_4430sdp_map_io,
90 .init_irq = omap_4430sdp_init_irq, 99 .init_irq = omap_4430sdp_init_irq,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index a1132288c701..8a2ce77a02ec 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -33,13 +33,13 @@
33#include <asm/mach/flash.h> 33#include <asm/mach/flash.h>
34 34
35#include <mach/gpio.h> 35#include <mach/gpio.h>
36#include <mach/led.h> 36#include <plat/led.h>
37#include <mach/mux.h> 37#include <plat/mux.h>
38#include <mach/usb.h> 38#include <plat/usb.h>
39#include <mach/board.h> 39#include <plat/board.h>
40#include <mach/common.h> 40#include <plat/common.h>
41#include <mach/gpmc.h> 41#include <plat/gpmc.h>
42#include <mach/control.h> 42#include <plat/control.h>
43 43
44/* LED & Switch macros */ 44/* LED & Switch macros */
45#define LED0_GPIO13 13 45#define LED0_GPIO13 13
@@ -333,7 +333,7 @@ static void __init omap_apollon_map_io(void)
333MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") 333MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
334 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 334 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
335 .phys_io = 0x48000000, 335 .phys_io = 0x48000000,
336 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 336 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
337 .boot_params = 0x80000100, 337 .boot_params = 0x80000100,
338 .map_io = omap_apollon_map_io, 338 .map_io = omap_apollon_map_io,
339 .init_irq = omap_apollon_init_irq, 339 .init_irq = omap_apollon_init_irq,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 2e09a1c444cb..7e6e6ca88be5 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -26,10 +26,10 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28#include <mach/gpio.h> 28#include <mach/gpio.h>
29#include <mach/mux.h> 29#include <plat/mux.h>
30#include <mach/usb.h> 30#include <plat/usb.h>
31#include <mach/board.h> 31#include <plat/board.h>
32#include <mach/common.h> 32#include <plat/common.h>
33 33
34static struct omap_board_config_kernel generic_config[] = { 34static struct omap_board_config_kernel generic_config[] = {
35}; 35};
@@ -56,7 +56,7 @@ static void __init omap_generic_map_io(void)
56MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") 56MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
57 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 57 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
58 .phys_io = 0x48000000, 58 .phys_io = 0x48000000,
59 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 59 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
60 .boot_params = 0x80000100, 60 .boot_params = 0x80000100,
61 .map_io = omap_generic_map_io, 61 .map_io = omap_generic_map_io,
62 .init_irq = omap_generic_init_irq, 62 .init_irq = omap_generic_init_irq,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index eaa02d012c5c..cfb7f1257d20 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -31,16 +31,16 @@
31#include <asm/mach/map.h> 31#include <asm/mach/map.h>
32#include <asm/mach/flash.h> 32#include <asm/mach/flash.h>
33 33
34#include <mach/control.h> 34#include <plat/control.h>
35#include <mach/gpio.h> 35#include <mach/gpio.h>
36#include <mach/mux.h> 36#include <plat/mux.h>
37#include <mach/usb.h> 37#include <plat/usb.h>
38#include <mach/board.h> 38#include <plat/board.h>
39#include <mach/common.h> 39#include <plat/common.h>
40#include <mach/keypad.h> 40#include <plat/keypad.h>
41#include <mach/menelaus.h> 41#include <plat/menelaus.h>
42#include <mach/dma.h> 42#include <plat/dma.h>
43#include <mach/gpmc.h> 43#include <plat/gpmc.h>
44 44
45#define H4_FLASH_CS 0 45#define H4_FLASH_CS 0
46#define H4_SMC91X_CS 1 46#define H4_SMC91X_CS 1
@@ -376,7 +376,7 @@ static void __init omap_h4_map_io(void)
376MACHINE_START(OMAP_H4, "OMAP2420 H4 board") 376MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
377 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 377 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
378 .phys_io = 0x48000000, 378 .phys_io = 0x48000000,
379 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 379 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
380 .boot_params = 0x80000100, 380 .boot_params = 0x80000100,
381 .map_io = omap_h4_map_io, 381 .map_io = omap_h4_map_io,
382 .init_irq = omap_h4_init_irq, 382 .init_irq = omap_h4_init_irq,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d57ec2f4d0a9..c062238fe881 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -33,15 +33,15 @@
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <mach/mcspi.h> 36#include <plat/mcspi.h>
37#include <mach/gpio.h> 37#include <mach/gpio.h>
38#include <mach/board.h> 38#include <plat/board.h>
39#include <mach/common.h> 39#include <plat/common.h>
40#include <mach/gpmc.h> 40#include <plat/gpmc.h>
41 41
42#include <asm/delay.h> 42#include <asm/delay.h>
43#include <mach/control.h> 43#include <plat/control.h>
44#include <mach/usb.h> 44#include <plat/usb.h>
45 45
46#include "mmc-twl4030.h" 46#include "mmc-twl4030.h"
47 47
@@ -399,7 +399,7 @@ static void __init omap_ldp_map_io(void)
399 399
400MACHINE_START(OMAP_LDP, "OMAP LDP board") 400MACHINE_START(OMAP_LDP, "OMAP LDP board")
401 .phys_io = 0x48000000, 401 .phys_io = 0x48000000,
402 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 402 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
403 .boot_params = 0x80000100, 403 .boot_params = 0x80000100,
404 .map_io = omap_ldp_map_io, 404 .map_io = omap_ldp_map_io,
405 .init_irq = omap_ldp_init_irq, 405 .init_irq = omap_ldp_init_irq,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8341632d260b..764ab1ed576d 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -23,12 +23,12 @@
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25 25
26#include <mach/board.h> 26#include <plat/board.h>
27#include <mach/common.h> 27#include <plat/common.h>
28#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/mcspi.h> 29#include <plat/mcspi.h>
30#include <mach/onenand.h> 30#include <plat/onenand.h>
31#include <mach/serial.h> 31#include <plat/serial.h>
32 32
33static struct omap2_mcspi_device_config p54spi_mcspi_config = { 33static struct omap2_mcspi_device_config p54spi_mcspi_config = {
34 .turbo_mode = 0, 34 .turbo_mode = 0,
@@ -121,7 +121,7 @@ static void __init n8x0_init_machine(void)
121 121
122MACHINE_START(NOKIA_N800, "Nokia N800") 122MACHINE_START(NOKIA_N800, "Nokia N800")
123 .phys_io = 0x48000000, 123 .phys_io = 0x48000000,
124 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 124 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
125 .boot_params = 0x80000100, 125 .boot_params = 0x80000100,
126 .map_io = n8x0_map_io, 126 .map_io = n8x0_map_io,
127 .init_irq = n8x0_init_irq, 127 .init_irq = n8x0_init_irq,
@@ -131,7 +131,7 @@ MACHINE_END
131 131
132MACHINE_START(NOKIA_N810, "Nokia N810") 132MACHINE_START(NOKIA_N810, "Nokia N810")
133 .phys_io = 0x48000000, 133 .phys_io = 0x48000000,
134 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 134 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
135 .boot_params = 0x80000100, 135 .boot_params = 0x80000100,
136 .map_io = n8x0_map_io, 136 .map_io = n8x0_map_io,
137 .init_irq = n8x0_init_irq, 137 .init_irq = n8x0_init_irq,
@@ -141,7 +141,7 @@ MACHINE_END
141 141
142MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") 142MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
143 .phys_io = 0x48000000, 143 .phys_io = 0x48000000,
144 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 144 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
145 .boot_params = 0x80000100, 145 .boot_params = 0x80000100,
146 .map_io = n8x0_map_io, 146 .map_io = n8x0_map_io,
147 .init_irq = n8x0_init_irq, 147 .init_irq = n8x0_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 08b0816afa61..76c727ed8da5 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -37,13 +37,13 @@
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
39 39
40#include <mach/board.h> 40#include <plat/board.h>
41#include <mach/common.h> 41#include <plat/common.h>
42#include <mach/gpmc.h> 42#include <plat/gpmc.h>
43#include <mach/nand.h> 43#include <plat/nand.h>
44#include <mach/mux.h> 44#include <plat/mux.h>
45#include <mach/usb.h> 45#include <plat/usb.h>
46#include <mach/timer-gp.h> 46#include <plat/timer-gp.h>
47 47
48#include "mmc-twl4030.h" 48#include "mmc-twl4030.h"
49 49
@@ -429,7 +429,7 @@ static void __init omap3_beagle_map_io(void)
429MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") 429MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
430 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ 430 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
431 .phys_io = 0x48000000, 431 .phys_io = 0x48000000,
432 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 432 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
433 .boot_params = 0x80000100, 433 .boot_params = 0x80000100,
434 .map_io = omap3_beagle_map_io, 434 .map_io = omap3_beagle_map_io,
435 .init_irq = omap3_beagle_init_irq, 435 .init_irq = omap3_beagle_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 4c4d7f8dbd72..522ff6288c6f 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -33,11 +33,11 @@
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35 35
36#include <mach/board.h> 36#include <plat/board.h>
37#include <mach/mux.h> 37#include <plat/mux.h>
38#include <mach/usb.h> 38#include <plat/usb.h>
39#include <mach/common.h> 39#include <plat/common.h>
40#include <mach/mcspi.h> 40#include <plat/mcspi.h>
41 41
42#include "sdram-micron-mt46h32m32lf-6.h" 42#include "sdram-micron-mt46h32m32lf-6.h"
43#include "mmc-twl4030.h" 43#include "mmc-twl4030.h"
@@ -324,7 +324,7 @@ static void __init omap3_evm_map_io(void)
324MACHINE_START(OMAP3EVM, "OMAP3 EVM") 324MACHINE_START(OMAP3EVM, "OMAP3 EVM")
325 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ 325 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
326 .phys_io = 0x48000000, 326 .phys_io = 0x48000000,
327 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 327 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
328 .boot_params = 0x80000100, 328 .boot_params = 0x80000100,
329 .map_io = omap3_evm_map_io, 329 .map_io = omap3_evm_map_io,
330 .init_irq = omap3_evm_init_irq, 330 .init_irq = omap3_evm_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 7519edb69155..7fb9023b4239 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -34,13 +34,13 @@
34#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
35#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36 36
37#include <mach/board.h> 37#include <plat/board.h>
38#include <mach/common.h> 38#include <plat/common.h>
39#include <mach/gpio.h> 39#include <mach/gpio.h>
40#include <mach/hardware.h> 40#include <mach/hardware.h>
41#include <mach/mcspi.h> 41#include <plat/mcspi.h>
42#include <mach/usb.h> 42#include <plat/usb.h>
43#include <mach/mux.h> 43#include <plat/mux.h>
44 44
45#include "sdram-micron-mt46h32m32lf-6.h" 45#include "sdram-micron-mt46h32m32lf-6.h"
46#include "mmc-twl4030.h" 46#include "mmc-twl4030.h"
@@ -412,7 +412,7 @@ static void __init omap3pandora_map_io(void)
412 412
413MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") 413MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
414 .phys_io = 0x48000000, 414 .phys_io = 0x48000000,
415 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 415 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
416 .boot_params = 0x80000100, 416 .boot_params = 0x80000100,
417 .map_io = omap3pandora_map_io, 417 .map_io = omap3pandora_map_io,
418 .init_irq = omap3pandora_init_irq, 418 .init_irq = omap3pandora_init_irq,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 9917d2fddc2f..461522c1bced 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -38,14 +38,14 @@
38#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
39#include <asm/mach/map.h> 39#include <asm/mach/map.h>
40 40
41#include <mach/board.h> 41#include <plat/board.h>
42#include <mach/common.h> 42#include <plat/common.h>
43#include <mach/gpio.h> 43#include <mach/gpio.h>
44#include <mach/gpmc.h> 44#include <plat/gpmc.h>
45#include <mach/hardware.h> 45#include <mach/hardware.h>
46#include <mach/nand.h> 46#include <plat/nand.h>
47#include <mach/mux.h> 47#include <plat/mux.h>
48#include <mach/usb.h> 48#include <plat/usb.h>
49 49
50#include "sdram-micron-mt46h32m32lf-6.h" 50#include "sdram-micron-mt46h32m32lf-6.h"
51#include "mmc-twl4030.h" 51#include "mmc-twl4030.h"
@@ -67,7 +67,7 @@
67#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ 67#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
68 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 68 defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
69 69
70#include <mach/mcspi.h> 70#include <plat/mcspi.h>
71#include <linux/spi/spi.h> 71#include <linux/spi/spi.h>
72#include <linux/spi/ads7846.h> 72#include <linux/spi/ads7846.h>
73 73
@@ -451,7 +451,7 @@ static void __init overo_map_io(void)
451 451
452MACHINE_START(OVERO, "Gumstix Overo") 452MACHINE_START(OVERO, "Gumstix Overo")
453 .phys_io = 0x48000000, 453 .phys_io = 0x48000000,
454 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 454 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
455 .boot_params = 0x80000100, 455 .boot_params = 0x80000100,
456 .map_io = overo_map_io, 456 .map_io = overo_map_io,
457 .init_irq = overo_init_irq, 457 .init_irq = overo_init_irq,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index e34d96a825e3..cf4583a5d284 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -22,14 +22,14 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/mmc/host.h> 23#include <linux/mmc/host.h>
24 24
25#include <mach/mcspi.h> 25#include <plat/mcspi.h>
26#include <mach/mux.h> 26#include <plat/mux.h>
27#include <mach/board.h> 27#include <plat/board.h>
28#include <mach/common.h> 28#include <plat/common.h>
29#include <mach/dma.h> 29#include <plat/dma.h>
30#include <mach/gpmc.h> 30#include <plat/gpmc.h>
31#include <mach/onenand.h> 31#include <plat/onenand.h>
32#include <mach/gpmc-smc91x.h> 32#include <plat/gpmc-smc91x.h>
33 33
34#include "mmc-twl4030.h" 34#include "mmc-twl4030.h"
35 35
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 78869a9a1cc2..f1e7e5bbf985 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -22,13 +22,13 @@
22#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
23#include <asm/mach/map.h> 23#include <asm/mach/map.h>
24 24
25#include <mach/mcspi.h> 25#include <plat/mcspi.h>
26#include <mach/mux.h> 26#include <plat/mux.h>
27#include <mach/board.h> 27#include <plat/board.h>
28#include <mach/common.h> 28#include <plat/common.h>
29#include <mach/dma.h> 29#include <plat/dma.h>
30#include <mach/gpmc.h> 30#include <plat/gpmc.h>
31#include <mach/usb.h> 31#include <plat/usb.h>
32 32
33static struct omap_lcd_config rx51_lcd_config = { 33static struct omap_lcd_config rx51_lcd_config = {
34 .ctrl_name = "internal", 34 .ctrl_name = "internal",
@@ -84,7 +84,7 @@ static void __init rx51_map_io(void)
84MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") 84MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
85 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ 85 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
86 .phys_io = 0x48000000, 86 .phys_io = 0x48000000,
87 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 87 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
88 .boot_params = 0x80000100, 88 .boot_params = 0x80000100,
89 .map_io = rx51_map_io, 89 .map_io = rx51_map_io,
90 .init_irq = rx51_init_irq, 90 .init_irq = rx51_init_irq,
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 1f13e2a1f322..91ecddc9057a 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -14,7 +14,7 @@
14#include <linux/smsc911x.h> 14#include <linux/smsc911x.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16 16
17#include <mach/gpmc.h> 17#include <plat/gpmc.h>
18 18
19#define ZOOM2_SMSC911X_CS 7 19#define ZOOM2_SMSC911X_CS 7
20#define ZOOM2_SMSC911X_GPIO 158 20#define ZOOM2_SMSC911X_GPIO 158
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 51e0b3ba5f3a..ea01a0fa07fb 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -21,8 +21,8 @@
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
23 23
24#include <mach/common.h> 24#include <plat/common.h>
25#include <mach/usb.h> 25#include <plat/usb.h>
26 26
27#include "mmc-twl4030.h" 27#include "mmc-twl4030.h"
28#include "sdram-micron-mt46h32m32lf-6.h" 28#include "sdram-micron-mt46h32m32lf-6.h"
@@ -282,7 +282,7 @@ static void __init omap_zoom2_map_io(void)
282 282
283MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") 283MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
284 .phys_io = 0x48000000, 284 .phys_io = 0x48000000,
285 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, 285 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
286 .boot_params = 0x80000100, 286 .boot_params = 0x80000100,
287 .map_io = omap_zoom2_map_io, 287 .map_io = omap_zoom2_map_io,
288 .init_irq = omap_zoom2_init_irq, 288 .init_irq = omap_zoom2_init_irq,
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f2a92d614f0f..4716206547ac 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -24,13 +24,13 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/bitops.h> 25#include <linux/bitops.h>
26 26
27#include <mach/clock.h> 27#include <plat/clock.h>
28#include <mach/clockdomain.h> 28#include <plat/clockdomain.h>
29#include <mach/cpu.h> 29#include <plat/cpu.h>
30#include <mach/prcm.h> 30#include <plat/prcm.h>
31#include <asm/div64.h> 31#include <asm/div64.h>
32 32
33#include <mach/sdrc.h> 33#include <plat/sdrc.h>
34#include "sdrc.h" 34#include "sdrc.h"
35#include "clock.h" 35#include "clock.h"
36#include "prm.h" 36#include "prm.h"
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 9ae7540f8af2..43b6bedaafd6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -16,7 +16,7 @@
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H 17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 18
19#include <mach/clock.h> 19#include <plat/clock.h>
20 20
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index e2dbedd581e8..e70e7e000eaa 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -28,13 +28,13 @@
28#include <linux/cpufreq.h> 28#include <linux/cpufreq.h>
29#include <linux/bitops.h> 29#include <linux/bitops.h>
30 30
31#include <mach/clock.h> 31#include <plat/clock.h>
32#include <mach/sram.h> 32#include <plat/sram.h>
33#include <mach/prcm.h> 33#include <plat/prcm.h>
34#include <asm/div64.h> 34#include <asm/div64.h>
35#include <asm/clkdev.h> 35#include <asm/clkdev.h>
36 36
37#include <mach/sdrc.h> 37#include <plat/sdrc.h>
38#include "clock.h" 38#include "clock.h"
39#include "prm.h" 39#include "prm.h"
40#include "prm-regbits-24xx.h" 40#include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 7c5c00df3c70..225c1a7385ee 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -27,13 +27,13 @@
27#include <linux/limits.h> 27#include <linux/limits.h>
28#include <linux/bitops.h> 28#include <linux/bitops.h>
29 29
30#include <mach/cpu.h> 30#include <plat/cpu.h>
31#include <mach/clock.h> 31#include <plat/clock.h>
32#include <mach/sram.h> 32#include <plat/sram.h>
33#include <asm/div64.h> 33#include <asm/div64.h>
34#include <asm/clkdev.h> 34#include <asm/clkdev.h>
35 35
36#include <mach/sdrc.h> 36#include <plat/sdrc.h>
37#include "clock.h" 37#include "clock.h"
38#include "prm.h" 38#include "prm.h"
39#include "prm-regbits-34xx.h" 39#include "prm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 9565c05bebd2..8fe1bcb23dd9 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -19,7 +19,7 @@
19#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 19#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 20#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
21 21
22#include <mach/control.h> 22#include <plat/control.h>
23 23
24#include "clock.h" 24#include "clock.h"
25#include "cm.h" 25#include "cm.h"
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 58aff8485df9..fcd82320a6a3 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -28,14 +28,14 @@
28 28
29#include <linux/bitops.h> 29#include <linux/bitops.h>
30 30
31#include <mach/clock.h> 31#include <plat/clock.h>
32 32
33#include "prm.h" 33#include "prm.h"
34#include "prm-regbits-24xx.h" 34#include "prm-regbits-24xx.h"
35#include "cm.h" 35#include "cm.h"
36 36
37#include <mach/powerdomain.h> 37#include <plat/powerdomain.h>
38#include <mach/clockdomain.h> 38#include <plat/clockdomain.h>
39 39
40/* clkdm_list contains all registered struct clockdomains */ 40/* clkdm_list contains all registered struct clockdomains */
41static LIST_HEAD(clkdm_list); 41static LIST_HEAD(clkdm_list);
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index fe319ae4ca0a..c4ee0761d908 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -10,7 +10,7 @@
10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H 10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H 11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
12 12
13#include <mach/clockdomain.h> 13#include <plat/clockdomain.h>
14 14
15/* 15/*
16 * OMAP2/3-common clockdomains 16 * OMAP2/3-common clockdomains
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index cfd0b726ba44..a2fcfcc253cc 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -17,11 +17,11 @@
17#include "prcm-common.h" 17#include "prcm-common.h"
18 18
19#define OMAP2420_CM_REGADDR(module, reg) \ 19#define OMAP2420_CM_REGADDR(module, reg) \
20 OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
21#define OMAP2430_CM_REGADDR(module, reg) \ 21#define OMAP2430_CM_REGADDR(module, reg) \
22 OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23#define OMAP34XX_CM_REGADDR(module, reg) \ 23#define OMAP34XX_CM_REGADDR(module, reg) \
24 OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
25 25
26/* 26/*
27 * Architecture-specific global CM registers 27 * Architecture-specific global CM registers
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 5f3aad977842..cdd1f35636dd 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,11 +15,127 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18#include <mach/common.h> 18#include <plat/common.h>
19#include <mach/control.h> 19#include <plat/control.h>
20#include <plat/sdrc.h>
21#include "cm-regbits-34xx.h"
22#include "prm-regbits-34xx.h"
23#include "cm.h"
24#include "prm.h"
25#include "sdrc.h"
20 26
21static void __iomem *omap2_ctrl_base; 27static void __iomem *omap2_ctrl_base;
22 28
29#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
30struct omap3_scratchpad {
31 u32 boot_config_ptr;
32 u32 public_restore_ptr;
33 u32 secure_ram_restore_ptr;
34 u32 sdrc_module_semaphore;
35 u32 prcm_block_offset;
36 u32 sdrc_block_offset;
37};
38
39struct omap3_scratchpad_prcm_block {
40 u32 prm_clksrc_ctrl;
41 u32 prm_clksel;
42 u32 cm_clksel_core;
43 u32 cm_clksel_wkup;
44 u32 cm_clken_pll;
45 u32 cm_autoidle_pll;
46 u32 cm_clksel1_pll;
47 u32 cm_clksel2_pll;
48 u32 cm_clksel3_pll;
49 u32 cm_clken_pll_mpu;
50 u32 cm_autoidle_pll_mpu;
51 u32 cm_clksel1_pll_mpu;
52 u32 cm_clksel2_pll_mpu;
53 u32 prcm_block_size;
54};
55
56struct omap3_scratchpad_sdrc_block {
57 u16 sysconfig;
58 u16 cs_cfg;
59 u16 sharing;
60 u16 err_type;
61 u32 dll_a_ctrl;
62 u32 dll_b_ctrl;
63 u32 power;
64 u32 cs_0;
65 u32 mcfg_0;
66 u16 mr_0;
67 u16 emr_1_0;
68 u16 emr_2_0;
69 u16 emr_3_0;
70 u32 actim_ctrla_0;
71 u32 actim_ctrlb_0;
72 u32 rfr_ctrl_0;
73 u32 cs_1;
74 u32 mcfg_1;
75 u16 mr_1;
76 u16 emr_1_1;
77 u16 emr_2_1;
78 u16 emr_3_1;
79 u32 actim_ctrla_1;
80 u32 actim_ctrlb_1;
81 u32 rfr_ctrl_1;
82 u16 dcdl_1_ctrl;
83 u16 dcdl_2_ctrl;
84 u32 flags;
85 u32 block_size;
86};
87
88void *omap3_secure_ram_storage;
89
90/*
91 * This is used to store ARM registers in SDRAM before attempting
92 * an MPU OFF. The save and restore happens from the SRAM sleep code.
93 * The address is stored in scratchpad, so that it can be used
94 * during the restore path.
95 */
96u32 omap3_arm_context[128];
97
98struct omap3_control_regs {
99 u32 sysconfig;
100 u32 devconf0;
101 u32 mem_dftrw0;
102 u32 mem_dftrw1;
103 u32 msuspendmux_0;
104 u32 msuspendmux_1;
105 u32 msuspendmux_2;
106 u32 msuspendmux_3;
107 u32 msuspendmux_4;
108 u32 msuspendmux_5;
109 u32 sec_ctrl;
110 u32 devconf1;
111 u32 csirxfe;
112 u32 iva2_bootaddr;
113 u32 iva2_bootmod;
114 u32 debobs_0;
115 u32 debobs_1;
116 u32 debobs_2;
117 u32 debobs_3;
118 u32 debobs_4;
119 u32 debobs_5;
120 u32 debobs_6;
121 u32 debobs_7;
122 u32 debobs_8;
123 u32 prog_io0;
124 u32 prog_io1;
125 u32 dss_dpll_spreading;
126 u32 core_dpll_spreading;
127 u32 per_dpll_spreading;
128 u32 usbhost_dpll_spreading;
129 u32 pbias_lite;
130 u32 temp_sensor;
131 u32 sramldo4;
132 u32 sramldo5;
133 u32 csi;
134};
135
136static struct omap3_control_regs control_context;
137#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
138
23#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 139#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
24 140
25void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 141void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset)
62 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 178 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
63} 179}
64 180
181#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
182/*
183 * Clears the scratchpad contents in case of cold boot-
184 * called during bootup
185 */
186void omap3_clear_scratchpad_contents(void)
187{
188 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
189 u32 *v_addr;
190 u32 offset = 0;
191 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
192 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
193 OMAP3430_GLOBAL_COLD_RST) {
194 for ( ; offset <= max_offset; offset += 0x4)
195 __raw_writel(0x0, (v_addr + offset));
196 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
197 OMAP3_PRM_RSTST_OFFSET);
198 }
199}
200
201/* Populate the scratchpad structure with restore structure */
202void omap3_save_scratchpad_contents(void)
203{
204 void * __iomem scratchpad_address;
205 u32 arm_context_addr;
206 struct omap3_scratchpad scratchpad_contents;
207 struct omap3_scratchpad_prcm_block prcm_block_contents;
208 struct omap3_scratchpad_sdrc_block sdrc_block_contents;
209
210 /* Populate the Scratchpad contents */
211 scratchpad_contents.boot_config_ptr = 0x0;
212 if (omap_rev() != OMAP3430_REV_ES3_0 &&
213 omap_rev() != OMAP3430_REV_ES3_1)
214 scratchpad_contents.public_restore_ptr =
215 virt_to_phys(get_restore_pointer());
216 else
217 scratchpad_contents.public_restore_ptr =
218 virt_to_phys(get_es3_restore_pointer());
219 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
220 scratchpad_contents.secure_ram_restore_ptr = 0x0;
221 else
222 scratchpad_contents.secure_ram_restore_ptr =
223 (u32) __pa(omap3_secure_ram_storage);
224 scratchpad_contents.sdrc_module_semaphore = 0x0;
225 scratchpad_contents.prcm_block_offset = 0x2C;
226 scratchpad_contents.sdrc_block_offset = 0x64;
227
228 /* Populate the PRCM block contents */
229 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
230 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
231 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
232 OMAP3_PRM_CLKSEL_OFFSET);
233 prcm_block_contents.cm_clksel_core =
234 cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
235 prcm_block_contents.cm_clksel_wkup =
236 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
237 prcm_block_contents.cm_clken_pll =
238 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
239 prcm_block_contents.cm_autoidle_pll =
240 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
241 prcm_block_contents.cm_clksel1_pll =
242 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
243 prcm_block_contents.cm_clksel2_pll =
244 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
245 prcm_block_contents.cm_clksel3_pll =
246 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
247 prcm_block_contents.cm_clken_pll_mpu =
248 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
249 prcm_block_contents.cm_autoidle_pll_mpu =
250 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
251 prcm_block_contents.cm_clksel1_pll_mpu =
252 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
253 prcm_block_contents.cm_clksel2_pll_mpu =
254 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
255 prcm_block_contents.prcm_block_size = 0x0;
256
257 /* Populate the SDRC block contents */
258 sdrc_block_contents.sysconfig =
259 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
260 sdrc_block_contents.cs_cfg =
261 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
262 sdrc_block_contents.sharing =
263 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
264 sdrc_block_contents.err_type =
265 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
266 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
267 sdrc_block_contents.dll_b_ctrl = 0x0;
268 /*
269 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
270 * be programed to issue automatic self refresh on timeout
271 * of AUTO_CNT = 1 prior to any transition to OFF mode.
272 */
273 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
274 && (omap_rev() >= OMAP3430_REV_ES3_0))
275 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
276 ~(SDRC_POWER_AUTOCOUNT_MASK|
277 SDRC_POWER_CLKCTRL_MASK)) |
278 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
279 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
280 else
281 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
282
283 sdrc_block_contents.cs_0 = 0x0;
284 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
285 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
286 sdrc_block_contents.emr_1_0 = 0x0;
287 sdrc_block_contents.emr_2_0 = 0x0;
288 sdrc_block_contents.emr_3_0 = 0x0;
289 sdrc_block_contents.actim_ctrla_0 =
290 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
291 sdrc_block_contents.actim_ctrlb_0 =
292 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
293 sdrc_block_contents.rfr_ctrl_0 =
294 sdrc_read_reg(SDRC_RFR_CTRL_0);
295 sdrc_block_contents.cs_1 = 0x0;
296 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
297 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
298 sdrc_block_contents.emr_1_1 = 0x0;
299 sdrc_block_contents.emr_2_1 = 0x0;
300 sdrc_block_contents.emr_3_1 = 0x0;
301 sdrc_block_contents.actim_ctrla_1 =
302 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
303 sdrc_block_contents.actim_ctrlb_1 =
304 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
305 sdrc_block_contents.rfr_ctrl_1 =
306 sdrc_read_reg(SDRC_RFR_CTRL_1);
307 sdrc_block_contents.dcdl_1_ctrl = 0x0;
308 sdrc_block_contents.dcdl_2_ctrl = 0x0;
309 sdrc_block_contents.flags = 0x0;
310 sdrc_block_contents.block_size = 0x0;
311
312 arm_context_addr = virt_to_phys(omap3_arm_context);
313
314 /* Copy all the contents to the scratchpad location */
315 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
316 memcpy_toio(scratchpad_address, &scratchpad_contents,
317 sizeof(scratchpad_contents));
318 /* Scratchpad contents being 32 bits, a divide by 4 done here */
319 memcpy_toio(scratchpad_address +
320 scratchpad_contents.prcm_block_offset,
321 &prcm_block_contents, sizeof(prcm_block_contents));
322 memcpy_toio(scratchpad_address +
323 scratchpad_contents.sdrc_block_offset,
324 &sdrc_block_contents, sizeof(sdrc_block_contents));
325 /*
326 * Copies the address of the location in SDRAM where ARM
327 * registers get saved during a MPU OFF transition.
328 */
329 memcpy_toio(scratchpad_address +
330 scratchpad_contents.sdrc_block_offset +
331 sizeof(sdrc_block_contents), &arm_context_addr, 4);
332}
333
334void omap3_control_save_context(void)
335{
336 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
337 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
338 control_context.mem_dftrw0 =
339 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
340 control_context.mem_dftrw1 =
341 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
342 control_context.msuspendmux_0 =
343 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
344 control_context.msuspendmux_1 =
345 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
346 control_context.msuspendmux_2 =
347 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
348 control_context.msuspendmux_3 =
349 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
350 control_context.msuspendmux_4 =
351 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
352 control_context.msuspendmux_5 =
353 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
354 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
355 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
356 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
357 control_context.iva2_bootaddr =
358 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
359 control_context.iva2_bootmod =
360 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
361 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
362 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
363 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
364 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
365 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
366 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
367 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
368 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
369 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
370 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
371 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
372 control_context.dss_dpll_spreading =
373 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
374 control_context.core_dpll_spreading =
375 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
376 control_context.per_dpll_spreading =
377 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
378 control_context.usbhost_dpll_spreading =
379 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
380 control_context.pbias_lite =
381 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
382 control_context.temp_sensor =
383 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
384 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
385 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
386 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
387 return;
388}
389
390void omap3_control_restore_context(void)
391{
392 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
393 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
394 omap_ctrl_writel(control_context.mem_dftrw0,
395 OMAP343X_CONTROL_MEM_DFTRW0);
396 omap_ctrl_writel(control_context.mem_dftrw1,
397 OMAP343X_CONTROL_MEM_DFTRW1);
398 omap_ctrl_writel(control_context.msuspendmux_0,
399 OMAP2_CONTROL_MSUSPENDMUX_0);
400 omap_ctrl_writel(control_context.msuspendmux_1,
401 OMAP2_CONTROL_MSUSPENDMUX_1);
402 omap_ctrl_writel(control_context.msuspendmux_2,
403 OMAP2_CONTROL_MSUSPENDMUX_2);
404 omap_ctrl_writel(control_context.msuspendmux_3,
405 OMAP2_CONTROL_MSUSPENDMUX_3);
406 omap_ctrl_writel(control_context.msuspendmux_4,
407 OMAP2_CONTROL_MSUSPENDMUX_4);
408 omap_ctrl_writel(control_context.msuspendmux_5,
409 OMAP2_CONTROL_MSUSPENDMUX_5);
410 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
411 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
412 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
413 omap_ctrl_writel(control_context.iva2_bootaddr,
414 OMAP343X_CONTROL_IVA2_BOOTADDR);
415 omap_ctrl_writel(control_context.iva2_bootmod,
416 OMAP343X_CONTROL_IVA2_BOOTMOD);
417 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
418 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
419 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
420 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
421 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
422 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
423 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
424 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
425 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
426 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
427 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
428 omap_ctrl_writel(control_context.dss_dpll_spreading,
429 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
430 omap_ctrl_writel(control_context.core_dpll_spreading,
431 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
432 omap_ctrl_writel(control_context.per_dpll_spreading,
433 OMAP343X_CONTROL_PER_DPLL_SPREADING);
434 omap_ctrl_writel(control_context.usbhost_dpll_spreading,
435 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
436 omap_ctrl_writel(control_context.pbias_lite,
437 OMAP343X_CONTROL_PBIAS_LITE);
438 omap_ctrl_writel(control_context.temp_sensor,
439 OMAP343X_CONTROL_TEMP_SENSOR);
440 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
441 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
442 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
443 return;
444}
445#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
new file mode 100644
index 000000000000..a26d6a08ae3f
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -0,0 +1,318 @@
1/*
2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
3 *
4 * OMAP3 CPU IDLE Routines
5 *
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
11 *
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
14 *
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
17 *
18 * Based on pm.c for omap2
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
23 */
24
25#include <linux/sched.h>
26#include <linux/cpuidle.h>
27
28#include <plat/prcm.h>
29#include <plat/irqs.h>
30#include <plat/powerdomain.h>
31#include <plat/clockdomain.h>
32#include <plat/control.h>
33#include <plat/serial.h>
34
35#include "pm.h"
36
37#ifdef CONFIG_CPU_IDLE
38
39#define OMAP3_MAX_STATES 7
40#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
41#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
42#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
43#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
44#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
45#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
46#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
47
48struct omap3_processor_cx {
49 u8 valid;
50 u8 type;
51 u32 sleep_latency;
52 u32 wakeup_latency;
53 u32 mpu_state;
54 u32 core_state;
55 u32 threshold;
56 u32 flags;
57};
58
59struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
60struct omap3_processor_cx current_cx_state;
61struct powerdomain *mpu_pd, *core_pd;
62
63static int omap3_idle_bm_check(void)
64{
65 if (!omap3_can_sleep())
66 return 1;
67 return 0;
68}
69
70static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
71 struct clockdomain *clkdm)
72{
73 omap2_clkdm_allow_idle(clkdm);
74 return 0;
75}
76
77static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
78 struct clockdomain *clkdm)
79{
80 omap2_clkdm_deny_idle(clkdm);
81 return 0;
82}
83
84/**
85 * omap3_enter_idle - Programs OMAP3 to enter the specified state
86 * @dev: cpuidle device
87 * @state: The target state to be programmed
88 *
89 * Called from the CPUidle framework to program the device to the
90 * specified target state selected by the governor.
91 */
92static int omap3_enter_idle(struct cpuidle_device *dev,
93 struct cpuidle_state *state)
94{
95 struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
96 struct timespec ts_preidle, ts_postidle, ts_idle;
97 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
98
99 current_cx_state = *cx;
100
101 /* Used to keep track of the total time in idle */
102 getnstimeofday(&ts_preidle);
103
104 local_irq_disable();
105 local_fiq_disable();
106
107 if (!enable_off_mode) {
108 if (mpu_state < PWRDM_POWER_RET)
109 mpu_state = PWRDM_POWER_RET;
110 if (core_state < PWRDM_POWER_RET)
111 core_state = PWRDM_POWER_RET;
112 }
113
114 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
115 pwrdm_set_next_pwrst(core_pd, core_state);
116
117 if (omap_irq_pending() || need_resched())
118 goto return_sleep_time;
119
120 if (cx->type == OMAP3_STATE_C1) {
121 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
122 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
123 }
124
125 /* Execute ARM wfi */
126 omap_sram_idle();
127
128 if (cx->type == OMAP3_STATE_C1) {
129 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
130 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
131 }
132
133return_sleep_time:
134 getnstimeofday(&ts_postidle);
135 ts_idle = timespec_sub(ts_postidle, ts_preidle);
136
137 local_irq_enable();
138 local_fiq_enable();
139
140 return (u32)timespec_to_ns(&ts_idle)/1000;
141}
142
143/**
144 * omap3_enter_idle_bm - Checks for any bus activity
145 * @dev: cpuidle device
146 * @state: The target state to be programmed
147 *
148 * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
149 * function checks for any pending activity and then programs the
150 * device to the specified or a safer state.
151 */
152static int omap3_enter_idle_bm(struct cpuidle_device *dev,
153 struct cpuidle_state *state)
154{
155 struct cpuidle_state *new_state = state;
156
157 if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
158 BUG_ON(!dev->safe_state);
159 new_state = dev->safe_state;
160 }
161
162 dev->last_state = new_state;
163 return omap3_enter_idle(dev, new_state);
164}
165
166DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
167
168/* omap3_init_power_states - Initialises the OMAP3 specific C states.
169 *
170 * Below is the desciption of each C state.
171 * C1 . MPU WFI + Core active
172 * C2 . MPU WFI + Core inactive
173 * C3 . MPU CSWR + Core inactive
174 * C4 . MPU OFF + Core inactive
175 * C5 . MPU CSWR + Core CSWR
176 * C6 . MPU OFF + Core CSWR
177 * C7 . MPU OFF + Core OFF
178 */
179void omap_init_power_states(void)
180{
181 /* C1 . MPU WFI + Core active */
182 omap3_power_states[OMAP3_STATE_C1].valid = 1;
183 omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
184 omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
185 omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
186 omap3_power_states[OMAP3_STATE_C1].threshold = 5;
187 omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
188 omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
189 omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
190
191 /* C2 . MPU WFI + Core inactive */
192 omap3_power_states[OMAP3_STATE_C2].valid = 1;
193 omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
194 omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
195 omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
196 omap3_power_states[OMAP3_STATE_C2].threshold = 30;
197 omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
198 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
199 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
200
201 /* C3 . MPU CSWR + Core inactive */
202 omap3_power_states[OMAP3_STATE_C3].valid = 1;
203 omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
204 omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
205 omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
206 omap3_power_states[OMAP3_STATE_C3].threshold = 300;
207 omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
208 omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
209 omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
210 CPUIDLE_FLAG_CHECK_BM;
211
212 /* C4 . MPU OFF + Core inactive */
213 omap3_power_states[OMAP3_STATE_C4].valid = 1;
214 omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
215 omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
216 omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
217 omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
218 omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
219 omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
220 omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
221 CPUIDLE_FLAG_CHECK_BM;
222
223 /* C5 . MPU CSWR + Core CSWR*/
224 omap3_power_states[OMAP3_STATE_C5].valid = 1;
225 omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
226 omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
227 omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
228 omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
229 omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
230 omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
231 omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
232 CPUIDLE_FLAG_CHECK_BM;
233
234 /* C6 . MPU OFF + Core CSWR */
235 omap3_power_states[OMAP3_STATE_C6].valid = 1;
236 omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
237 omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
238 omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
239 omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
240 omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
241 omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
242 omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
243 CPUIDLE_FLAG_CHECK_BM;
244
245 /* C7 . MPU OFF + Core OFF */
246 omap3_power_states[OMAP3_STATE_C7].valid = 1;
247 omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
248 omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
249 omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
250 omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
251 omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
252 omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
253 omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
254 CPUIDLE_FLAG_CHECK_BM;
255}
256
257struct cpuidle_driver omap3_idle_driver = {
258 .name = "omap3_idle",
259 .owner = THIS_MODULE,
260};
261
262/**
263 * omap3_idle_init - Init routine for OMAP3 idle
264 *
265 * Registers the OMAP3 specific cpuidle driver with the cpuidle
266 * framework with the valid set of states.
267 */
268int __init omap3_idle_init(void)
269{
270 int i, count = 0;
271 struct omap3_processor_cx *cx;
272 struct cpuidle_state *state;
273 struct cpuidle_device *dev;
274
275 mpu_pd = pwrdm_lookup("mpu_pwrdm");
276 core_pd = pwrdm_lookup("core_pwrdm");
277
278 omap_init_power_states();
279 cpuidle_register_driver(&omap3_idle_driver);
280
281 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
282
283 for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
284 cx = &omap3_power_states[i];
285 state = &dev->states[count];
286
287 if (!cx->valid)
288 continue;
289 cpuidle_set_statedata(state, cx);
290 state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
291 state->target_residency = cx->threshold;
292 state->flags = cx->flags;
293 state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
294 omap3_enter_idle_bm : omap3_enter_idle;
295 if (cx->type == OMAP3_STATE_C1)
296 dev->safe_state = state;
297 sprintf(state->name, "C%d", count+1);
298 count++;
299 }
300
301 if (!count)
302 return -EINVAL;
303 dev->state_count = count;
304
305 if (cpuidle_register_device(dev)) {
306 printk(KERN_ERR "%s: CPUidle register device failed\n",
307 __func__);
308 return -EIO;
309 }
310
311 return 0;
312}
313#else
314int __init omap3_idle_init(void)
315{
316 return 0;
317}
318#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index faf7a1e0c525..7d4513b619f2 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -20,12 +20,12 @@
20#include <asm/mach-types.h> 20#include <asm/mach-types.h>
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22 22
23#include <mach/control.h> 23#include <plat/control.h>
24#include <mach/tc.h> 24#include <plat/tc.h>
25#include <mach/board.h> 25#include <plat/board.h>
26#include <mach/mux.h> 26#include <plat/mux.h>
27#include <mach/gpio.h> 27#include <mach/gpio.h>
28#include <mach/mmc.h> 28#include <plat/mmc.h>
29 29
30#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 30#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
31 31
@@ -250,7 +250,7 @@ static inline void omap_init_sti(void) {}
250 250
251#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) 251#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
252 252
253#include <mach/mcspi.h> 253#include <plat/mcspi.h>
254 254
255#define OMAP2_MCSPI1_BASE 0x48098000 255#define OMAP2_MCSPI1_BASE 0x48098000
256#define OMAP2_MCSPI2_BASE 0x4809a000 256#define OMAP2_MCSPI2_BASE 0x4809a000
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 54fec53a48e7..7bb69220adfa 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -17,9 +17,9 @@
17 17
18#include <asm/mach/flash.h> 18#include <asm/mach/flash.h>
19 19
20#include <mach/onenand.h> 20#include <plat/onenand.h>
21#include <mach/board.h> 21#include <plat/board.h>
22#include <mach/gpmc.h> 22#include <plat/gpmc.h>
23 23
24static struct omap_onenand_platform_data *gpmc_onenand_data; 24static struct omap_onenand_platform_data *gpmc_onenand_data;
25 25
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index df99d31d8b64..6083e21b3be6 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -17,9 +17,9 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/smc91x.h> 18#include <linux/smc91x.h>
19 19
20#include <mach/board.h> 20#include <plat/board.h>
21#include <mach/gpmc.h> 21#include <plat/gpmc.h>
22#include <mach/gpmc-smc91x.h> 22#include <plat/gpmc-smc91x.h>
23 23
24static struct omap_smc91x_platform_data *gpmc_cfg; 24static struct omap_smc91x_platform_data *gpmc_cfg;
25 25
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f3c992e29651..e86f5ca180ea 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,9 +24,9 @@
24#include <linux/module.h> 24#include <linux/module.h>
25 25
26#include <asm/mach-types.h> 26#include <asm/mach-types.h>
27#include <mach/gpmc.h> 27#include <plat/gpmc.h>
28 28
29#include <mach/sdrc.h> 29#include <plat/sdrc.h>
30 30
31/* GPMC register offsets */ 31/* GPMC register offsets */
32#define GPMC_REVISION 0x00 32#define GPMC_REVISION 0x00
@@ -62,6 +62,33 @@
62#define ENABLE_PREFETCH (0x1 << 7) 62#define ENABLE_PREFETCH (0x1 << 7)
63#define DMA_MPU_MODE 2 63#define DMA_MPU_MODE 2
64 64
65/* Structure to save gpmc cs context */
66struct gpmc_cs_config {
67 u32 config1;
68 u32 config2;
69 u32 config3;
70 u32 config4;
71 u32 config5;
72 u32 config6;
73 u32 config7;
74 int is_valid;
75};
76
77/*
78 * Structure to save/restore gpmc context
79 * to support core off on OMAP3
80 */
81struct omap3_gpmc_regs {
82 u32 sysconfig;
83 u32 irqenable;
84 u32 timeout_ctrl;
85 u32 config;
86 u32 prefetch_config1;
87 u32 prefetch_config2;
88 u32 prefetch_control;
89 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
90};
91
65static struct resource gpmc_mem_root; 92static struct resource gpmc_mem_root;
66static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 93static struct resource gpmc_cs_mem[GPMC_CS_NUM];
67static DEFINE_SPINLOCK(gpmc_mem_lock); 94static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -261,7 +288,7 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
261 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; 288 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
262 l &= ~(0x0f << 8); 289 l &= ~(0x0f << 8);
263 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; 290 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
264 l |= 1 << 6; /* CSVALID */ 291 l |= GPMC_CONFIG7_CSVALID;
265 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 292 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
266} 293}
267 294
@@ -270,7 +297,7 @@ static void gpmc_cs_disable_mem(int cs)
270 u32 l; 297 u32 l;
271 298
272 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 299 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
273 l &= ~(1 << 6); /* CSVALID */ 300 l &= ~GPMC_CONFIG7_CSVALID;
274 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 301 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
275} 302}
276 303
@@ -290,7 +317,7 @@ static int gpmc_cs_mem_enabled(int cs)
290 u32 l; 317 u32 l;
291 318
292 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 319 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
293 return l & (1 << 6); 320 return l & GPMC_CONFIG7_CSVALID;
294} 321}
295 322
296int gpmc_cs_set_reserved(int cs, int reserved) 323int gpmc_cs_set_reserved(int cs, int reserved)
@@ -516,3 +543,68 @@ void __init gpmc_init(void)
516 gpmc_write_reg(GPMC_SYSCONFIG, l); 543 gpmc_write_reg(GPMC_SYSCONFIG, l);
517 gpmc_mem_init(); 544 gpmc_mem_init();
518} 545}
546
547#ifdef CONFIG_ARCH_OMAP3
548static struct omap3_gpmc_regs gpmc_context;
549
550void omap3_gpmc_save_context()
551{
552 int i;
553 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
554 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
555 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
556 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
557 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
558 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
559 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
560 for (i = 0; i < GPMC_CS_NUM; i++) {
561 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
562 if (gpmc_context.cs_context[i].is_valid) {
563 gpmc_context.cs_context[i].config1 =
564 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
565 gpmc_context.cs_context[i].config2 =
566 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
567 gpmc_context.cs_context[i].config3 =
568 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
569 gpmc_context.cs_context[i].config4 =
570 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
571 gpmc_context.cs_context[i].config5 =
572 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
573 gpmc_context.cs_context[i].config6 =
574 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
575 gpmc_context.cs_context[i].config7 =
576 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
577 }
578 }
579}
580
581void omap3_gpmc_restore_context()
582{
583 int i;
584 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
585 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
586 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
587 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
588 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
589 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
590 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
591 for (i = 0; i < GPMC_CS_NUM; i++) {
592 if (gpmc_context.cs_context[i].is_valid) {
593 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
594 gpmc_context.cs_context[i].config1);
595 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
596 gpmc_context.cs_context[i].config2);
597 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
598 gpmc_context.cs_context[i].config3);
599 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
600 gpmc_context.cs_context[i].config4);
601 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
602 gpmc_context.cs_context[i].config5);
603 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
604 gpmc_context.cs_context[i].config6);
605 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
606 gpmc_context.cs_context[i].config7);
607 }
608 }
609}
610#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a98201cc265c..d28e6fec7e47 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -21,9 +21,9 @@
21 21
22#include <asm/cputype.h> 22#include <asm/cputype.h>
23 23
24#include <mach/common.h> 24#include <plat/common.h>
25#include <mach/control.h> 25#include <plat/control.h>
26#include <mach/cpu.h> 26#include <plat/cpu.h>
27 27
28static struct omap_chip_id omap_chip; 28static struct omap_chip_id omap_chip;
29static unsigned int omap_revision; 29static unsigned int omap_revision;
diff --git a/arch/arm/mach-omap2/include/mach/clkdev.h b/arch/arm/mach-omap2/include/mach/clkdev.h
new file mode 100644
index 000000000000..53b027441c56
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/clkdev.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/clkdev.h
3 */
4
5#include <plat/clkdev.h>
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
new file mode 100644
index 000000000000..e9f255df9163
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -0,0 +1,59 @@
1/* arch/arm/mach-omap2/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17#ifdef CONFIG_ARCH_OMAP2
18 moveq \rx, #0x48000000 @ physical base address
19 movne \rx, #0xfa000000 @ virtual base
20 orr \rx, \rx, #0x0006a000
21#ifdef CONFIG_OMAP_LL_DEBUG_UART2
22 add \rx, \rx, #0x00002000 @ UART 2
23#endif
24#ifdef CONFIG_OMAP_LL_DEBUG_UART3
25 add \rx, \rx, #0x00004000 @ UART 3
26#endif
27
28#elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
29 moveq \rx, #0x48000000 @ physical base address
30 movne \rx, #0xfa000000 @ virtual base
31 orr \rx, \rx, #0x0006a000
32#ifdef CONFIG_OMAP_LL_DEBUG_UART2
33 add \rx, \rx, #0x00002000 @ UART 2
34#endif
35#ifdef CONFIG_OMAP_LL_DEBUG_UART3
36 add \rx, \rx, #0x00fb0000 @ UART 3
37 add \rx, \rx, #0x00006000
38#endif
39#endif
40 .endm
41
42 .macro senduart,rd,rx
43 strb \rd, [\rx]
44 .endm
45
46 .macro busyuart,rd,rx
471001: ldrb \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
48 and \rd, \rd, #0x60
49 teq \rd, #0x60
50 beq 1002f
51 ldrb \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
52 and \rd, \rd, #0x60
53 teq \rd, #0x60
54 bne 1001b
551002:
56 .endm
57
58 .macro waituart,rd,rx
59 .endm
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
new file mode 100644
index 000000000000..c7f1720bf282
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -0,0 +1,124 @@
1/*
2 * arch/arm/plat-omap/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <mach/io.h>
15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
17
18#include <plat/omap24xx.h>
19#include <plat/omap34xx.h>
20
21/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
22#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
23#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
24#elif defined(CONFIG_ARCH_OMAP34XX)
25#define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
26#endif
27#if defined(CONFIG_ARCH_OMAP4)
28#include <plat/omap44xx.h>
29#endif
30#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
31#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
32
33 .macro disable_fiq
34 .endm
35
36 .macro get_irqnr_preamble, base, tmp
37 .endm
38
39 .macro arch_ret_to_user, tmp1, tmp2
40 .endm
41
42#ifndef CONFIG_ARCH_OMAP4
43 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
44 ldr \base, =OMAP2_VA_IC_BASE
45 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
46 cmp \irqnr, #0x0
47 bne 2222f
48 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
49 cmp \irqnr, #0x0
50 bne 2222f
51 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
52 cmp \irqnr, #0x0
532222:
54 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
55 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
56
57 .endm
58#else
59#define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
60
61 /*
62 * The interrupt numbering scheme is defined in the
63 * interrupt controller spec. To wit:
64 *
65 * Interrupts 0-15 are IPI
66 * 16-28 are reserved
67 * 29-31 are local. We allow 30 to be used for the watchdog.
68 * 32-1020 are global
69 * 1021-1022 are reserved
70 * 1023 is "spurious" (no interrupt)
71 *
72 * For now, we ignore all local interrupts so only return an
73 * interrupt if it's between 30 and 1020. The test_for_ipi
74 * routine below will pick up on IPIs.
75 * A simple read from the controller will tell us the number
76 * of the highest priority enabled interrupt.
77 * We then just need to check whether it is in the
78 * valid range for an IRQ (30-1020 inclusive).
79 */
80 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
81 ldr \base, =OMAP44XX_VA_GIC_CPU_BASE
82 ldr \irqstat, [\base, #GIC_CPU_INTACK]
83
84 ldr \tmp, =1021
85
86 bic \irqnr, \irqstat, #0x1c00
87
88 cmp \irqnr, #29
89 cmpcc \irqnr, \irqnr
90 cmpne \irqnr, \tmp
91 cmpcs \irqnr, \irqnr
92 .endm
93
94 /* We assume that irqstat (the raw value of the IRQ acknowledge
95 * register) is preserved from the macro above.
96 * If there is an IPI, we immediately signal end of interrupt
97 * on the controller, since this requires the original irqstat
98 * value which we won't easily be able to recreate later.
99 */
100
101 .macro test_for_ipi, irqnr, irqstat, base, tmp
102 bic \irqnr, \irqstat, #0x1c00
103 cmp \irqnr, #16
104 it cc
105 strcc \irqstat, [\base, #GIC_CPU_EOI]
106 it cs
107 cmpcs \irqnr, \irqnr
108 .endm
109
110 /* As above, this assumes that irqstat and base are preserved */
111
112 .macro test_for_ltirq, irqnr, irqstat, base, tmp
113 bic \irqnr, \irqstat, #0x1c00
114 mov \tmp, #0
115 cmp \irqnr, #29
116 itt eq
117 moveq \tmp, #1
118 streq \irqstat, [\base, #GIC_CPU_EOI]
119 cmp \tmp, #0
120 .endm
121#endif
122
123 .macro irq_prio_table
124 .endm
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
new file mode 100644
index 000000000000..be4d290d57ee
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/gpio.h
3 */
4
5#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
new file mode 100644
index 000000000000..78edf9d33f71
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/hardware.h
3 */
4
5#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
new file mode 100644
index 000000000000..fd78f31aa1ad
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/io.h
3 */
4
5#include <plat/io.h>
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
new file mode 100644
index 000000000000..44dab7725696
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/irqs.h
3 */
4
5#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h
new file mode 100644
index 000000000000..ca6d32a917dd
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/memory.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/memory.h
3 */
4
5#include <plat/memory.h>
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
new file mode 100644
index 000000000000..323675f21b69
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/smp.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/smp.h
3 */
4
5#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
new file mode 100644
index 000000000000..d488721ab90b
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/system.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/system.h
3 */
4
5#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/include/mach/timex.h b/arch/arm/mach-omap2/include/mach/timex.h
new file mode 100644
index 000000000000..de9f8fc40e7c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/timex.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/timex.h
3 */
4
5#include <plat/timex.h>
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
new file mode 100644
index 000000000000..78e0557bfd4e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/uncompress.h
3 */
4
5#include <plat/uncompress.h>
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
new file mode 100644
index 000000000000..9ce9b6e8ad23
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x38000000)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 56be87d13edb..59d28b2fd8c5 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,24 +27,24 @@
27 27
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29 29
30#include <mach/mux.h> 30#include <plat/mux.h>
31#include <mach/omapfb.h> 31#include <plat/omapfb.h>
32#include <mach/sram.h> 32#include <plat/sram.h>
33#include <mach/sdrc.h> 33#include <plat/sdrc.h>
34#include <mach/gpmc.h> 34#include <plat/gpmc.h>
35#include <mach/serial.h> 35#include <plat/serial.h>
36 36
37#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */ 37#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
38#include "clock.h" 38#include "clock.h"
39 39
40#include <mach/omap-pm.h> 40#include <plat/omap-pm.h>
41#include <mach/powerdomain.h> 41#include <plat/powerdomain.h>
42#include "powerdomains.h" 42#include "powerdomains.h"
43 43
44#include <mach/clockdomain.h> 44#include <plat/clockdomain.h>
45#include "clockdomains.h" 45#include "clockdomains.h"
46#endif 46#endif
47#include <mach/omap_hwmod.h> 47#include <plat/omap_hwmod.h>
48#include "omap_hwmod_2420.h" 48#include "omap_hwmod_2420.h"
49#include "omap_hwmod_2430.h" 49#include "omap_hwmod_2430.h"
50#include "omap_hwmod_34xx.h" 50#include "omap_hwmod_34xx.h"
@@ -203,6 +203,24 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
203 .type = MT_DEVICE, 203 .type = MT_DEVICE,
204 }, 204 },
205 { 205 {
206 .virtual = OMAP44XX_EMIF1_VIRT,
207 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
208 .length = OMAP44XX_EMIF1_SIZE,
209 .type = MT_DEVICE,
210 },
211 {
212 .virtual = OMAP44XX_EMIF2_VIRT,
213 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
214 .length = OMAP44XX_EMIF2_SIZE,
215 .type = MT_DEVICE,
216 },
217 {
218 .virtual = OMAP44XX_DMM_VIRT,
219 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
220 .length = OMAP44XX_DMM_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
206 .virtual = L4_PER_44XX_VIRT, 224 .virtual = L4_PER_44XX_VIRT,
207 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 225 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
208 .length = L4_PER_44XX_SIZE, 226 .length = L4_PER_44XX_SIZE,
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 4a0e1cd5c1f4..6f4b7cc8f4d1 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -17,7 +17,7 @@
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/stringify.h> 18#include <linux/stringify.h>
19 19
20#include <mach/iommu.h> 20#include <plat/iommu.h>
21 21
22/* 22/*
23 * omap2 architecture specific register bit definitions 23 * omap2 architecture specific register bit definitions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index b82863887f10..e9bc782fa414 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,10 @@
25#define INTC_SYSSTATUS 0x0014 25#define INTC_SYSSTATUS 0x0014
26#define INTC_SIR 0x0040 26#define INTC_SIR 0x0040
27#define INTC_CONTROL 0x0048 27#define INTC_CONTROL 0x0048
28#define INTC_PROTECTION 0x004C
29#define INTC_IDLE 0x0050
30#define INTC_THRESHOLD 0x0068
31#define INTC_MIR0 0x0084
28#define INTC_MIR_CLEAR0 0x0088 32#define INTC_MIR_CLEAR0 0x0088
29#define INTC_MIR_SET0 0x008c 33#define INTC_MIR_SET0 0x008c
30#define INTC_PENDING_IRQ0 0x0098 34#define INTC_PENDING_IRQ0 0x0098
@@ -48,6 +52,18 @@ static struct omap_irq_bank {
48 }, 52 },
49}; 53};
50 54
55/* Structure to save interrupt controller context */
56struct omap3_intc_regs {
57 u32 sysconfig;
58 u32 protection;
59 u32 idle;
60 u32 threshold;
61 u32 ilr[INTCPS_NR_IRQS];
62 u32 mir[INTCPS_NR_MIR_REGS];
63};
64
65static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
66
51/* INTC bank register get/set */ 67/* INTC bank register get/set */
52 68
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) 69static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -178,12 +194,20 @@ void __init omap_init_irq(void)
178 int i; 194 int i;
179 195
180 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 196 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
197 unsigned long base;
181 struct omap_irq_bank *bank = irq_banks + i; 198 struct omap_irq_bank *bank = irq_banks + i;
182 199
183 if (cpu_is_omap24xx()) 200 if (cpu_is_omap24xx())
184 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); 201 base = OMAP24XX_IC_BASE;
185 else if (cpu_is_omap34xx()) 202 else if (cpu_is_omap34xx())
186 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE); 203 base = OMAP34XX_IC_BASE;
204
205 /* Static mapping, never released */
206 bank->base_reg = ioremap(base, SZ_4K);
207 if (!bank->base_reg) {
208 printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
209 continue;
210 }
187 211
188 omap_irq_bank_init_one(bank); 212 omap_irq_bank_init_one(bank);
189 213
@@ -201,3 +225,53 @@ void __init omap_init_irq(void)
201 } 225 }
202} 226}
203 227
228#ifdef CONFIG_ARCH_OMAP3
229void omap_intc_save_context(void)
230{
231 int ind = 0, i = 0;
232 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
233 struct omap_irq_bank *bank = irq_banks + ind;
234 intc_context[ind].sysconfig =
235 intc_bank_read_reg(bank, INTC_SYSCONFIG);
236 intc_context[ind].protection =
237 intc_bank_read_reg(bank, INTC_PROTECTION);
238 intc_context[ind].idle =
239 intc_bank_read_reg(bank, INTC_IDLE);
240 intc_context[ind].threshold =
241 intc_bank_read_reg(bank, INTC_THRESHOLD);
242 for (i = 0; i < INTCPS_NR_IRQS; i++)
243 intc_context[ind].ilr[i] =
244 intc_bank_read_reg(bank, (0x100 + 0x4*i));
245 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
246 intc_context[ind].mir[i] =
247 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
248 (0x20 * i));
249 }
250}
251
252void omap_intc_restore_context(void)
253{
254 int ind = 0, i = 0;
255
256 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
257 struct omap_irq_bank *bank = irq_banks + ind;
258 intc_bank_write_reg(intc_context[ind].sysconfig,
259 bank, INTC_SYSCONFIG);
260 intc_bank_write_reg(intc_context[ind].sysconfig,
261 bank, INTC_SYSCONFIG);
262 intc_bank_write_reg(intc_context[ind].protection,
263 bank, INTC_PROTECTION);
264 intc_bank_write_reg(intc_context[ind].idle,
265 bank, INTC_IDLE);
266 intc_bank_write_reg(intc_context[ind].threshold,
267 bank, INTC_THRESHOLD);
268 for (i = 0; i < INTCPS_NR_IRQS; i++)
269 intc_bank_write_reg(intc_context[ind].ilr[i],
270 bank, (0x100 + 0x4*i));
271 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
272 intc_bank_write_reg(intc_context[ind].mir[i],
273 &irq_banks[0], INTC_MIR0 + (0x20 * i));
274 }
275 /* MIRs are saved and restore with other PRCM registers */
276}
277#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index ef57b38a56a4..5ba3aa69465e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -15,7 +15,7 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <mach/mailbox.h> 18#include <plat/mailbox.h>
19#include <mach/irqs.h> 19#include <mach/irqs.h>
20 20
21#define MAILBOX_REVISION 0x000 21#define MAILBOX_REVISION 0x000
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a846aa1ebb4d..baa451733850 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -18,10 +18,10 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19 19
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/dma.h> 21#include <plat/dma.h>
22#include <mach/mux.h> 22#include <plat/mux.h>
23#include <mach/cpu.h> 23#include <plat/cpu.h>
24#include <mach/mcbsp.h> 24#include <plat/mcbsp.h>
25 25
26static void omap2_mcbsp2_mux_setup(void) 26static void omap2_mcbsp2_mux_setup(void)
27{ 27{
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index c9c59a2db4e2..340391468909 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -20,9 +20,9 @@
20#include <linux/regulator/consumer.h> 20#include <linux/regulator/consumer.h>
21 21
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <mach/control.h> 23#include <plat/control.h>
24#include <mach/mmc.h> 24#include <plat/mmc.h>
25#include <mach/board.h> 25#include <plat/board.h>
26 26
27#include "mmc-twl4030.h" 27#include "mmc-twl4030.h"
28 28
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index b5fac32aae70..32c953e608db 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -30,8 +30,8 @@
30 30
31#include <asm/system.h> 31#include <asm/system.h>
32 32
33#include <mach/control.h> 33#include <plat/control.h>
34#include <mach/mux.h> 34#include <plat/mux.h>
35 35
36#ifdef CONFIG_OMAP_MUX 36#ifdef CONFIG_OMAP_MUX
37 37
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 48ee295db275..4890bcf4dadd 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,13 +24,14 @@
24#include <asm/localtimer.h> 24#include <asm/localtimer.h>
25#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <plat/common.h>
27 28
28/* Registers used for communicating startup information */ 29/* Registers used for communicating startup information */
29#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) 30static void __iomem *omap4_auxcoreboot_reg0;
30#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) 31static void __iomem *omap4_auxcoreboot_reg1;
31 32
32/* SCU base address */ 33/* SCU base address */
33static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; 34static void __iomem *scu_base;
34 35
35/* 36/*
36 * Use SCU config register to count number of cores 37 * Use SCU config register to count number of cores
@@ -53,8 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
53 * core (e.g. timer irq), then they will not have been enabled 54 * core (e.g. timer irq), then they will not have been enabled
54 * for us: do so 55 * for us: do so
55 */ 56 */
56 57 gic_cpu_init(0, gic_cpu_base_addr);
57 gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
58 58
59 /* 59 /*
60 * Synchronise with the boot thread. 60 * Synchronise with the boot thread.
@@ -79,7 +79,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
79 * the AuxCoreBoot1 register is updated with cpu state 79 * the AuxCoreBoot1 register is updated with cpu state
80 * A barrier is added to ensure that write buffer is drained 80 * A barrier is added to ensure that write buffer is drained
81 */ 81 */
82 __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); 82 __raw_writel(cpu, omap4_auxcoreboot_reg1);
83 smp_wmb(); 83 smp_wmb();
84 84
85 timeout = jiffies + (1 * HZ); 85 timeout = jiffies + (1 * HZ);
@@ -104,7 +104,7 @@ static void __init wakeup_secondary(void)
104 * A barrier is added to ensure that write buffer is drained 104 * A barrier is added to ensure that write buffer is drained
105 */ 105 */
106 __raw_writel(virt_to_phys(omap_secondary_startup), \ 106 __raw_writel(virt_to_phys(omap_secondary_startup), \
107 OMAP4_AUXCOREBOOT_REG0); 107 omap4_auxcoreboot_reg0);
108 smp_wmb(); 108 smp_wmb();
109 109
110 /* 110 /*
@@ -120,7 +120,13 @@ static void __init wakeup_secondary(void)
120 */ 120 */
121void __init smp_init_cpus(void) 121void __init smp_init_cpus(void)
122{ 122{
123 unsigned int i, ncores = get_core_count(); 123 unsigned int i, ncores;
124
125 /* Never released */
126 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
127 BUG_ON(!scu_base);
128
129 ncores = get_core_count();
124 130
125 for (i = 0; i < ncores; i++) 131 for (i = 0; i < ncores; i++)
126 set_cpu_possible(i, true); 132 set_cpu_possible(i, true);
@@ -130,6 +136,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
130{ 136{
131 unsigned int ncores = get_core_count(); 137 unsigned int ncores = get_core_count();
132 unsigned int cpu = smp_processor_id(); 138 unsigned int cpu = smp_processor_id();
139 void __iomem *omap4_wkupgen_base;
133 int i; 140 int i;
134 141
135 /* sanity check */ 142 /* sanity check */
@@ -161,6 +168,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
161 for (i = 0; i < max_cpus; i++) 168 for (i = 0; i < max_cpus; i++)
162 set_cpu_present(i, true); 169 set_cpu_present(i, true);
163 170
171 /* Never released */
172 omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
173 BUG_ON(!omap4_wkupgen_base);
174 omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
175 omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
176
164 if (max_cpus > 1) { 177 if (max_cpus > 1) {
165 /* 178 /*
166 * Enable the local timer or broadcast device for the 179 * Enable the local timer or broadcast device for the
diff --git a/arch/arm/mach-omap2/omap3-iommu.c b/arch/arm/mach-omap2/omap3-iommu.c
index 194189c746c2..6a9bf4f59d8a 100644
--- a/arch/arm/mach-omap2/omap3-iommu.c
+++ b/arch/arm/mach-omap2/omap3-iommu.c
@@ -12,7 +12,7 @@
12 12
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#include <mach/iommu.h> 15#include <plat/iommu.h>
16 16
17#define OMAP3_MMU1_BASE 0x480bd400 17#define OMAP3_MMU1_BASE 0x480bd400
18#define OMAP3_MMU2_BASE 0x5d000000 18#define OMAP3_MMU2_BASE 0x5d000000
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index d2e0f1c95961..633b216a8b26 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -45,11 +45,11 @@
45#include <linux/mutex.h> 45#include <linux/mutex.h>
46#include <linux/bootmem.h> 46#include <linux/bootmem.h>
47 47
48#include <mach/cpu.h> 48#include <plat/cpu.h>
49#include <mach/clockdomain.h> 49#include <plat/clockdomain.h>
50#include <mach/powerdomain.h> 50#include <plat/powerdomain.h>
51#include <mach/clock.h> 51#include <plat/clock.h>
52#include <mach/omap_hwmod.h> 52#include <plat/omap_hwmod.h>
53 53
54#include "cm.h" 54#include "cm.h"
55 55
@@ -496,6 +496,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
496 struct omap_hwmod_addr_space *mem; 496 struct omap_hwmod_addr_space *mem;
497 int i; 497 int i;
498 int found = 0; 498 int found = 0;
499 void __iomem *va_start;
499 500
500 if (!oh || oh->slaves_cnt == 0) 501 if (!oh || oh->slaves_cnt == 0)
501 return NULL; 502 return NULL;
@@ -509,16 +510,20 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
509 } 510 }
510 } 511 }
511 512
512 /* XXX use ioremap() instead? */ 513 if (found) {
513 514 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
514 if (found) 515 if (!va_start) {
516 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
517 return NULL;
518 }
515 pr_debug("omap_hwmod: %s: MPU register target at va %p\n", 519 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
516 oh->name, OMAP2_IO_ADDRESS(mem->pa_start)); 520 oh->name, va_start);
517 else 521 } else {
518 pr_debug("omap_hwmod: %s: no MPU register target found\n", 522 pr_debug("omap_hwmod: %s: no MPU register target found\n",
519 oh->name); 523 oh->name);
524 }
520 525
521 return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL; 526 return (found) ? va_start : NULL;
522} 527}
523 528
524/** 529/**
@@ -1148,6 +1153,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
1148 pr_debug("omap_hwmod: %s: unregistering\n", oh->name); 1153 pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
1149 1154
1150 mutex_lock(&omap_hwmod_mutex); 1155 mutex_lock(&omap_hwmod_mutex);
1156 iounmap(oh->_rt_va);
1151 list_del(&oh->node); 1157 list_del(&oh->node);
1152 mutex_unlock(&omap_hwmod_mutex); 1158 mutex_unlock(&omap_hwmod_mutex);
1153 1159
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420.h b/arch/arm/mach-omap2/omap_hwmod_2420.h
index 767e4965ac4e..a9ca1b99a301 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420.h
+++ b/arch/arm/mach-omap2/omap_hwmod_2420.h
@@ -16,10 +16,10 @@
16 16
17#ifdef CONFIG_ARCH_OMAP2420 17#ifdef CONFIG_ARCH_OMAP2420
18 18
19#include <mach/omap_hwmod.h> 19#include <plat/omap_hwmod.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/cpu.h> 21#include <plat/cpu.h>
22#include <mach/dma.h> 22#include <plat/dma.h>
23 23
24#include "prm-regbits-24xx.h" 24#include "prm-regbits-24xx.h"
25 25
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430.h b/arch/arm/mach-omap2/omap_hwmod_2430.h
index a412be6420ec..59a208bea6c2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430.h
+++ b/arch/arm/mach-omap2/omap_hwmod_2430.h
@@ -16,10 +16,10 @@
16 16
17#ifdef CONFIG_ARCH_OMAP2430 17#ifdef CONFIG_ARCH_OMAP2430
18 18
19#include <mach/omap_hwmod.h> 19#include <plat/omap_hwmod.h>
20#include <mach/irqs.h> 20#include <mach/irqs.h>
21#include <mach/cpu.h> 21#include <plat/cpu.h>
22#include <mach/dma.h> 22#include <plat/dma.h>
23 23
24#include "prm-regbits-24xx.h" 24#include "prm-regbits-24xx.h"
25 25
diff --git a/arch/arm/mach-omap2/omap_hwmod_34xx.h b/arch/arm/mach-omap2/omap_hwmod_34xx.h
index 1e069f831575..b6076b9c364e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_34xx.h
+++ b/arch/arm/mach-omap2/omap_hwmod_34xx.h
@@ -14,10 +14,10 @@
14 14
15#ifdef CONFIG_ARCH_OMAP34XX 15#ifdef CONFIG_ARCH_OMAP34XX
16 16
17#include <mach/omap_hwmod.h> 17#include <plat/omap_hwmod.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19#include <mach/cpu.h> 19#include <plat/cpu.h>
20#include <mach/dma.h> 20#include <plat/dma.h>
21 21
22#include "prm-regbits-34xx.h" 22#include "prm-regbits-34xx.h"
23 23
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 2fc4d6abbd0a..8baa30d2acfb 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -26,10 +26,10 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/module.h> 27#include <linux/module.h>
28 28
29#include <mach/clock.h> 29#include <plat/clock.h>
30#include <mach/board.h> 30#include <plat/board.h>
31#include <mach/powerdomain.h> 31#include <plat/powerdomain.h>
32#include <mach/clockdomain.h> 32#include <plat/clockdomain.h>
33 33
34#include "prm.h" 34#include "prm.h"
35#include "cm.h" 35#include "cm.h"
@@ -51,7 +51,8 @@ int omap2_pm_debug;
51 regs[reg_count++].val = __raw_readl(reg) 51 regs[reg_count++].val = __raw_readl(reg)
52#define DUMP_INTC_REG(reg, off) \ 52#define DUMP_INTC_REG(reg, off) \
53 regs[reg_count].name = #reg; \ 53 regs[reg_count].name = #reg; \
54 regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off))) 54 regs[reg_count++].val = \
55 __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
55 56
56static int __init pm_dbg_init(void); 57static int __init pm_dbg_init(void);
57 58
@@ -526,6 +527,29 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
526 return 0; 527 return 0;
527} 528}
528 529
530static int option_get(void *data, u64 *val)
531{
532 u32 *option = data;
533
534 *val = *option;
535
536 return 0;
537}
538
539static int option_set(void *data, u64 val)
540{
541 u32 *option = data;
542
543 *option = val;
544
545 if (option == &enable_off_mode)
546 omap3_pm_off_mode_enable(val);
547
548 return 0;
549}
550
551DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
552
529static int __init pm_dbg_init(void) 553static int __init pm_dbg_init(void)
530{ 554{
531 int i; 555 int i;
@@ -568,6 +592,12 @@ static int __init pm_dbg_init(void)
568 592
569 } 593 }
570 594
595 (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
596 &enable_off_mode, &pm_dbg_option_fops);
597 (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
598 &sleep_while_idle, &pm_dbg_option_fops);
599 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
600 &wakeup_timer_seconds, &pm_dbg_option_fops);
571 pm_dbg_init_done = 1; 601 pm_dbg_init_done = 1;
572 602
573 return 0; 603 return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8400f5768923..0bf345db7147 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,11 +11,24 @@
11#ifndef __ARCH_ARM_MACH_OMAP2_PM_H 11#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
12#define __ARCH_ARM_MACH_OMAP2_PM_H 12#define __ARCH_ARM_MACH_OMAP2_PM_H
13 13
14#include <mach/powerdomain.h> 14#include <plat/powerdomain.h>
15
16extern u32 enable_off_mode;
17extern u32 sleep_while_idle;
18
19extern void *omap3_secure_ram_storage;
20extern void omap3_pm_off_mode_enable(int);
21extern void omap_sram_idle(void);
22extern int omap3_can_sleep(void);
23extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
24extern int omap3_idle_init(void);
15 25
16extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); 26extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
17extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); 27extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
18 28
29extern u32 wakeup_timer_seconds;
30extern struct omap_dm_timer *gptimer_wakeup;
31
19#ifdef CONFIG_PM_DEBUG 32#ifdef CONFIG_PM_DEBUG
20extern void omap2_pm_dump(int mode, int resume, unsigned int us); 33extern void omap2_pm_dump(int mode, int resume, unsigned int us);
21extern int omap2_pm_debug; 34extern int omap2_pm_debug;
@@ -36,6 +49,7 @@ extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
36 void __iomem *sdrc_power); 49 void __iomem *sdrc_power);
37extern void omap34xx_cpu_suspend(u32 *addr, int save_state); 50extern void omap34xx_cpu_suspend(u32 *addr, int save_state);
38extern void save_secure_ram_context(u32 *addr); 51extern void save_secure_ram_context(u32 *addr);
52extern void omap3_save_scratchpad_contents(void);
39 53
40extern unsigned int omap24xx_idle_loop_suspend_sz; 54extern unsigned int omap24xx_idle_loop_suspend_sz;
41extern unsigned int omap34xx_suspend_sz; 55extern unsigned int omap34xx_suspend_sz;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index bff5c4e89742..cba05b9f041f 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -36,12 +36,12 @@
36#include <asm/mach-types.h> 36#include <asm/mach-types.h>
37 37
38#include <mach/irqs.h> 38#include <mach/irqs.h>
39#include <mach/clock.h> 39#include <plat/clock.h>
40#include <mach/sram.h> 40#include <plat/sram.h>
41#include <mach/control.h> 41#include <plat/control.h>
42#include <mach/mux.h> 42#include <plat/mux.h>
43#include <mach/dma.h> 43#include <plat/dma.h>
44#include <mach/board.h> 44#include <plat/board.h>
45 45
46#include "prm.h" 46#include "prm.h"
47#include "prm-regbits-24xx.h" 47#include "prm-regbits-24xx.h"
@@ -50,8 +50,8 @@
50#include "sdrc.h" 50#include "sdrc.h"
51#include "pm.h" 51#include "pm.h"
52 52
53#include <mach/powerdomain.h> 53#include <plat/powerdomain.h>
54#include <mach/clockdomain.h> 54#include <plat/clockdomain.h>
55 55
56static void (*omap2_sram_idle)(void); 56static void (*omap2_sram_idle)(void);
57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, 57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 89463190923a..81ed252a0f8a 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -5,6 +5,9 @@
5 * Tony Lindgren <tony@atomide.com> 5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander 6 * Jouni Hogander
7 * 7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8 * Copyright (C) 2005 Texas Instruments, Inc. 11 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com> 12 * Richard Woodruff <r-woodruff2@ti.com>
10 * 13 *
@@ -22,12 +25,20 @@
22#include <linux/list.h> 25#include <linux/list.h>
23#include <linux/err.h> 26#include <linux/err.h>
24#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/clk.h>
29
30#include <plat/sram.h>
31#include <plat/clockdomain.h>
32#include <plat/powerdomain.h>
33#include <plat/control.h>
34#include <plat/serial.h>
35#include <plat/sdrc.h>
36#include <plat/prcm.h>
37#include <plat/gpmc.h>
38#include <plat/dma.h>
39#include <plat/dmtimer.h>
25 40
26#include <mach/sram.h> 41#include <asm/tlbflush.h>
27#include <mach/clockdomain.h>
28#include <mach/powerdomain.h>
29#include <mach/control.h>
30#include <mach/serial.h>
31 42
32#include "cm.h" 43#include "cm.h"
33#include "cm-regbits-34xx.h" 44#include "cm-regbits-34xx.h"
@@ -35,6 +46,16 @@
35 46
36#include "prm.h" 47#include "prm.h"
37#include "pm.h" 48#include "pm.h"
49#include "sdrc.h"
50
51/* Scratchpad offsets */
52#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
53#define OMAP343X_TABLE_VALUE_OFFSET 0x30
54#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
55
56u32 enable_off_mode;
57u32 sleep_while_idle;
58u32 wakeup_timer_seconds;
38 59
39struct power_state { 60struct power_state {
40 struct powerdomain *pwrdm; 61 struct powerdomain *pwrdm;
@@ -49,7 +70,112 @@ static LIST_HEAD(pwrst_list);
49 70
50static void (*_omap_sram_idle)(u32 *addr, int save_state); 71static void (*_omap_sram_idle)(u32 *addr, int save_state);
51 72
52static struct powerdomain *mpu_pwrdm; 73static int (*_omap_save_secure_sram)(u32 *addr);
74
75static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
76static struct powerdomain *core_pwrdm, *per_pwrdm;
77static struct powerdomain *cam_pwrdm;
78
79static inline void omap3_per_save_context(void)
80{
81 omap_gpio_save_context();
82}
83
84static inline void omap3_per_restore_context(void)
85{
86 omap_gpio_restore_context();
87}
88
89static void omap3_enable_io_chain(void)
90{
91 int timeout = 0;
92
93 if (omap_rev() >= OMAP3430_REV_ES3_1) {
94 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
95 /* Do a readback to assure write has been done */
96 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
97
98 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
99 OMAP3430_ST_IO_CHAIN)) {
100 timeout++;
101 if (timeout > 1000) {
102 printk(KERN_ERR "Wake up daisy chain "
103 "activation failed.\n");
104 return;
105 }
106 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
107 WKUP_MOD, PM_WKST);
108 }
109 }
110}
111
112static void omap3_disable_io_chain(void)
113{
114 if (omap_rev() >= OMAP3430_REV_ES3_1)
115 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
116}
117
118static void omap3_core_save_context(void)
119{
120 u32 control_padconf_off;
121
122 /* Save the padconf registers */
123 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
124 control_padconf_off |= START_PADCONF_SAVE;
125 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
126 /* wait for the save to complete */
127 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
128 & PADCONF_SAVE_DONE)
129 ;
130 /* Save the Interrupt controller context */
131 omap_intc_save_context();
132 /* Save the GPMC context */
133 omap3_gpmc_save_context();
134 /* Save the system control module context, padconf already save above*/
135 omap3_control_save_context();
136 omap_dma_global_context_save();
137}
138
139static void omap3_core_restore_context(void)
140{
141 /* Restore the control module context, padconf restored by h/w */
142 omap3_control_restore_context();
143 /* Restore the GPMC context */
144 omap3_gpmc_restore_context();
145 /* Restore the interrupt controller context */
146 omap_intc_restore_context();
147 omap_dma_global_context_restore();
148}
149
150/*
151 * FIXME: This function should be called before entering off-mode after
152 * OMAP3 secure services have been accessed. Currently it is only called
153 * once during boot sequence, but this works as we are not using secure
154 * services.
155 */
156static void omap3_save_secure_ram_context(u32 target_mpu_state)
157{
158 u32 ret;
159
160 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
161 /*
162 * MPU next state must be set to POWER_ON temporarily,
163 * otherwise the WFI executed inside the ROM code
164 * will hang the system.
165 */
166 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
167 ret = _omap_save_secure_sram((u32 *)
168 __pa(omap3_secure_ram_storage));
169 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
170 /* Following is for error tracking, it should not happen */
171 if (ret) {
172 printk(KERN_ERR "save_secure_sram() returns %08x\n",
173 ret);
174 while (1)
175 ;
176 }
177 }
178}
53 179
54/* 180/*
55 * PRCM Interrupt Handler Helper Function 181 * PRCM Interrupt Handler Helper Function
@@ -161,7 +287,36 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
161 return IRQ_HANDLED; 287 return IRQ_HANDLED;
162} 288}
163 289
164static void omap_sram_idle(void) 290static void restore_control_register(u32 val)
291{
292 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
293}
294
295/* Function to restore the table entry that was modified for enabling MMU */
296static void restore_table_entry(void)
297{
298 u32 *scratchpad_address;
299 u32 previous_value, control_reg_value;
300 u32 *address;
301
302 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
303
304 /* Get address of entry that was modified */
305 address = (u32 *)__raw_readl(scratchpad_address +
306 OMAP343X_TABLE_ADDRESS_OFFSET);
307 /* Get the previous value which needs to be restored */
308 previous_value = __raw_readl(scratchpad_address +
309 OMAP343X_TABLE_VALUE_OFFSET);
310 address = __va(address);
311 *address = previous_value;
312 flush_tlb_all();
313 control_reg_value = __raw_readl(scratchpad_address
314 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
315 /* This will enable caches and prediction */
316 restore_control_register(control_reg_value);
317}
318
319void omap_sram_idle(void)
165{ 320{
166 /* Variable to tell what needs to be saved and restored 321 /* Variable to tell what needs to be saved and restored
167 * in omap_sram_idle*/ 322 * in omap_sram_idle*/
@@ -169,17 +324,32 @@ static void omap_sram_idle(void)
169 /* save_state = 1 => Only L1 and logic lost */ 324 /* save_state = 1 => Only L1 and logic lost */
170 /* save_state = 2 => Only L2 lost */ 325 /* save_state = 2 => Only L2 lost */
171 /* save_state = 3 => L1, L2 and logic lost */ 326 /* save_state = 3 => L1, L2 and logic lost */
172 int save_state = 0, mpu_next_state; 327 int save_state = 0;
328 int mpu_next_state = PWRDM_POWER_ON;
329 int per_next_state = PWRDM_POWER_ON;
330 int core_next_state = PWRDM_POWER_ON;
331 int core_prev_state, per_prev_state;
332 u32 sdrc_pwr = 0;
333 int per_state_modified = 0;
173 334
174 if (!_omap_sram_idle) 335 if (!_omap_sram_idle)
175 return; 336 return;
176 337
338 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
339 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
340 pwrdm_clear_all_prev_pwrst(core_pwrdm);
341 pwrdm_clear_all_prev_pwrst(per_pwrdm);
342
177 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); 343 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
178 switch (mpu_next_state) { 344 switch (mpu_next_state) {
345 case PWRDM_POWER_ON:
179 case PWRDM_POWER_RET: 346 case PWRDM_POWER_RET:
180 /* No need to save context */ 347 /* No need to save context */
181 save_state = 0; 348 save_state = 0;
182 break; 349 break;
350 case PWRDM_POWER_OFF:
351 save_state = 3;
352 break;
183 default: 353 default:
184 /* Invalid state */ 354 /* Invalid state */
185 printk(KERN_ERR "Invalid mpu state in sram_idle\n"); 355 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
@@ -187,68 +357,115 @@ static void omap_sram_idle(void)
187 } 357 }
188 pwrdm_pre_transition(); 358 pwrdm_pre_transition();
189 359
190 omap2_gpio_prepare_for_retention(); 360 /* NEON control */
191 omap_uart_prepare_idle(0); 361 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
192 omap_uart_prepare_idle(1); 362 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
193 omap_uart_prepare_idle(2); 363
364 /* PER */
365 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
366 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
367 if (per_next_state < PWRDM_POWER_ON) {
368 omap_uart_prepare_idle(2);
369 omap2_gpio_prepare_for_retention();
370 if (per_next_state == PWRDM_POWER_OFF) {
371 if (core_next_state == PWRDM_POWER_ON) {
372 per_next_state = PWRDM_POWER_RET;
373 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
374 per_state_modified = 1;
375 } else
376 omap3_per_save_context();
377 }
378 }
379
380 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
381 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
382
383 /* CORE */
384 if (core_next_state < PWRDM_POWER_ON) {
385 omap_uart_prepare_idle(0);
386 omap_uart_prepare_idle(1);
387 if (core_next_state == PWRDM_POWER_OFF) {
388 omap3_core_save_context();
389 omap3_prcm_save_context();
390 }
391 /* Enable IO-PAD and IO-CHAIN wakeups */
392 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
393 omap3_enable_io_chain();
394 }
395
396 /*
397 * On EMU/HS devices ROM code restores a SRDC value
398 * from scratchpad which has automatic self refresh on timeout
399 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
400 * Hence store/restore the SDRC_POWER register here.
401 */
402 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
403 omap_type() != OMAP2_DEVICE_TYPE_GP &&
404 core_next_state == PWRDM_POWER_OFF)
405 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
194 406
195 _omap_sram_idle(NULL, save_state); 407 /*
408 * omap3_arm_context is the location where ARM registers
409 * get saved. The restore path then reads from this
410 * location and restores them back.
411 */
412 _omap_sram_idle(omap3_arm_context, save_state);
196 cpu_init(); 413 cpu_init();
197 414
198 omap_uart_resume_idle(2); 415 /* Restore normal SDRC POWER settings */
199 omap_uart_resume_idle(1); 416 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
200 omap_uart_resume_idle(0); 417 omap_type() != OMAP2_DEVICE_TYPE_GP &&
201 omap2_gpio_resume_after_retention(); 418 core_next_state == PWRDM_POWER_OFF)
419 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
420
421 /* Restore table entry modified during MMU restoration */
422 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
423 restore_table_entry();
424
425 /* CORE */
426 if (core_next_state < PWRDM_POWER_ON) {
427 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
428 if (core_prev_state == PWRDM_POWER_OFF) {
429 omap3_core_restore_context();
430 omap3_prcm_restore_context();
431 omap3_sram_restore_context();
432 omap2_sms_restore_context();
433 }
434 omap_uart_resume_idle(0);
435 omap_uart_resume_idle(1);
436 if (core_next_state == PWRDM_POWER_OFF)
437 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
438 OMAP3430_GR_MOD,
439 OMAP3_PRM_VOLTCTRL_OFFSET);
440 }
202 441
203 pwrdm_post_transition(); 442 /* PER */
443 if (per_next_state < PWRDM_POWER_ON) {
444 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
445 if (per_prev_state == PWRDM_POWER_OFF)
446 omap3_per_restore_context();
447 omap2_gpio_resume_after_retention();
448 omap_uart_resume_idle(2);
449 if (per_state_modified)
450 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
451 }
204 452
205} 453 /* Disable IO-PAD and IO-CHAIN wakeup */
454 if (core_next_state < PWRDM_POWER_ON) {
455 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
456 omap3_disable_io_chain();
457 }
206 458
207/* 459 pwrdm_post_transition();
208 * Check if functional clocks are enabled before entering
209 * sleep. This function could be behind CONFIG_PM_DEBUG
210 * when all drivers are configuring their sysconfig registers
211 * properly and using their clocks properly.
212 */
213static int omap3_fclks_active(void)
214{
215 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
216 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
217 460
218 fck_core1 = cm_read_mod_reg(CORE_MOD, 461 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
219 CM_FCLKEN1);
220 if (omap_rev() > OMAP3430_REV_ES1_0) {
221 fck_core3 = cm_read_mod_reg(CORE_MOD,
222 OMAP3430ES2_CM_FCLKEN3);
223 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
224 CM_FCLKEN);
225 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
226 CM_FCLKEN);
227 } else
228 fck_sgx = cm_read_mod_reg(GFX_MOD,
229 OMAP3430ES2_CM_FCLKEN3);
230 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
231 CM_FCLKEN);
232 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
233 CM_FCLKEN);
234 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
235 CM_FCLKEN);
236
237 /* Ignore UART clocks. These are handled by UART core (serial.c) */
238 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
239 fck_per &= ~OMAP3430_EN_UART3;
240
241 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
242 fck_cam | fck_per | fck_usbhost)
243 return 1;
244 return 0;
245} 462}
246 463
247static int omap3_can_sleep(void) 464int omap3_can_sleep(void)
248{ 465{
249 if (!omap_uart_can_sleep()) 466 if (!sleep_while_idle)
250 return 0; 467 return 0;
251 if (omap3_fclks_active()) 468 if (!omap_uart_can_sleep())
252 return 0; 469 return 0;
253 return 1; 470 return 1;
254} 471}
@@ -256,7 +473,7 @@ static int omap3_can_sleep(void)
256/* This sets pwrdm state (other than mpu & core. Currently only ON & 473/* This sets pwrdm state (other than mpu & core. Currently only ON &
257 * RET are supported. Function is assuming that clkdm doesn't have 474 * RET are supported. Function is assuming that clkdm doesn't have
258 * hw_sup mode enabled. */ 475 * hw_sup mode enabled. */
259static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) 476int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
260{ 477{
261 u32 cur_state; 478 u32 cur_state;
262 int sleep_switch = 0; 479 int sleep_switch = 0;
@@ -306,7 +523,7 @@ static void omap3_pm_idle(void)
306 if (!omap3_can_sleep()) 523 if (!omap3_can_sleep())
307 goto out; 524 goto out;
308 525
309 if (omap_irq_pending()) 526 if (omap_irq_pending() || need_resched())
310 goto out; 527 goto out;
311 528
312 omap_sram_idle(); 529 omap_sram_idle();
@@ -319,6 +536,22 @@ out:
319#ifdef CONFIG_SUSPEND 536#ifdef CONFIG_SUSPEND
320static suspend_state_t suspend_state; 537static suspend_state_t suspend_state;
321 538
539static void omap2_pm_wakeup_on_timer(u32 seconds)
540{
541 u32 tick_rate, cycles;
542
543 if (!seconds)
544 return;
545
546 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
547 cycles = tick_rate * seconds;
548 omap_dm_timer_stop(gptimer_wakeup);
549 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
550
551 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
552 seconds, cycles, tick_rate);
553}
554
322static int omap3_pm_prepare(void) 555static int omap3_pm_prepare(void)
323{ 556{
324 disable_hlt(); 557 disable_hlt();
@@ -330,6 +563,9 @@ static int omap3_pm_suspend(void)
330 struct power_state *pwrst; 563 struct power_state *pwrst;
331 int state, ret = 0; 564 int state, ret = 0;
332 565
566 if (wakeup_timer_seconds)
567 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
568
333 /* Read current next_pwrsts */ 569 /* Read current next_pwrsts */
334 list_for_each_entry(pwrst, &pwrst_list, node) 570 list_for_each_entry(pwrst, &pwrst_list, node)
335 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 571 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
@@ -690,6 +926,22 @@ static void __init prcm_setup_regs(void)
690 omap3_d2d_idle(); 926 omap3_d2d_idle();
691} 927}
692 928
929void omap3_pm_off_mode_enable(int enable)
930{
931 struct power_state *pwrst;
932 u32 state;
933
934 if (enable)
935 state = PWRDM_POWER_OFF;
936 else
937 state = PWRDM_POWER_RET;
938
939 list_for_each_entry(pwrst, &pwrst_list, node) {
940 pwrst->next_state = state;
941 set_pwrdm_state(pwrst->pwrdm, state);
942 }
943}
944
693int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) 945int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
694{ 946{
695 struct power_state *pwrst; 947 struct power_state *pwrst;
@@ -749,6 +1001,15 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
749 return 0; 1001 return 0;
750} 1002}
751 1003
1004void omap_push_sram_idle(void)
1005{
1006 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1007 omap34xx_cpu_suspend_sz);
1008 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1009 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1010 save_secure_ram_context_sz);
1011}
1012
752static int __init omap3_pm_init(void) 1013static int __init omap3_pm_init(void)
753{ 1014{
754 struct power_state *pwrst, *tmp; 1015 struct power_state *pwrst, *tmp;
@@ -786,15 +1047,47 @@ static int __init omap3_pm_init(void)
786 goto err2; 1047 goto err2;
787 } 1048 }
788 1049
789 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, 1050 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
790 omap34xx_cpu_suspend_sz); 1051 per_pwrdm = pwrdm_lookup("per_pwrdm");
1052 core_pwrdm = pwrdm_lookup("core_pwrdm");
1053 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
791 1054
1055 omap_push_sram_idle();
792#ifdef CONFIG_SUSPEND 1056#ifdef CONFIG_SUSPEND
793 suspend_set_ops(&omap_pm_ops); 1057 suspend_set_ops(&omap_pm_ops);
794#endif /* CONFIG_SUSPEND */ 1058#endif /* CONFIG_SUSPEND */
795 1059
796 pm_idle = omap3_pm_idle; 1060 pm_idle = omap3_pm_idle;
1061 omap3_idle_init();
1062
1063 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1064 /*
1065 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1066 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1067 * waking up PER with every CORE wakeup - see
1068 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1069 */
1070 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1071
1072 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1073 omap3_secure_ram_storage =
1074 kmalloc(0x803F, GFP_KERNEL);
1075 if (!omap3_secure_ram_storage)
1076 printk(KERN_ERR "Memory allocation failed when"
1077 "allocating for secure sram context\n");
1078
1079 local_irq_disable();
1080 local_fiq_disable();
1081
1082 omap_dma_global_context_save();
1083 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1084 omap_dma_global_context_restore();
1085
1086 local_irq_enable();
1087 local_fiq_enable();
1088 }
797 1089
1090 omap3_save_scratchpad_contents();
798err1: 1091err1:
799 return ret; 1092 return ret;
800err2: 1093err2:
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index f00289abd30f..b6990e377783 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -31,9 +31,9 @@
31#include "prm.h" 31#include "prm.h"
32#include "prm-regbits-34xx.h" 32#include "prm-regbits-34xx.h"
33 33
34#include <mach/cpu.h> 34#include <plat/cpu.h>
35#include <mach/powerdomain.h> 35#include <plat/powerdomain.h>
36#include <mach/clockdomain.h> 36#include <plat/clockdomain.h>
37 37
38#include "pm.h" 38#include "pm.h"
39 39
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 691470ea4c6a..057b2e3e2c35 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -63,7 +63,7 @@
63 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE 63 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
64 */ 64 */
65 65
66#include <mach/powerdomain.h> 66#include <plat/powerdomain.h>
67 67
68#include "prcm-common.h" 68#include "prcm-common.h"
69#include "prm.h" 69#include "prm.h"
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains24xx.h
index 9f08dc3f7fd2..bd249a495aa9 100644
--- a/arch/arm/mach-omap2/powerdomains24xx.h
+++ b/arch/arm/mach-omap2/powerdomains24xx.h
@@ -20,7 +20,7 @@
20 * the array in mach-omap2/powerdomains.h. 20 * the array in mach-omap2/powerdomains.h.
21 */ 21 */
22 22
23#include <mach/powerdomain.h> 23#include <plat/powerdomain.h>
24 24
25#include "prcm-common.h" 25#include "prcm-common.h"
26#include "prm.h" 26#include "prm.h"
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 4dcf94b800ab..fd09b0827df0 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -20,7 +20,7 @@
20 * the array in mach-omap2/powerdomains.h. 20 * the array in mach-omap2/powerdomains.h.
21 */ 21 */
22 22
23#include <mach/powerdomain.h> 23#include <plat/powerdomain.h>
24 24
25#include "prcm-common.h" 25#include "prcm-common.h"
26#include "prm.h" 26#include "prm.h"
@@ -338,7 +338,13 @@ static struct powerdomain usbhost_pwrdm = {
338 .sleepdep_srcs = dss_per_usbhost_sleepdeps, 338 .sleepdep_srcs = dss_per_usbhost_sleepdeps,
339 .pwrsts = PWRSTS_OFF_RET_ON, 339 .pwrsts = PWRSTS_OFF_RET_ON,
340 .pwrsts_logic_ret = PWRDM_POWER_RET, 340 .pwrsts_logic_ret = PWRDM_POWER_RET,
341 .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */ 341 /*
342 * REVISIT: Enabling usb host save and restore mechanism seems to
343 * leave the usb host domain permanently in ACTIVE mode after
344 * changing the usb host power domain state from OFF to active once.
345 * Disabling for now.
346 */
347 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
342 .banks = 1, 348 .banks = 1,
343 .pwrsts_mem_ret = { 349 .pwrsts_mem_ret = {
344 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ 350 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index ced555a4cd1a..029d376198d4 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -7,6 +7,9 @@
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
10 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
11 * 14 *
12 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
@@ -19,10 +22,13 @@
19#include <linux/io.h> 22#include <linux/io.h>
20#include <linux/delay.h> 23#include <linux/delay.h>
21 24
22#include <mach/common.h> 25#include <plat/common.h>
23#include <mach/prcm.h> 26#include <plat/prcm.h>
27#include <plat/irqs.h>
28#include <plat/control.h>
24 29
25#include "clock.h" 30#include "clock.h"
31#include "cm.h"
26#include "prm.h" 32#include "prm.h"
27#include "prm-regbits-24xx.h" 33#include "prm-regbits-24xx.h"
28 34
@@ -31,6 +37,89 @@ static void __iomem *cm_base;
31 37
32#define MAX_MODULE_ENABLE_WAIT 100000 38#define MAX_MODULE_ENABLE_WAIT 100000
33 39
40struct omap3_prcm_regs {
41 u32 control_padconf_sys_nirq;
42 u32 iva2_cm_clksel1;
43 u32 iva2_cm_clksel2;
44 u32 cm_sysconfig;
45 u32 sgx_cm_clksel;
46 u32 wkup_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken;
56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
79 u32 pll_cm_autoidle;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119};
120
121struct omap3_prcm_regs prcm_context;
122
34u32 omap_prcm_get_reset_sources(void) 123u32 omap_prcm_get_reset_sources(void)
35{ 124{
36 /* XXX This presumably needs modification for 34XX */ 125 /* XXX This presumably needs modification for 34XX */
@@ -46,9 +135,18 @@ void omap_prcm_arch_reset(char mode)
46 135
47 if (cpu_is_omap24xx()) 136 if (cpu_is_omap24xx())
48 prcm_offs = WKUP_MOD; 137 prcm_offs = WKUP_MOD;
49 else if (cpu_is_omap34xx()) 138 else if (cpu_is_omap34xx()) {
139 u32 l;
140
50 prcm_offs = OMAP3430_GR_MOD; 141 prcm_offs = OMAP3430_GR_MOD;
51 else 142 l = ('B' << 24) | ('M' << 16) | mode;
143 /* Reserve the first word in scratchpad for communicating
144 * with the boot ROM. A pointer to a data structure
145 * describing the boot process can be stored there,
146 * cf. OMAP34xx TRM, Initialization / Software Booting
147 * Configuration. */
148 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
149 } else
52 WARN_ON(1); 150 WARN_ON(1);
53 151
54 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL); 152 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
@@ -168,3 +266,308 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
168 prm_base = omap2_globals->prm; 266 prm_base = omap2_globals->prm;
169 cm_base = omap2_globals->cm; 267 cm_base = omap2_globals->cm;
170} 268}
269
270#ifdef CONFIG_ARCH_OMAP3
271void omap3_prcm_save_context(void)
272{
273 prcm_context.control_padconf_sys_nirq =
274 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
275 prcm_context.iva2_cm_clksel1 =
276 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
277 prcm_context.iva2_cm_clksel2 =
278 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
279 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
280 prcm_context.sgx_cm_clksel =
281 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
282 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
283 prcm_context.dss_cm_clksel =
284 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
285 prcm_context.cam_cm_clksel =
286 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
287 prcm_context.per_cm_clksel =
288 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
289 prcm_context.emu_cm_clksel =
290 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
291 prcm_context.emu_cm_clkstctrl =
292 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
293 prcm_context.pll_cm_autoidle2 =
294 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
295 prcm_context.pll_cm_clksel4 =
296 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
297 prcm_context.pll_cm_clksel5 =
298 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
299 prcm_context.pll_cm_clken =
300 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
301 prcm_context.pll_cm_clken2 =
302 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
303 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
304 prcm_context.iva2_cm_fclken =
305 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
306 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
307 OMAP3430_CM_CLKEN_PLL);
308 prcm_context.core_cm_fclken1 =
309 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
310 prcm_context.core_cm_fclken3 =
311 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
312 prcm_context.sgx_cm_fclken =
313 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
314 prcm_context.wkup_cm_fclken =
315 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
316 prcm_context.dss_cm_fclken =
317 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
318 prcm_context.cam_cm_fclken =
319 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
320 prcm_context.per_cm_fclken =
321 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
322 prcm_context.usbhost_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
324 prcm_context.core_cm_iclken1 =
325 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
326 prcm_context.core_cm_iclken2 =
327 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
328 prcm_context.core_cm_iclken3 =
329 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
330 prcm_context.sgx_cm_iclken =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
332 prcm_context.wkup_cm_iclken =
333 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
334 prcm_context.dss_cm_iclken =
335 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
336 prcm_context.cam_cm_iclken =
337 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
338 prcm_context.per_cm_iclken =
339 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
340 prcm_context.usbhost_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
342 prcm_context.iva2_cm_autiidle2 =
343 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
344 prcm_context.mpu_cm_autoidle2 =
345 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
346 prcm_context.pll_cm_autoidle =
347 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
348 prcm_context.iva2_cm_clkstctrl =
349 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
350 prcm_context.mpu_cm_clkstctrl =
351 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
352 prcm_context.core_cm_clkstctrl =
353 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
354 prcm_context.sgx_cm_clkstctrl =
355 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
356 prcm_context.dss_cm_clkstctrl =
357 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
358 prcm_context.cam_cm_clkstctrl =
359 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
360 prcm_context.per_cm_clkstctrl =
361 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
362 prcm_context.neon_cm_clkstctrl =
363 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
364 prcm_context.usbhost_cm_clkstctrl =
365 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
366 prcm_context.core_cm_autoidle1 =
367 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
368 prcm_context.core_cm_autoidle2 =
369 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
370 prcm_context.core_cm_autoidle3 =
371 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
372 prcm_context.wkup_cm_autoidle =
373 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
374 prcm_context.dss_cm_autoidle =
375 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
376 prcm_context.cam_cm_autoidle =
377 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
378 prcm_context.per_cm_autoidle =
379 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
380 prcm_context.usbhost_cm_autoidle =
381 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
382 prcm_context.sgx_cm_sleepdep =
383 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
384 prcm_context.dss_cm_sleepdep =
385 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
386 prcm_context.cam_cm_sleepdep =
387 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
388 prcm_context.per_cm_sleepdep =
389 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
390 prcm_context.usbhost_cm_sleepdep =
391 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
392 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
393 OMAP3_CM_CLKOUT_CTRL_OFFSET);
394 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
395 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
396 prcm_context.sgx_pm_wkdep =
397 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
398 prcm_context.dss_pm_wkdep =
399 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
400 prcm_context.cam_pm_wkdep =
401 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
402 prcm_context.per_pm_wkdep =
403 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
404 prcm_context.neon_pm_wkdep =
405 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
406 prcm_context.usbhost_pm_wkdep =
407 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
408 prcm_context.core_pm_mpugrpsel1 =
409 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
410 prcm_context.iva2_pm_ivagrpsel1 =
411 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
412 prcm_context.core_pm_mpugrpsel3 =
413 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
414 prcm_context.core_pm_ivagrpsel3 =
415 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
416 prcm_context.wkup_pm_mpugrpsel =
417 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
418 prcm_context.wkup_pm_ivagrpsel =
419 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
420 prcm_context.per_pm_mpugrpsel =
421 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
422 prcm_context.per_pm_ivagrpsel =
423 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
424 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
425 return;
426}
427
428void omap3_prcm_restore_context(void)
429{
430 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
431 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
432 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
433 CM_CLKSEL1);
434 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
435 CM_CLKSEL2);
436 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
437 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
438 CM_CLKSEL);
439 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
440 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
441 CM_CLKSEL);
442 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
443 CM_CLKSEL);
444 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
445 CM_CLKSEL);
446 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
447 CM_CLKSEL1);
448 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
449 CM_CLKSTCTRL);
450 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
451 CM_AUTOIDLE2);
452 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
453 OMAP3430ES2_CM_CLKSEL4);
454 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
455 OMAP3430ES2_CM_CLKSEL5);
456 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
457 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
458 OMAP3430ES2_CM_CLKEN2);
459 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
460 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
461 CM_FCLKEN);
462 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
463 OMAP3430_CM_CLKEN_PLL);
464 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
465 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
466 OMAP3430ES2_CM_FCLKEN3);
467 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
468 CM_FCLKEN);
469 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
470 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
471 CM_FCLKEN);
472 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
473 CM_FCLKEN);
474 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
475 CM_FCLKEN);
476 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
477 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
478 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
479 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
480 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
481 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
482 CM_ICLKEN);
483 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
484 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
485 CM_ICLKEN);
486 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
487 CM_ICLKEN);
488 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
489 CM_ICLKEN);
490 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
491 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
492 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
493 CM_AUTOIDLE2);
494 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
495 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
496 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
497 CM_CLKSTCTRL);
498 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
499 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
500 CM_CLKSTCTRL);
501 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
502 CM_CLKSTCTRL);
503 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
504 CM_CLKSTCTRL);
505 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
506 CM_CLKSTCTRL);
507 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
508 CM_CLKSTCTRL);
509 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
510 CM_CLKSTCTRL);
511 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
512 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
513 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
514 CM_AUTOIDLE1);
515 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
516 CM_AUTOIDLE2);
517 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
518 CM_AUTOIDLE3);
519 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
520 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
521 CM_AUTOIDLE);
522 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
523 CM_AUTOIDLE);
524 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
525 CM_AUTOIDLE);
526 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
527 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
528 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
529 OMAP3430_CM_SLEEPDEP);
530 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
531 OMAP3430_CM_SLEEPDEP);
532 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
533 OMAP3430_CM_SLEEPDEP);
534 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
535 OMAP3430_CM_SLEEPDEP);
536 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
537 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
538 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
539 OMAP3_CM_CLKOUT_CTRL_OFFSET);
540 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
541 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
542 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
543 PM_WKDEP);
544 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
545 PM_WKDEP);
546 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
547 PM_WKDEP);
548 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
549 PM_WKDEP);
550 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
551 PM_WKDEP);
552 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
553 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
554 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
555 OMAP3430_PM_MPUGRPSEL1);
556 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
557 OMAP3430_PM_IVAGRPSEL1);
558 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
559 OMAP3430ES2_PM_MPUGRPSEL3);
560 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
561 OMAP3430ES2_PM_IVAGRPSEL3);
562 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
563 OMAP3430_PM_MPUGRPSEL);
564 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
565 OMAP3430_PM_IVAGRPSEL);
566 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
567 OMAP3430_PM_MPUGRPSEL);
568 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
569 OMAP3430_PM_IVAGRPSEL);
570 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
571 return;
572}
573#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 9fd03a2ec95c..8f21bae6dc1c 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -365,6 +365,7 @@
365/* PM_PREPWSTST_GFX specific bits */ 365/* PM_PREPWSTST_GFX specific bits */
366 366
367/* PM_WKEN_WKUP specific bits */ 367/* PM_WKEN_WKUP specific bits */
368#define OMAP3430_EN_IO_CHAIN (1 << 16)
368#define OMAP3430_EN_IO (1 << 8) 369#define OMAP3430_EN_IO (1 << 8)
369#define OMAP3430_EN_GPIO1 (1 << 3) 370#define OMAP3430_EN_GPIO1 (1 << 3)
370 371
@@ -373,6 +374,7 @@
373/* PM_IVA2GRPSEL_WKUP specific bits */ 374/* PM_IVA2GRPSEL_WKUP specific bits */
374 375
375/* PM_WKST_WKUP specific bits */ 376/* PM_WKST_WKUP specific bits */
377#define OMAP3430_ST_IO_CHAIN (1 << 16)
376#define OMAP3430_ST_IO (1 << 8) 378#define OMAP3430_ST_IO (1 << 8)
377 379
378/* PRM_CLKSEL */ 380/* PRM_CLKSEL */
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 03c467c35f54..a117f853ea39 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,11 +17,11 @@
17#include "prcm-common.h" 17#include "prcm-common.h"
18 18
19#define OMAP2420_PRM_REGADDR(module, reg) \ 19#define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) 20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21#define OMAP2430_PRM_REGADDR(module, reg) \ 21#define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) 22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23#define OMAP34XX_PRM_REGADDR(module, reg) \ 23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) 24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25 25
26/* 26/*
27 * Architecture-specific global PRM registers 27 * Architecture-specific global PRM registers
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index 02e1c2d4705f..a391b4939f74 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -14,7 +14,7 @@
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF 14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
15#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF 15#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
16 16
17#include <mach/sdrc.h> 17#include <plat/sdrc.h>
18 18
19/* Micron MT46H32M32LF-6 */ 19/* Micron MT46H32M32LF-6 */
20/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ 20/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 3751d293cb1f..0e518a72831f 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -14,7 +14,7 @@
14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 14#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
15#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6 15#define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
16 16
17#include <mach/sdrc.h> 17#include <plat/sdrc.h>
18 18
19/* Qimonda HYB18M512160AF-6 */ 19/* Qimonda HYB18M512160AF-6 */
20static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { 20static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 9e3bd4fa7810..9a592199321c 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -23,13 +23,13 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/io.h> 24#include <linux/io.h>
25 25
26#include <mach/common.h> 26#include <plat/common.h>
27#include <mach/clock.h> 27#include <plat/clock.h>
28#include <mach/sram.h> 28#include <plat/sram.h>
29 29
30#include "prm.h" 30#include "prm.h"
31 31
32#include <mach/sdrc.h> 32#include <plat/sdrc.h>
33#include "sdrc.h" 33#include "sdrc.h"
34 34
35static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; 35static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
@@ -37,12 +37,38 @@ static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
37void __iomem *omap2_sdrc_base; 37void __iomem *omap2_sdrc_base;
38void __iomem *omap2_sms_base; 38void __iomem *omap2_sms_base;
39 39
40struct omap2_sms_regs {
41 u32 sms_sysconfig;
42};
43
44static struct omap2_sms_regs sms_context;
45
40/* SDRC_POWER register bits */ 46/* SDRC_POWER register bits */
41#define SDRC_POWER_EXTCLKDIS_SHIFT 3 47#define SDRC_POWER_EXTCLKDIS_SHIFT 3
42#define SDRC_POWER_PWDENA_SHIFT 2 48#define SDRC_POWER_PWDENA_SHIFT 2
43#define SDRC_POWER_PAGEPOLICY_SHIFT 0 49#define SDRC_POWER_PAGEPOLICY_SHIFT 0
44 50
45/** 51/**
52 * omap2_sms_save_context - Save SMS registers
53 *
54 * Save SMS registers that need to be restored after off mode.
55 */
56void omap2_sms_save_context(void)
57{
58 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
59}
60
61/**
62 * omap2_sms_restore_context - Restore SMS registers
63 *
64 * Restore SMS registers that need to be Restored after off mode.
65 */
66void omap2_sms_restore_context(void)
67{
68 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
69}
70
71/**
46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate 72 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
47 * @r: SDRC clock rate (in Hz) 73 * @r: SDRC clock rate (in Hz)
48 * @sdrc_cs0: chip select 0 ram timings ** 74 * @sdrc_cs0: chip select 0 ram timings **
@@ -132,4 +158,5 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
132 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | 158 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
133 (1 << SDRC_POWER_PAGEPOLICY_SHIFT); 159 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
134 sdrc_write_reg(l, SDRC_POWER); 160 sdrc_write_reg(l, SDRC_POWER);
161 omap2_sms_save_context();
135} 162}
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 0837eda5f2b6..48207b018989 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -15,7 +15,7 @@
15 */ 15 */
16#undef DEBUG 16#undef DEBUG
17 17
18#include <mach/sdrc.h> 18#include <plat/sdrc.h>
19 19
20#ifndef __ASSEMBLER__ 20#ifndef __ASSEMBLER__
21extern void __iomem *omap2_sdrc_base; 21extern void __iomem *omap2_sdrc_base;
@@ -48,9 +48,12 @@ static inline u32 sms_read_reg(u16 reg)
48 return __raw_readl(OMAP_SMS_REGADDR(reg)); 48 return __raw_readl(OMAP_SMS_REGADDR(reg));
49} 49}
50#else 50#else
51#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) 51#define OMAP242X_SDRC_REGADDR(reg) \
52#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) 52 OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
53#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) 53#define OMAP243X_SDRC_REGADDR(reg) \
54 OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
55#define OMAP34XX_SDRC_REGADDR(reg) \
56 OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
54#endif /* __ASSEMBLER__ */ 57#endif /* __ASSEMBLER__ */
55 58
56#endif 59#endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index feaec7eaf6bd..0f4d27aef44d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,13 +24,13 @@
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include <mach/common.h> 27#include <plat/common.h>
28#include <mach/clock.h> 28#include <plat/clock.h>
29#include <mach/sram.h> 29#include <plat/sram.h>
30 30
31#include "prm.h" 31#include "prm.h"
32#include "clock.h" 32#include "clock.h"
33#include <mach/sdrc.h> 33#include <plat/sdrc.h>
34#include "sdrc.h" 34#include "sdrc.h"
35 35
36/* Memory timing, DLL mode flags */ 36/* Memory timing, DLL mode flags */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 54dfeb5d5667..72df1b188135 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -24,10 +24,10 @@
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include <mach/common.h> 27#include <plat/common.h>
28#include <mach/board.h> 28#include <plat/board.h>
29#include <mach/clock.h> 29#include <plat/clock.h>
30#include <mach/control.h> 30#include <plat/control.h>
31 31
32#include "prm.h" 32#include "prm.h"
33#include "pm.h" 33#include "pm.h"
@@ -73,7 +73,6 @@ static LIST_HEAD(uart_list);
73 73
74static struct plat_serial8250_port serial_platform_data0[] = { 74static struct plat_serial8250_port serial_platform_data0[] = {
75 { 75 {
76 .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE, 76 .mapbase = OMAP_UART1_BASE,
78 .irq = 72, 77 .irq = 72,
79 .flags = UPF_BOOT_AUTOCONF, 78 .flags = UPF_BOOT_AUTOCONF,
@@ -87,7 +86,6 @@ static struct plat_serial8250_port serial_platform_data0[] = {
87 86
88static struct plat_serial8250_port serial_platform_data1[] = { 87static struct plat_serial8250_port serial_platform_data1[] = {
89 { 88 {
90 .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE, 89 .mapbase = OMAP_UART2_BASE,
92 .irq = 73, 90 .irq = 73,
93 .flags = UPF_BOOT_AUTOCONF, 91 .flags = UPF_BOOT_AUTOCONF,
@@ -101,7 +99,6 @@ static struct plat_serial8250_port serial_platform_data1[] = {
101 99
102static struct plat_serial8250_port serial_platform_data2[] = { 100static struct plat_serial8250_port serial_platform_data2[] = {
103 { 101 {
104 .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE, 102 .mapbase = OMAP_UART3_BASE,
106 .irq = 74, 103 .irq = 74,
107 .flags = UPF_BOOT_AUTOCONF, 104 .flags = UPF_BOOT_AUTOCONF,
@@ -116,7 +113,6 @@ static struct plat_serial8250_port serial_platform_data2[] = {
116#ifdef CONFIG_ARCH_OMAP4 113#ifdef CONFIG_ARCH_OMAP4
117static struct plat_serial8250_port serial_platform_data3[] = { 114static struct plat_serial8250_port serial_platform_data3[] = {
118 { 115 {
119 .membase = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
120 .mapbase = OMAP_UART4_BASE, 116 .mapbase = OMAP_UART4_BASE,
121 .irq = 70, 117 .irq = 70,
122 .flags = UPF_BOOT_AUTOCONF, 118 .flags = UPF_BOOT_AUTOCONF,
@@ -159,8 +155,6 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
159 155
160#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) 156#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
161 157
162static int enable_off_mode; /* to be removed by full off-mode patches */
163
164static void omap_uart_save_context(struct omap_uart_state *uart) 158static void omap_uart_save_context(struct omap_uart_state *uart)
165{ 159{
166 u16 lcr = 0; 160 u16 lcr = 0;
@@ -595,6 +589,16 @@ void __init omap_serial_early_init(void)
595 struct device *dev = &pdev->dev; 589 struct device *dev = &pdev->dev;
596 struct plat_serial8250_port *p = dev->platform_data; 590 struct plat_serial8250_port *p = dev->platform_data;
597 591
592 /*
593 * Module 4KB + L4 interconnect 4KB
594 * Static mapping, never released
595 */
596 p->membase = ioremap(p->mapbase, SZ_8K);
597 if (!p->membase) {
598 printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
599 continue;
600 }
601
598 sprintf(name, "uart%d_ick", i+1); 602 sprintf(name, "uart%d_ick", i+1);
599 uart->ick = clk_get(NULL, name); 603 uart->ick = clk_get(NULL, name);
600 if (IS_ERR(uart->ick)) { 604 if (IS_ERR(uart->ick)) {
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index 130aadbfa083..c7780cc8d919 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -29,7 +29,7 @@
29#include <asm/assembler.h> 29#include <asm/assembler.h>
30#include <mach/io.h> 30#include <mach/io.h>
31 31
32#include <mach/omap24xx.h> 32#include <plat/omap24xx.h>
33 33
34#include "sdrc.h" 34#include "sdrc.h"
35 35
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index e5e2553e79a6..15268f8b61de 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -27,22 +27,35 @@
27#include <linux/linkage.h> 27#include <linux/linkage.h>
28#include <asm/assembler.h> 28#include <asm/assembler.h>
29#include <mach/io.h> 29#include <mach/io.h>
30#include <mach/control.h> 30#include <plat/control.h>
31 31
32#include "cm.h"
32#include "prm.h" 33#include "prm.h"
33#include "sdrc.h" 34#include "sdrc.h"
34 35
35#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ 36#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
36 OMAP3430_PM_PREPWSTST) 37 OMAP3430_PM_PREPWSTST)
38#define PM_PREPWSTST_CORE_P 0x48306AE8
37#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ 39#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
38 OMAP3430_PM_PREPWSTST) 40 OMAP3430_PM_PREPWSTST)
39#define PM_PWSTCTRL_MPU_P OMAP34XX_PRM_REGADDR(MPU_MOD, PM_PWSTCTRL) 41#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
42#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
43#define SRAM_BASE_P 0x40200000
44#define CONTROL_STAT 0x480022F0
40#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is 45#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
41 * available */ 46 * available */
42#define SCRATCHPAD_BASE_P OMAP343X_CTRL_REGADDR(\ 47#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
43 OMAP343X_CONTROL_MEM_WKUP +\ 48 + SCRATCHPAD_MEM_OFFS)
44 SCRATCHPAD_MEM_OFFS)
45#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) 49#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
50#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
51#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
52#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
53#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
54#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
55#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
56#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
57#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
58#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
46 59
47 .text 60 .text
48/* Function call to get the restore pointer for resume from OFF */ 61/* Function call to get the restore pointer for resume from OFF */
@@ -51,7 +64,93 @@ ENTRY(get_restore_pointer)
51 adr r0, restore 64 adr r0, restore
52 ldmfd sp!, {pc} @ restore regs and return 65 ldmfd sp!, {pc} @ restore regs and return
53ENTRY(get_restore_pointer_sz) 66ENTRY(get_restore_pointer_sz)
54 .word . - get_restore_pointer_sz 67 .word . - get_restore_pointer
68
69 .text
70/* Function call to get the restore pointer for for ES3 to resume from OFF */
71ENTRY(get_es3_restore_pointer)
72 stmfd sp!, {lr} @ save registers on stack
73 adr r0, restore_es3
74 ldmfd sp!, {pc} @ restore regs and return
75ENTRY(get_es3_restore_pointer_sz)
76 .word . - get_es3_restore_pointer
77
78ENTRY(es3_sdrc_fix)
79 ldr r4, sdrc_syscfg @ get config addr
80 ldr r5, [r4] @ get value
81 tst r5, #0x100 @ is part access blocked
82 it eq
83 biceq r5, r5, #0x100 @ clear bit if set
84 str r5, [r4] @ write back change
85 ldr r4, sdrc_mr_0 @ get config addr
86 ldr r5, [r4] @ get value
87 str r5, [r4] @ write back change
88 ldr r4, sdrc_emr2_0 @ get config addr
89 ldr r5, [r4] @ get value
90 str r5, [r4] @ write back change
91 ldr r4, sdrc_manual_0 @ get config addr
92 mov r5, #0x2 @ autorefresh command
93 str r5, [r4] @ kick off refreshes
94 ldr r4, sdrc_mr_1 @ get config addr
95 ldr r5, [r4] @ get value
96 str r5, [r4] @ write back change
97 ldr r4, sdrc_emr2_1 @ get config addr
98 ldr r5, [r4] @ get value
99 str r5, [r4] @ write back change
100 ldr r4, sdrc_manual_1 @ get config addr
101 mov r5, #0x2 @ autorefresh command
102 str r5, [r4] @ kick off refreshes
103 bx lr
104sdrc_syscfg:
105 .word SDRC_SYSCONFIG_P
106sdrc_mr_0:
107 .word SDRC_MR_0_P
108sdrc_emr2_0:
109 .word SDRC_EMR2_0_P
110sdrc_manual_0:
111 .word SDRC_MANUAL_0_P
112sdrc_mr_1:
113 .word SDRC_MR_1_P
114sdrc_emr2_1:
115 .word SDRC_EMR2_1_P
116sdrc_manual_1:
117 .word SDRC_MANUAL_1_P
118ENTRY(es3_sdrc_fix_sz)
119 .word . - es3_sdrc_fix
120
121/* Function to call rom code to save secure ram context */
122ENTRY(save_secure_ram_context)
123 stmfd sp!, {r1-r12, lr} @ save registers on stack
124save_secure_ram_debug:
125 /* b save_secure_ram_debug */ @ enable to debug save code
126 adr r3, api_params @ r3 points to parameters
127 str r0, [r3,#0x4] @ r0 has sdram address
128 ldr r12, high_mask
129 and r3, r3, r12
130 ldr r12, sram_phy_addr_mask
131 orr r3, r3, r12
132 mov r0, #25 @ set service ID for PPA
133 mov r12, r0 @ copy secure service ID in r12
134 mov r1, #0 @ set task id for ROM code in r1
135 mov r2, #4 @ set some flags in r2, r6
136 mov r6, #0xff
137 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
138 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
139 .word 0xE1600071 @ call SMI monitor (smi #1)
140 nop
141 nop
142 nop
143 nop
144 ldmfd sp!, {r1-r12, pc}
145sram_phy_addr_mask:
146 .word SRAM_BASE_P
147high_mask:
148 .word 0xffff
149api_params:
150 .word 0x4, 0x0, 0x0, 0x1, 0x1
151ENTRY(save_secure_ram_context_sz)
152 .word . - save_secure_ram_context
153
55/* 154/*
56 * Forces OMAP into idle state 155 * Forces OMAP into idle state
57 * 156 *
@@ -92,11 +191,29 @@ loop:
92 nop 191 nop
93 nop 192 nop
94 nop 193 nop
95 bl i_dll_wait 194 bl wait_sdrc_ok
96 195
97 ldmfd sp!, {r0-r12, pc} @ restore regs and return 196 ldmfd sp!, {r0-r12, pc} @ restore regs and return
197restore_es3:
198 /*b restore_es3*/ @ Enable to debug restore code
199 ldr r5, pm_prepwstst_core_p
200 ldr r4, [r5]
201 and r4, r4, #0x3
202 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
203 bne restore
204 adr r0, es3_sdrc_fix
205 ldr r1, sram_base
206 ldr r2, es3_sdrc_fix_sz
207 mov r2, r2, ror #2
208copy_to_sram:
209 ldmia r0!, {r3} @ val = *src
210 stmia r1!, {r3} @ *dst = val
211 subs r2, r2, #0x1 @ num_words--
212 bne copy_to_sram
213 ldr r1, sram_base
214 blx r1
98restore: 215restore:
99 /* b restore*/ @ Enable to debug restore code 216 /* b restore*/ @ Enable to debug restore code
100 /* Check what was the reason for mpu reset and store the reason in r9*/ 217 /* Check what was the reason for mpu reset and store the reason in r9*/
101 /* 1 - Only L1 and logic lost */ 218 /* 1 - Only L1 and logic lost */
102 /* 2 - Only L2 lost - In this case, we wont be here */ 219 /* 2 - Only L2 lost - In this case, we wont be here */
@@ -108,9 +225,44 @@ restore:
108 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost 225 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
109 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation 226 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
110 bne logic_l1_restore 227 bne logic_l1_restore
228 ldr r0, control_stat
229 ldr r1, [r0]
230 and r1, #0x700
231 cmp r1, #0x300
232 beq l2_inv_gp
233 mov r0, #40 @ set service ID for PPA
234 mov r12, r0 @ copy secure Service ID in r12
235 mov r1, #0 @ set task id for ROM code in r1
236 mov r2, #4 @ set some flags in r2, r6
237 mov r6, #0xff
238 adr r3, l2_inv_api_params @ r3 points to dummy parameters
239 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
240 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
241 .word 0xE1600071 @ call SMI monitor (smi #1)
242 /* Write to Aux control register to set some bits */
243 mov r0, #42 @ set service ID for PPA
244 mov r12, r0 @ copy secure Service ID in r12
245 mov r1, #0 @ set task id for ROM code in r1
246 mov r2, #4 @ set some flags in r2, r6
247 mov r6, #0xff
248 adr r3, write_aux_control_params @ r3 points to parameters
249 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
250 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
251 .word 0xE1600071 @ call SMI monitor (smi #1)
252
253 b logic_l1_restore
254l2_inv_api_params:
255 .word 0x1, 0x00
256write_aux_control_params:
257 .word 0x1, 0x72
258l2_inv_gp:
111 /* Execute smi to invalidate L2 cache */ 259 /* Execute smi to invalidate L2 cache */
112 mov r12, #0x1 @ set up to invalide L2 260 mov r12, #0x1 @ set up to invalide L2
113smi: .word 0xE1600070 @ Call SMI monitor (smieq) 261smi: .word 0xE1600070 @ Call SMI monitor (smieq)
262 /* Write to Aux control register to set some bits */
263 mov r0, #0x72
264 mov r12, #0x3
265 .word 0xE1600070 @ Call SMI monitor (smieq)
114logic_l1_restore: 266logic_l1_restore:
115 mov r1, #0 267 mov r1, #0
116 /* Invalidate all instruction caches to PoU 268 /* Invalidate all instruction caches to PoU
@@ -391,33 +543,55 @@ skip_l2_inval:
391 nop 543 nop
392 nop 544 nop
393 nop 545 nop
394 bl i_dll_wait 546 bl wait_sdrc_ok
395 /* restore regs and return */ 547 /* restore regs and return */
396 ldmfd sp!, {r0-r12, pc} 548 ldmfd sp!, {r0-r12, pc}
397 549
398i_dll_wait: 550/* Make sure SDRC accesses are ok */
399 ldr r4, clk_stabilize_delay 551wait_sdrc_ok:
552 ldr r4, cm_idlest1_core
553 ldr r5, [r4]
554 and r5, r5, #0x2
555 cmp r5, #0
556 bne wait_sdrc_ok
557 ldr r4, sdrc_power
558 ldr r5, [r4]
559 bic r5, r5, #0x40
560 str r5, [r4]
561wait_dll_lock:
562 /* Is dll in lock mode? */
563 ldr r4, sdrc_dlla_ctrl
564 ldr r5, [r4]
565 tst r5, #0x4
566 bxne lr
567 /* wait till dll locks */
568 ldr r4, sdrc_dlla_status
569 ldr r5, [r4]
570 and r5, r5, #0x4
571 cmp r5, #0x4
572 bne wait_dll_lock
573 bx lr
400 574
401i_dll_delay: 575cm_idlest1_core:
402 subs r4, r4, #0x1 576 .word CM_IDLEST1_CORE_V
403 bne i_dll_delay 577sdrc_dlla_status:
404 ldr r4, sdrc_power 578 .word SDRC_DLLA_STATUS_V
405 ldr r5, [r4] 579sdrc_dlla_ctrl:
406 bic r5, r5, #0x40 580 .word SDRC_DLLA_CTRL_V
407 str r5, [r4]
408 bx lr
409pm_prepwstst_core: 581pm_prepwstst_core:
410 .word PM_PREPWSTST_CORE_V 582 .word PM_PREPWSTST_CORE_V
583pm_prepwstst_core_p:
584 .word PM_PREPWSTST_CORE_P
411pm_prepwstst_mpu: 585pm_prepwstst_mpu:
412 .word PM_PREPWSTST_MPU_V 586 .word PM_PREPWSTST_MPU_V
413pm_pwstctrl_mpu: 587pm_pwstctrl_mpu:
414 .word PM_PWSTCTRL_MPU_P 588 .word PM_PWSTCTRL_MPU_P
415scratchpad_base: 589scratchpad_base:
416 .word SCRATCHPAD_BASE_P 590 .word SCRATCHPAD_BASE_P
591sram_base:
592 .word SRAM_BASE_P + 0x8000
417sdrc_power: 593sdrc_power:
418 .word SDRC_POWER_V 594 .word SDRC_POWER_V
419context_mem:
420 .word 0x803E3E14
421clk_stabilize_delay: 595clk_stabilize_delay:
422 .word 0x000001FF 596 .word 0x000001FF
423assoc_mask: 597assoc_mask:
@@ -432,5 +606,7 @@ table_entry:
432 .word 0x00000C02 606 .word 0x00000C02
433cache_pred_disable_mask: 607cache_pred_disable_mask:
434 .word 0xFFFFE7FB 608 .word 0xFFFFE7FB
609control_stat:
610 .word CONTROL_STAT
435ENTRY(omap34xx_cpu_suspend_sz) 611ENTRY(omap34xx_cpu_suspend_sz)
436 .word . - omap34xx_cpu_suspend 612 .word . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 9b62208658bc..92e6e1a12af8 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap242x_sdi_timer_32ksynct_cr: 130omap242x_sdi_timer_32ksynct_cr:
131 .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) 131 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
132ENTRY(omap242x_sram_ddr_init_sz) 132ENTRY(omap242x_sram_ddr_init_sz)
133 .word . - omap242x_sram_ddr_init 133 .word . - omap242x_sram_ddr_init
134 134
@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap242x_srs_timer_32ksynct: 226omap242x_srs_timer_32ksynct:
227 .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) 227 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
228 228
229ENTRY(omap242x_sram_reprogram_sdrc_sz) 229ENTRY(omap242x_sram_reprogram_sdrc_sz)
230 .word . - omap242x_sram_reprogram_sdrc 230 .word . - omap242x_sram_reprogram_sdrc
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index df2cd9277c00..ab4973695c71 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap243x_sdi_timer_32ksynct_cr: 130omap243x_sdi_timer_32ksynct_cr:
131 .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) 131 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
132ENTRY(omap243x_sram_ddr_init_sz) 132ENTRY(omap243x_sram_ddr_init_sz)
133 .word . - omap243x_sram_ddr_init 133 .word . - omap243x_sram_ddr_init
134 134
@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap243x_srs_timer_32ksynct: 226omap243x_srs_timer_32ksynct:
227 .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010) 227 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
228 228
229ENTRY(omap243x_sram_reprogram_sdrc_sz) 229ENTRY(omap243x_sram_reprogram_sdrc_sz)
230 .word . - omap243x_sram_reprogram_sdrc 230 .word . - omap243x_sram_reprogram_sdrc
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index e2338c0aebcf..cd04deaa88c5 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -37,7 +37,7 @@
37#include <linux/clockchips.h> 37#include <linux/clockchips.h>
38 38
39#include <asm/mach/time.h> 39#include <asm/mach/time.h>
40#include <mach/dmtimer.h> 40#include <plat/dmtimer.h>
41#include <asm/localtimer.h> 41#include <asm/localtimer.h>
42 42
43/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ 43/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
@@ -47,6 +47,7 @@ static struct omap_dm_timer *gptimer;
47static struct clock_event_device clockevent_gpt; 47static struct clock_event_device clockevent_gpt;
48static u8 __initdata gptimer_id = 1; 48static u8 __initdata gptimer_id = 1;
49static u8 __initdata inited; 49static u8 __initdata inited;
50struct omap_dm_timer *gptimer_wakeup;
50 51
51static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 52static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
52{ 53{
@@ -134,6 +135,7 @@ static void __init omap2_gp_clockevent_init(void)
134 135
135 gptimer = omap_dm_timer_request_specific(gptimer_id); 136 gptimer = omap_dm_timer_request_specific(gptimer_id);
136 BUG_ON(gptimer == NULL); 137 BUG_ON(gptimer == NULL);
138 gptimer_wakeup = gptimer;
137 139
138#if defined(CONFIG_OMAP_32K_TIMER) 140#if defined(CONFIG_OMAP_32K_TIMER)
139 src = OMAP_TIMER_SRC_32_KHZ; 141 src = OMAP_TIMER_SRC_32_KHZ;
@@ -231,7 +233,8 @@ static void __init omap2_gp_clocksource_init(void)
231static void __init omap2_gp_timer_init(void) 233static void __init omap2_gp_timer_init(void)
232{ 234{
233#ifdef CONFIG_LOCAL_TIMERS 235#ifdef CONFIG_LOCAL_TIMERS
234 twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); 236 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
237 BUG_ON(!twd_base);
235#endif 238#endif
236 omap_dm_timer_init(); 239 omap_dm_timer_init();
237 240
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 1145a2562b0f..a80441dd19b8 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,8 +28,8 @@
28 28
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31#include <mach/mux.h> 31#include <plat/mux.h>
32#include <mach/usb.h> 32#include <plat/usb.h>
33 33
34#ifdef CONFIG_USB_MUSB_SOC 34#ifdef CONFIG_USB_MUSB_SOC
35 35
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 8622c24cd270..10a2013c1104 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -16,8 +16,8 @@
16 16
17#include <linux/usb/musb.h> 17#include <linux/usb/musb.h>
18 18
19#include <mach/gpmc.h> 19#include <plat/gpmc.h>
20#include <mach/mux.h> 20#include <plat/mux.h>
21 21
22 22
23static u8 async_cs, sync_cs; 23static u8 async_cs, sync_cs;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 06:35:25 -0500