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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-10-10 18:10:10 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-10 18:10:10 -0400
commit59aaade72544ad1be4183c1066c20b5883a78717 (patch)
treeda57c3029145c21b5eae457fbd66b997b503f155 /arch/arm/mach-omap2
parent8e5bdc44ba82d1f75c8732c2c2b64a22bb622e8f (diff)
parent99b3075b9095c23acf8d884bdc7fe33c8c3520f0 (diff)
Merge branch 'omap3-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into omap-all
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/Kconfig22
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-ldp.c86
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c244
-rw-r--r--arch/arm/mach-omap2/board-overo.c242
-rw-r--r--arch/arm/mach-omap2/gpmc.c5
-rw-r--r--arch/arm/mach-omap2/io.c126
-rw-r--r--arch/arm/mach-omap2/irq.c2
-rw-r--r--arch/arm/mach-omap2/memory.c14
-rw-r--r--arch/arm/mach-omap2/mux.c67
-rw-r--r--arch/arm/mach-omap2/sram34xx.S179
11 files changed, 957 insertions, 34 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7069c9d536f1..4832fcc7d04a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,8 +15,17 @@ config ARCH_OMAP2430
15 bool "OMAP2430 support" 15 bool "OMAP2430 support"
16 depends on ARCH_OMAP24XX 16 depends on ARCH_OMAP24XX
17 17
18config ARCH_OMAP34XX
19 bool "OMAP34xx Based System"
20 depends on ARCH_OMAP3
21
22config ARCH_OMAP3430
23 bool "OMAP3430 support"
24 depends on ARCH_OMAP3 && ARCH_OMAP34XX
25 select ARCH_OMAP_OTG
26
18comment "OMAP Board Type" 27comment "OMAP Board Type"
19 depends on ARCH_OMAP2 28 depends on ARCH_OMAP2 || ARCH_OMAP3
20 29
21config MACH_OMAP_GENERIC 30config MACH_OMAP_GENERIC
22 bool "Generic OMAP board" 31 bool "Generic OMAP board"
@@ -35,3 +44,14 @@ config MACH_OMAP_2430SDP
35 bool "OMAP 2430 SDP board" 44 bool "OMAP 2430 SDP board"
36 depends on ARCH_OMAP2 && ARCH_OMAP24XX 45 depends on ARCH_OMAP2 && ARCH_OMAP24XX
37 46
47config MACH_OMAP3_BEAGLE
48 bool "OMAP3 BEAGLE board"
49 depends on ARCH_OMAP3 && ARCH_OMAP34XX
50
51config MACH_OMAP_LDP
52 bool "OMAP3 LDP board"
53 depends on ARCH_OMAP3 && ARCH_OMAP34XX
54
55config MACH_OVERO
56 bool "Gumstix Overo board"
57 depends on ARCH_OMAP3 && ARCH_OMAP34XX
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 800639e7c6a4..c69392372c99 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
12# Functions loaded to SRAM 12# Functions loaded to SRAM
13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o 13obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
15 16
16# Power Management 17# Power Management
17ifeq ($(CONFIG_PM),y) 18ifeq ($(CONFIG_PM),y)
@@ -28,4 +29,7 @@ obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
28obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o 29obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
29obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 30obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
30obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o 31obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
32obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
33obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
34obj-$(CONFIG_MACH_OVERO) += board-overo.o
31 35
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
new file mode 100644
index 000000000000..1ea59986aa7a
--- /dev/null
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -0,0 +1,86 @@
1/*
2 * linux/arch/arm/mach-omap2/board-ldp.c
3 *
4 * Copyright (C) 2008 Texas Instruments Inc.
5 * Nishant Kamat <nskamat@ti.com>
6 *
7 * Modified from mach-omap2/board-3430sdp.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/input.h>
19#include <linux/workqueue.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/ads7846.h>
24
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <mach/board-ldp.h>
31#include <mach/mcspi.h>
32#include <mach/gpio.h>
33#include <mach/board.h>
34#include <mach/common.h>
35#include <mach/gpmc.h>
36
37#include <asm/io.h>
38#include <asm/delay.h>
39#include <mach/control.h>
40
41static void __init omap_ldp_init_irq(void)
42{
43 omap2_init_common_hw();
44 omap_init_irq();
45 omap_gpio_init();
46}
47
48static struct omap_uart_config ldp_uart_config __initdata = {
49 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
50};
51
52static struct omap_board_config_kernel ldp_config[] __initdata = {
53 { OMAP_TAG_UART, &ldp_uart_config },
54};
55
56static int __init omap_i2c_init(void)
57{
58 omap_register_i2c_bus(1, 2600, NULL, 0);
59 omap_register_i2c_bus(2, 400, NULL, 0);
60 omap_register_i2c_bus(3, 400, NULL, 0);
61 return 0;
62}
63
64static void __init omap_ldp_init(void)
65{
66 omap_i2c_init();
67 omap_board_config = ldp_config;
68 omap_board_config_size = ARRAY_SIZE(ldp_config);
69 omap_serial_init();
70}
71
72static void __init omap_ldp_map_io(void)
73{
74 omap2_set_globals_343x();
75 omap2_map_common_io();
76}
77
78MACHINE_START(OMAP_LDP, "OMAP LDP board")
79 .phys_io = 0x48000000,
80 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
81 .boot_params = 0x80000100,
82 .map_io = omap_ldp_map_io,
83 .init_irq = omap_ldp_init_irq,
84 .init_machine = omap_ldp_init,
85 .timer = &omap_timer,
86MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
new file mode 100644
index 000000000000..baa79674e9d5
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -0,0 +1,244 @@
1/*
2 * linux/arch/arm/mach-omap2/board-omap3beagle.c
3 *
4 * Copyright (C) 2008 Texas Instruments
5 *
6 * Modified from mach-omap2/board-3430sdp.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/leds.h>
23#include <linux/gpio.h>
24#include <linux/input.h>
25#include <linux/gpio_keys.h>
26
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h>
30
31#include <mach/hardware.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/flash.h>
36
37#include <mach/board.h>
38#include <mach/common.h>
39#include <mach/gpmc.h>
40#include <mach/nand.h>
41
42
43#define GPMC_CS0_BASE 0x60
44#define GPMC_CS_SIZE 0x30
45
46#define NAND_BLOCK_SIZE SZ_128K
47
48static struct mtd_partition omap3beagle_nand_partitions[] = {
49 /* All the partition sizes are listed in terms of NAND block size */
50 {
51 .name = "X-Loader",
52 .offset = 0,
53 .size = 4 * NAND_BLOCK_SIZE,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 },
56 {
57 .name = "U-Boot",
58 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
59 .size = 15 * NAND_BLOCK_SIZE,
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 },
62 {
63 .name = "U-Boot Env",
64 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
65 .size = 1 * NAND_BLOCK_SIZE,
66 },
67 {
68 .name = "Kernel",
69 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
70 .size = 32 * NAND_BLOCK_SIZE,
71 },
72 {
73 .name = "File System",
74 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
75 .size = MTDPART_SIZ_FULL,
76 },
77};
78
79static struct omap_nand_platform_data omap3beagle_nand_data = {
80 .options = NAND_BUSWIDTH_16,
81 .parts = omap3beagle_nand_partitions,
82 .nr_parts = ARRAY_SIZE(omap3beagle_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84 .nand_setup = NULL,
85 .dev_ready = NULL,
86};
87
88static struct resource omap3beagle_nand_resource = {
89 .flags = IORESOURCE_MEM,
90};
91
92static struct platform_device omap3beagle_nand_device = {
93 .name = "omap2-nand",
94 .id = -1,
95 .dev = {
96 .platform_data = &omap3beagle_nand_data,
97 },
98 .num_resources = 1,
99 .resource = &omap3beagle_nand_resource,
100};
101
102static struct omap_uart_config omap3_beagle_uart_config __initdata = {
103 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
104};
105
106static void __init omap3_beagle_init_irq(void)
107{
108 omap2_init_common_hw();
109 omap_init_irq();
110 omap_gpio_init();
111}
112
113static struct platform_device omap3_beagle_lcd_device = {
114 .name = "omap3beagle_lcd",
115 .id = -1,
116};
117
118static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
119 .ctrl_name = "internal",
120};
121
122static struct gpio_led gpio_leds[] = {
123 {
124 .name = "beagleboard::usr0",
125 .default_trigger = "heartbeat",
126 .gpio = 150,
127 },
128 {
129 .name = "beagleboard::usr1",
130 .default_trigger = "mmc0",
131 .gpio = 149,
132 },
133};
134
135static struct gpio_led_platform_data gpio_led_info = {
136 .leds = gpio_leds,
137 .num_leds = ARRAY_SIZE(gpio_leds),
138};
139
140static struct platform_device leds_gpio = {
141 .name = "leds-gpio",
142 .id = -1,
143 .dev = {
144 .platform_data = &gpio_led_info,
145 },
146};
147
148static struct gpio_keys_button gpio_buttons[] = {
149 {
150 .code = BTN_EXTRA,
151 .gpio = 7,
152 .desc = "user",
153 .wakeup = 1,
154 },
155};
156
157static struct gpio_keys_platform_data gpio_key_info = {
158 .buttons = gpio_buttons,
159 .nbuttons = ARRAY_SIZE(gpio_buttons),
160};
161
162static struct platform_device keys_gpio = {
163 .name = "gpio-keys",
164 .id = -1,
165 .dev = {
166 .platform_data = &gpio_key_info,
167 },
168};
169
170static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
171 { OMAP_TAG_UART, &omap3_beagle_uart_config },
172 { OMAP_TAG_LCD, &omap3_beagle_lcd_config },
173};
174
175static struct platform_device *omap3_beagle_devices[] __initdata = {
176 &omap3_beagle_lcd_device,
177 &leds_gpio,
178 &keys_gpio,
179};
180
181static void __init omap3beagle_flash_init(void)
182{
183 u8 cs = 0;
184 u8 nandcs = GPMC_CS_NUM + 1;
185
186 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
187
188 /* find out the chip-select on which NAND exists */
189 while (cs < GPMC_CS_NUM) {
190 u32 ret = 0;
191 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
192
193 if ((ret & 0xC00) == 0x800) {
194 printk(KERN_INFO "Found NAND on CS%d\n", cs);
195 if (nandcs > GPMC_CS_NUM)
196 nandcs = cs;
197 }
198 cs++;
199 }
200
201 if (nandcs > GPMC_CS_NUM) {
202 printk(KERN_INFO "NAND: Unable to find configuration "
203 "in GPMC\n ");
204 return;
205 }
206
207 if (nandcs < GPMC_CS_NUM) {
208 omap3beagle_nand_data.cs = nandcs;
209 omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)
210 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
211 omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
212
213 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
214 if (platform_device_register(&omap3beagle_nand_device) < 0)
215 printk(KERN_ERR "Unable to register NAND device\n");
216 }
217}
218
219static void __init omap3_beagle_init(void)
220{
221 platform_add_devices(omap3_beagle_devices,
222 ARRAY_SIZE(omap3_beagle_devices));
223 omap_board_config = omap3_beagle_config;
224 omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
225 omap_serial_init();
226 omap3beagle_flash_init();
227}
228
229static void __init omap3_beagle_map_io(void)
230{
231 omap2_set_globals_343x();
232 omap2_map_common_io();
233}
234
235MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
236 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
237 .phys_io = 0x48000000,
238 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
239 .boot_params = 0x80000100,
240 .map_io = omap3_beagle_map_io,
241 .init_irq = omap3_beagle_init_irq,
242 .init_machine = omap3_beagle_init,
243 .timer = &omap_timer,
244MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
new file mode 100644
index 000000000000..e09aa59a399c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -0,0 +1,242 @@
1/*
2 * board-overo.c (Gumstix Overo)
3 *
4 * Initial code: Steve Sakoman <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/platform_device.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/flash.h>
37#include <asm/mach/map.h>
38
39#include <mach/board-overo.h>
40#include <mach/board.h>
41#include <mach/common.h>
42#include <mach/gpio.h>
43#include <mach/gpmc.h>
44#include <mach/hardware.h>
45#include <mach/nand.h>
46
47#define NAND_BLOCK_SIZE SZ_128K
48#define GPMC_CS0_BASE 0x60
49#define GPMC_CS_SIZE 0x30
50
51static struct mtd_partition overo_nand_partitions[] = {
52 {
53 .name = "xloader",
54 .offset = 0, /* Offset = 0x00000 */
55 .size = 4 * NAND_BLOCK_SIZE,
56 .mask_flags = MTD_WRITEABLE
57 },
58 {
59 .name = "uboot",
60 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
61 .size = 14 * NAND_BLOCK_SIZE,
62 },
63 {
64 .name = "uboot environment",
65 .offset = MTDPART_OFS_APPEND, /* Offset = 0x240000 */
66 .size = 2 * NAND_BLOCK_SIZE,
67 },
68 {
69 .name = "linux",
70 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
71 .size = 32 * NAND_BLOCK_SIZE,
72 },
73 {
74 .name = "rootfs",
75 .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
76 .size = MTDPART_SIZ_FULL,
77 },
78};
79
80static struct omap_nand_platform_data overo_nand_data = {
81 .parts = overo_nand_partitions,
82 .nr_parts = ARRAY_SIZE(overo_nand_partitions),
83 .dma_channel = -1, /* disable DMA in OMAP NAND driver */
84};
85
86static struct resource overo_nand_resource = {
87 .flags = IORESOURCE_MEM,
88};
89
90static struct platform_device overo_nand_device = {
91 .name = "omap2-nand",
92 .id = -1,
93 .dev = {
94 .platform_data = &overo_nand_data,
95 },
96 .num_resources = 1,
97 .resource = &overo_nand_resource,
98};
99
100
101static void __init overo_flash_init(void)
102{
103 u8 cs = 0;
104 u8 nandcs = GPMC_CS_NUM + 1;
105
106 u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
107
108 /* find out the chip-select on which NAND exists */
109 while (cs < GPMC_CS_NUM) {
110 u32 ret = 0;
111 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
112
113 if ((ret & 0xC00) == 0x800) {
114 printk(KERN_INFO "Found NAND on CS%d\n", cs);
115 if (nandcs > GPMC_CS_NUM)
116 nandcs = cs;
117 }
118 cs++;
119 }
120
121 if (nandcs > GPMC_CS_NUM) {
122 printk(KERN_INFO "NAND: Unable to find configuration "
123 "in GPMC\n ");
124 return;
125 }
126
127 if (nandcs < GPMC_CS_NUM) {
128 overo_nand_data.cs = nandcs;
129 overo_nand_data.gpmc_cs_baseaddr = (void *)
130 (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
131 overo_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
132
133 printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
134 if (platform_device_register(&overo_nand_device) < 0)
135 printk(KERN_ERR "Unable to register NAND device\n");
136 }
137}
138static struct omap_uart_config overo_uart_config __initdata = {
139 .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
140};
141
142static int __init overo_i2c_init(void)
143{
144 /* i2c2 pins are used for gpio */
145 omap_register_i2c_bus(3, 400, NULL, 0);
146 return 0;
147}
148
149static void __init overo_init_irq(void)
150{
151 omap2_init_common_hw();
152 omap_init_irq();
153 omap_gpio_init();
154}
155
156static struct platform_device overo_lcd_device = {
157 .name = "overo_lcd",
158 .id = -1,
159};
160
161static struct omap_lcd_config overo_lcd_config __initdata = {
162 .ctrl_name = "internal",
163};
164
165static struct omap_board_config_kernel overo_config[] __initdata = {
166 { OMAP_TAG_UART, &overo_uart_config },
167 { OMAP_TAG_LCD, &overo_lcd_config },
168};
169
170static struct platform_device *overo_devices[] __initdata = {
171 &overo_lcd_device,
172};
173
174static void __init overo_init(void)
175{
176 overo_i2c_init();
177 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
178 omap_board_config = overo_config;
179 omap_board_config_size = ARRAY_SIZE(overo_config);
180 omap_serial_init();
181 overo_flash_init();
182
183 if ((gpio_request(OVERO_GPIO_W2W_NRESET,
184 "OVERO_GPIO_W2W_NRESET") == 0) &&
185 (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
186 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
187 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
188 udelay(10);
189 gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
190 } else {
191 printk(KERN_ERR "could not obtain gpio for "
192 "OVERO_GPIO_W2W_NRESET\n");
193 }
194
195 if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
196 (gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
197 gpio_export(OVERO_GPIO_BT_XGATE, 0);
198 else
199 printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
200
201 if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
202 (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
203 gpio_export(OVERO_GPIO_BT_NRESET, 0);
204 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
205 mdelay(6);
206 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
207 } else {
208 printk(KERN_ERR "could not obtain gpio for "
209 "OVERO_GPIO_BT_NRESET\n");
210 }
211
212 if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
213 (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
214 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
215 else
216 printk(KERN_ERR "could not obtain gpio for "
217 "OVERO_GPIO_USBH_CPEN\n");
218
219 if ((gpio_request(OVERO_GPIO_USBH_NRESET,
220 "OVERO_GPIO_USBH_NRESET") == 0) &&
221 (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
222 gpio_export(OVERO_GPIO_USBH_NRESET, 0);
223 else
224 printk(KERN_ERR "could not obtain gpio for "
225 "OVERO_GPIO_USBH_NRESET\n");
226}
227
228static void __init overo_map_io(void)
229{
230 omap2_set_globals_343x();
231 omap2_map_common_io();
232}
233
234MACHINE_START(OVERO, "Gumstix Overo")
235 .phys_io = 0x48000000,
236 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
237 .boot_params = 0x80000100,
238 .map_io = overo_map_io,
239 .init_irq = overo_init_irq,
240 .init_machine = overo_init,
241 .timer = &omap_timer,
242MACHINE_END
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 149bfba43cfe..375ad27479cc 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -220,6 +220,11 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
220 220
221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
222 222
223 if (cpu_is_omap34xx()) {
224 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
225 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
226 }
227
223 /* caller is expected to have initialized CONFIG1 to cover 228 /* caller is expected to have initialized CONFIG1 to cover
224 * at least sync vs async 229 * at least sync vs async
225 */ 230 */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03c6ab1a3b1f..71a9de382d2d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -43,7 +43,9 @@
43 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
44 * default mapping provided here. 44 * default mapping provided here.
45 */ 45 */
46static struct map_desc omap2_io_desc[] __initdata = { 46
47#ifdef CONFIG_ARCH_OMAP24XX
48static struct map_desc omap24xx_io_desc[] __initdata = {
47 { 49 {
48 .virtual = L3_24XX_VIRT, 50 .virtual = L3_24XX_VIRT,
49 .pfn = __phys_to_pfn(L3_24XX_PHYS), 51 .pfn = __phys_to_pfn(L3_24XX_PHYS),
@@ -51,12 +53,39 @@ static struct map_desc omap2_io_desc[] __initdata = {
51 .type = MT_DEVICE 53 .type = MT_DEVICE
52 }, 54 },
53 { 55 {
54 .virtual = L4_24XX_VIRT, 56 .virtual = L4_24XX_VIRT,
55 .pfn = __phys_to_pfn(L4_24XX_PHYS), 57 .pfn = __phys_to_pfn(L4_24XX_PHYS),
56 .length = L4_24XX_SIZE, 58 .length = L4_24XX_SIZE,
57 .type = MT_DEVICE 59 .type = MT_DEVICE
60 },
61};
62
63#ifdef CONFIG_ARCH_OMAP2420
64static struct map_desc omap242x_io_desc[] __initdata = {
65 {
66 .virtual = DSP_MEM_24XX_VIRT,
67 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
68 .length = DSP_MEM_24XX_SIZE,
69 .type = MT_DEVICE
70 },
71 {
72 .virtual = DSP_IPI_24XX_VIRT,
73 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
74 .length = DSP_IPI_24XX_SIZE,
75 .type = MT_DEVICE
58 }, 76 },
77 {
78 .virtual = DSP_MMU_24XX_VIRT,
79 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
80 .length = DSP_MMU_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#endif
86
59#ifdef CONFIG_ARCH_OMAP2430 87#ifdef CONFIG_ARCH_OMAP2430
88static struct map_desc omap243x_io_desc[] __initdata = {
60 { 89 {
61 .virtual = L4_WK_243X_VIRT, 90 .virtual = L4_WK_243X_VIRT,
62 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 91 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
@@ -69,30 +98,90 @@ static struct map_desc omap2_io_desc[] __initdata = {
69 .length = OMAP243X_GPMC_SIZE, 98 .length = OMAP243X_GPMC_SIZE,
70 .type = MT_DEVICE 99 .type = MT_DEVICE
71 }, 100 },
101 {
102 .virtual = OMAP243X_SDRC_VIRT,
103 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
104 .length = OMAP243X_SDRC_SIZE,
105 .type = MT_DEVICE
106 },
107 {
108 .virtual = OMAP243X_SMS_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
110 .length = OMAP243X_SMS_SIZE,
111 .type = MT_DEVICE
112 },
113};
72#endif 114#endif
115#endif
116
117#ifdef CONFIG_ARCH_OMAP34XX
118static struct map_desc omap34xx_io_desc[] __initdata = {
73 { 119 {
74 .virtual = DSP_MEM_24XX_VIRT, 120 .virtual = L3_34XX_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS), 121 .pfn = __phys_to_pfn(L3_34XX_PHYS),
76 .length = DSP_MEM_24XX_SIZE, 122 .length = L3_34XX_SIZE,
77 .type = MT_DEVICE 123 .type = MT_DEVICE
78 }, 124 },
79 { 125 {
80 .virtual = DSP_IPI_24XX_VIRT, 126 .virtual = L4_34XX_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS), 127 .pfn = __phys_to_pfn(L4_34XX_PHYS),
82 .length = DSP_IPI_24XX_SIZE, 128 .length = L4_34XX_SIZE,
83 .type = MT_DEVICE 129 .type = MT_DEVICE
84 }, 130 },
85 { 131 {
86 .virtual = DSP_MMU_24XX_VIRT, 132 .virtual = L4_WK_34XX_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS), 133 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
88 .length = DSP_MMU_24XX_SIZE, 134 .length = L4_WK_34XX_SIZE,
135 .type = MT_DEVICE
136 },
137 {
138 .virtual = OMAP34XX_GPMC_VIRT,
139 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
140 .length = OMAP34XX_GPMC_SIZE,
141 .type = MT_DEVICE
142 },
143 {
144 .virtual = OMAP343X_SMS_VIRT,
145 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
146 .length = OMAP343X_SMS_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = OMAP343X_SDRC_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
152 .length = OMAP343X_SDRC_SIZE,
89 .type = MT_DEVICE 153 .type = MT_DEVICE
90 } 154 },
155 {
156 .virtual = L4_PER_34XX_VIRT,
157 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
158 .length = L4_PER_34XX_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = L4_EMU_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
164 .length = L4_EMU_34XX_SIZE,
165 .type = MT_DEVICE
166 },
91}; 167};
168#endif
92 169
93void __init omap2_map_common_io(void) 170void __init omap2_map_common_io(void)
94{ 171{
95 iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc)); 172#if defined(CONFIG_ARCH_OMAP2420)
173 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
174 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
175#endif
176
177#if defined(CONFIG_ARCH_OMAP2430)
178 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
179 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
180#endif
181
182#if defined(CONFIG_ARCH_OMAP34XX)
183 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
184#endif
96 185
97 /* Normally devicemaps_init() would flush caches and tlb after 186 /* Normally devicemaps_init() would flush caches and tlb after
98 * mdesc->map_io(), but we must also do it here because of the CPU 187 * mdesc->map_io(), but we must also do it here because of the CPU
@@ -112,11 +201,6 @@ void __init omap2_init_common_hw(void)
112 pwrdm_init(powerdomains_omap); 201 pwrdm_init(powerdomains_omap);
113 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 202 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
114 omap2_clk_init(); 203 omap2_clk_init();
115/*
116 * Need to Fix this for 2430
117 */
118#ifndef CONFIG_ARCH_OMAP2430
119 omap2_init_memory(); 204 omap2_init_memory();
120#endif
121 gpmc_init(); 205 gpmc_init();
122} 206}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index c39e26dc5ee3..d354e0fe4477 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -128,6 +128,8 @@ void __init omap_init_irq(void)
128 128
129 if (cpu_is_omap24xx()) 129 if (cpu_is_omap24xx())
130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE); 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
131 else if (cpu_is_omap34xx())
132 bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
131 133
132 omap_irq_bank_init_one(bank); 134 omap_irq_bank_init_one(bank);
133 135
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 6b49cc9cbdcb..48b01f4cebc5 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -102,6 +102,17 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
102 return prev; 102 return prev;
103} 103}
104 104
105#if !defined(CONFIG_ARCH_OMAP2)
106void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
107 u32 base_cs, u32 force_unlock)
108{
109}
110void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
111 u32 mem_type)
112{
113}
114#endif
115
105void omap2_init_memory_params(u32 force_lock_to_unlock_mode) 116void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
106{ 117{
107 unsigned long dll_cnt; 118 unsigned long dll_cnt;
@@ -166,6 +177,9 @@ void __init omap2_init_memory(void)
166{ 177{
167 u32 l; 178 u32 l;
168 179
180 if (!cpu_is_omap2420())
181 return;
182
169 l = sms_read_reg(SMS_SYSCONFIG); 183 l = sms_read_reg(SMS_SYSCONFIG);
170 l &= ~(0x3 << 3); 184 l &= ~(0x3 << 3);
171 l |= (0x2 << 3); 185 l |= (0x2 << 3);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 6188e2f97854..5558803cd99e 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -298,13 +298,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
298 298
299/* TLL - HSUSB: 12-pin TLL Port 1*/ 299/* TLL - HSUSB: 12-pin TLL Port 1*/
300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da, 300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec, 304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee, 306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc, 308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de, 310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
@@ -324,13 +324,13 @@ MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
324 324
325/* TLL - HSUSB: 12-pin TLL Port 2*/ 325/* TLL - HSUSB: 12-pin TLL Port 2*/
326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0, 326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4, 330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6, 332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT) 333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8, 334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN) 335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa, 336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
@@ -350,13 +350,13 @@ MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
350 350
351/* TLL - HSUSB: 12-pin TLL Port 3*/ 351/* TLL - HSUSB: 12-pin TLL Port 3*/
352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180, 352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168, 356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a, 358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT) 359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186, 360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184, 362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
@@ -373,6 +373,49 @@ MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172, 374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN) 375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
376
377/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
378MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
379 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
380MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
381 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
382MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
383 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
384MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
385 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
386MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
387 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
388MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
389 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
390
391/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
392MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
393 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
394MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
395 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
396MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
397 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
398MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
399 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
400MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
401 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
402MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
403 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
404
405/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
406MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
407 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
408MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
409 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
410MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
411 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
412MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
413 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
414MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
415 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
416MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
417 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
418
376}; 419};
377 420
378#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) 421#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
new file mode 100644
index 000000000000..2c7146136342
--- /dev/null
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -0,0 +1,179 @@
1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2007
7 * Texas Instruments Inc.
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * (C) Copyright 2004
11 * Texas Instruments, <www.ti.com>
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#include <linux/linkage.h>
30#include <asm/assembler.h>
31#include <mach/hardware.h>
32
33#include <mach/io.h>
34
35#include "sdrc.h"
36#include "cm.h"
37
38 .text
39
40/*
41 * Change frequency of core dpll
42 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
43 */
44ENTRY(omap3_sram_configure_core_dpll)
45 stmfd sp!, {r1-r12, lr} @ store regs to stack
46 cmp r3, #0x2
47 blne configure_sdrc
48 cmp r3, #0x2
49 blne lock_dll
50 cmp r3, #0x1
51 blne unlock_dll
52 bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53 bl configure_core_dpll
54 bl enable_sdrc
55 cmp r3, #0x1
56 blne wait_dll_unlock
57 cmp r3, #0x2
58 blne wait_dll_lock
59 cmp r3, #0x1
60 blne configure_sdrc
61 mov r0, #0 @ return value
62 ldmfd sp!, {r1-r12, pc} @ restore regs and return
63unlock_dll:
64 ldr r4, omap3_sdrc_dlla_ctrl
65 ldr r5, [r4]
66 orr r5, r5, #0x4
67 str r5, [r4]
68 bx lr
69lock_dll:
70 ldr r4, omap3_sdrc_dlla_ctrl
71 ldr r5, [r4]
72 bic r5, r5, #0x4
73 str r5, [r4]
74 bx lr
75sdram_in_selfrefresh:
76 mov r5, #0x0 @ Move 0 to R5
77 mcr p15, 0, r5, c7, c10, 5 @ memory barrier
78 ldr r4, omap3_sdrc_power @ read the SDRC_POWER register
79 ldr r5, [r4] @ read the contents of SDRC_POWER
80 orr r5, r5, #0x40 @ enable self refresh on idle req
81 str r5, [r4] @ write back to SDRC_POWER register
82 ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
83 ldr r5, [r4]
84 bic r5, r5, #0x2 @ disable iclk bit for SRDC
85 str r5, [r4]
86wait_sdrc_idle:
87 ldr r4, omap3_cm_idlest1_core
88 ldr r5, [r4]
89 and r5, r5, #0x2 @ check for SDRC idle
90 cmp r5, #2
91 bne wait_sdrc_idle
92 bx lr
93configure_core_dpll:
94 ldr r4, omap3_cm_clksel1_pll
95 ldr r5, [r4]
96 ldr r6, core_m2_mask_val @ modify m2 for core dpll
97 and r5, r5, r6
98 orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val
99 str r5, [r4]
100 mov r5, #0x800 @ wait for the clock to stabilise
101 cmp r3, #2
102 bne wait_clk_stable
103 bx lr
104wait_clk_stable:
105 subs r5, r5, #1
106 bne wait_clk_stable
107 nop
108 nop
109 nop
110 nop
111 nop
112 nop
113 nop
114 nop
115 nop
116 nop
117 bx lr
118enable_sdrc:
119 ldr r4, omap3_cm_iclken1_core
120 ldr r5, [r4]
121 orr r5, r5, #0x2 @ enable iclk bit for SDRC
122 str r5, [r4]
123wait_sdrc_idle1:
124 ldr r4, omap3_cm_idlest1_core
125 ldr r5, [r4]
126 and r5, r5, #0x2
127 cmp r5, #0
128 bne wait_sdrc_idle1
129 ldr r4, omap3_sdrc_power
130 ldr r5, [r4]
131 bic r5, r5, #0x40
132 str r5, [r4]
133 bx lr
134wait_dll_lock:
135 ldr r4, omap3_sdrc_dlla_status
136 ldr r5, [r4]
137 and r5, r5, #0x4
138 cmp r5, #0x4
139 bne wait_dll_lock
140 bx lr
141wait_dll_unlock:
142 ldr r4, omap3_sdrc_dlla_status
143 ldr r5, [r4]
144 and r5, r5, #0x4
145 cmp r5, #0x0
146 bne wait_dll_unlock
147 bx lr
148configure_sdrc:
149 ldr r4, omap3_sdrc_rfr_ctrl
150 str r0, [r4]
151 ldr r4, omap3_sdrc_actim_ctrla
152 str r1, [r4]
153 ldr r4, omap3_sdrc_actim_ctrlb
154 str r2, [r4]
155 bx lr
156
157omap3_sdrc_power:
158 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
159omap3_cm_clksel1_pll:
160 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
161omap3_cm_idlest1_core:
162 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
163omap3_cm_iclken1_core:
164 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
165omap3_sdrc_rfr_ctrl:
166 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
167omap3_sdrc_actim_ctrla:
168 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
169omap3_sdrc_actim_ctrlb:
170 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
171omap3_sdrc_dlla_status:
172 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
173omap3_sdrc_dlla_ctrl:
174 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
175core_m2_mask_val:
176 .word 0x07FFFFFF
177
178ENTRY(omap3_sram_configure_core_dpll_sz)
179 .word . - omap3_sram_configure_core_dpll
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