diff options
| author | Grazvydas Ignotas <notasas@gmail.com> | 2012-05-05 19:56:52 -0400 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2012-05-09 13:35:48 -0400 |
| commit | d723c17ab6e7f04f49cd715d5de4d4f6edf7b28a (patch) | |
| tree | 87cc4b898126226aa243868a106e323bbaa6ef95 /arch/arm/mach-omap2 | |
| parent | 33ee0db53994a574b76e0261fc9a3daf71f4b0d7 (diff) | |
ARM: OMAP2+: remove incorrect irq_chip ack field
Each irq_chip for the main interrupt controller has offsets set for irq
masking registers, which added to respective base results in a pointer
to appropriate hardware register. However this is not correct for
INTC_CONTROL as there is only one INTC_CONTROL register. This does not
cause problems because generic ack code is never called, but remove
this assignment to avoid confusion.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/irq.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 65f0d2571c9a..c11e8a84c947 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
| @@ -149,7 +149,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | |||
| 149 | ct->chip.irq_mask = irq_gc_mask_disable_reg; | 149 | ct->chip.irq_mask = irq_gc_mask_disable_reg; |
| 150 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; | 150 | ct->chip.irq_unmask = irq_gc_unmask_enable_reg; |
| 151 | 151 | ||
| 152 | ct->regs.ack = INTC_CONTROL; | ||
| 153 | ct->regs.enable = INTC_MIR_CLEAR0; | 152 | ct->regs.enable = INTC_MIR_CLEAR0; |
| 154 | ct->regs.disable = INTC_MIR_SET0; | 153 | ct->regs.disable = INTC_MIR_SET0; |
| 155 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | 154 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |