Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (163 commits)
  omap: complete removal of machine_desc.io_pg_offst and .phys_io
  omap: UART: fix wakeup registers for OMAP24xx UART2
  omap: Fix spotty MMC voltages
  ASoC: OMAP4: MCPDM: Remove unnecessary include of plat/control.h
  serial: omap-serial: fix signess error
  OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish
  omap: dma: Fix buffering disable bit setting for omap24xx
  omap: serial: Fix the boot-up crash/reboot without CONFIG_PM
  OMAP3: PM: fix scratchpad memory accesses for off-mode
  omap4: pandaboard: enable the ehci port on pandaboard
  omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set
  omap4: pandaboard: remove unused hsmmc definition
  OMAP: McBSP: Remove null omap44xx ops comment
  OMAP: McBSP: Swap CLKS source definition
  OMAP: McBSP: Fix CLKR and FSR signal muxing
  OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks
  OMAP: control: move plat-omap/control.h to mach-omap2/control.h
  OMAP: split plat-omap/common.c
  OMAP: McBSP: implement functional clock switching via clock framework
  OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c
  ...

Fixed up trivial conflicts in arch/arm/mach-omap2/
{board-zoom-peripherals.c,devices.c} as per Tony

96 files changed, 10349 insertions, 2761 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf0a7aa..ab784bfde908 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -11,9 +11,8 @@ config ARCH_OMAP2PLUS_TYPICAL
         select PM_RUNTIME
         select VFP
         select NEON if ARCH_OMAP3 || ARCH_OMAP4
-        select SERIAL_8250
-        select SERIAL_CORE_CONSOLE
-        select SERIAL_8250_CONSOLE
+        select SERIAL_OMAP
+        select SERIAL_OMAP_CONSOLE
         select I2C
         select I2C_OMAP
         select MFD
@@ -35,7 +34,7 @@ config ARCH_OMAP3
         default y
         select CPU_V7
         select USB_ARCH_HAS_EHCI
-        select ARM_L1_CACHE_SHIFT_6
+        select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -43,6 +42,8 @@ config ARCH_OMAP4
         depends on ARCH_OMAP2PLUS
         select CPU_V7
         select ARM_GIC
+        select PL310_ERRATA_588369
+        select ARM_ERRATA_720789
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
@@ -99,20 +100,20 @@ config MACH_OMAP2_TUSB6010
 
 config MACH_OMAP_H4
         bool "OMAP 2420 H4 board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2420
         default y
         select OMAP_PACKAGE_ZAF
         select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
         bool "OMAP 2420 Apollon board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2420
         default y
         select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
         bool "OMAP 2430 SDP board"
-        depends on ARCH_OMAP2
+        depends on ARCH_OMAP2430
         default y
         select OMAP_PACKAGE_ZAC
 
@@ -135,6 +136,26 @@ config MACH_OMAP_LDP
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_OMAP3530_LV_SOM
+        bool "OMAP3 Logic 3530 LV SOM board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP3530 SOM Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit
+
+config MACH_OMAP3_TORPEDO
+        bool "OMAP3 Logic 35x Torpedo board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+        default y
+        help
+         Support for the LogicPD OMAP35x Torpedo Development kit
+         for full description please see the products webpage at
+         http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit
+
 config MACH_OVERO
         bool "Gumstix Overo board"
         depends on ARCH_OMAP3
@@ -200,12 +221,18 @@ config MACH_OMAP_ZOOM2
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBP
+        select SERIAL_8250
+        select SERIAL_CORE_CONSOLE
+        select SERIAL_8250_CONSOLE
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
@@ -214,12 +241,25 @@ config MACH_CM_T35
         select OMAP_PACKAGE_CUS
         select OMAP_MUX
 
+config MACH_CM_T3517
+        bool "CompuLab CM-T3517 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+        select OMAP_MUX
+
 config MACH_IGEP0020
         bool "IGEP v2 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_IGEP0030
+        bool "IGEP OMAP3 module"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+
 config MACH_SBC3530
         bool "OMAP3 SBC STALKER board"
         depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e920f5..7352412e4917 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,10 @@
 #
 
 # Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
+         common.o
 
-omap-2-3-common                         = irq.o sdrc.o
+omap-2-3-common                         = irq.o sdrc.o prm2xxx_3xxx.o
 hwmod-common                            = omap_hwmod.o \
                                           omap_hwmod_common_data.o
 prcm-common                             = prcm.o powerdomain.o
@@ -15,7 +16,7 @@ clock-common				= clock.o clock_common_data.o \
 
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -49,14 +50,18 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a
 
+ifeq ($(CONFIG_PM_VERBOSE),y)
+CFLAGS_pm_bus.o                         += -DDEBUG
+endif
+
 endif
 
 # PRCM
@@ -87,6 +92,7 @@ obj-$(CONFIG_ARCH_OMAP2430)		+= opp2430_data.o
 obj-$(CONFIG_ARCH_OMAP2420)             += omap_hwmod_2420_data.o
 obj-$(CONFIG_ARCH_OMAP2430)             += omap_hwmod_2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
@@ -115,6 +121,10 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o \
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o \
                                            board-flash.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o \
@@ -146,8 +156,11 @@ obj-$(CONFIG_MACH_OMAP_3630SDP)		+= board-3630sdp.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            hsmmc.o
+obj-$(CONFIG_MACH_IGEP0030)             += board-igep0030.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
@@ -174,3 +187,6 @@ obj-y					+= $(nand-m) $(nand-y)
 
 smc91x-$(CONFIG_SMC91X)                 := gpmc-smc91x.o
 obj-y                                   += $(smc91x-m) $(smc91x-y)
+
+smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
+obj-y                                   += $(smsc911x-m) $(smsc911x-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index b857ce484510..b527f8d187ad 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mmc/host.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
 #include <linux/err.h>
@@ -190,7 +191,7 @@ static int __init omap2430_i2c_init(void)
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .ext_clock      = 1,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index a5b095cf2adc..4e3742c512b8 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,6 +24,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -38,15 +39,14 @@
 #include <plat/gpmc.h>
 #include <plat/display.h>
 
-#include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
-#include <mach/board-flash.h>
-
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
 #include "hsmmc.h"
 #include "pm.h"
+#include "control.h"
 
 #define CONFIG_DISABLE_HFCLK 1
 
@@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = {
         {1, 10000, 30000, 300000},
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_A),
@@ -353,12 +353,12 @@ static struct omap2_hsmmc_info mmc[] = {
                 /* 8 bits (default) requires S6.3 == ON,
                  * so the SIM card isn't used; else 4 bits.
                  */
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 4,
         },
         {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 7,
         },
         {}      /* Terminator */
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index fd27ac0860b0..bbcf580fa097 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -21,8 +21,8 @@
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
-#include <mach/board-flash.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
@@ -208,7 +208,6 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        omap_serial_init();
         zoom_peripherals_init();
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 0b6a65f3a10a..69a4ae971e41 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
+#include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/leds.h>
 
@@ -31,15 +32,18 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+
 #include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
 
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
+#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
+#define OMAP4_SFH7741_ENABLE_GPIO               188
 
 static struct gpio_led sdp4430_gpio_leds[] = {
         {
@@ -77,11 +81,47 @@ static struct gpio_led sdp4430_gpio_leds[] = {
 
 };
 
+static struct gpio_keys_button sdp4430_gpio_keys[] = {
+        {
+                .desc                   = "Proximity Sensor",
+                .type                   = EV_SW,
+                .code                   = SW_FRONT_PROXIMITY,
+                .gpio                   = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
+                .active_low             = 0,
+        }
+};
+
 static struct gpio_led_platform_data sdp4430_led_data = {
         .leds   = sdp4430_gpio_leds,
         .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
 };
 
+static int omap_prox_activate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
+        return 0;
+}
+
+static void omap_prox_deactivate(struct device *dev)
+{
+        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
+}
+
+static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
+        .buttons        = sdp4430_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(sdp4430_gpio_keys),
+        .enable         = omap_prox_activate,
+        .disable        = omap_prox_deactivate,
+};
+
+static struct platform_device sdp4430_gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &sdp4430_gpio_keys_data,
+        },
+};
+
 static struct platform_device sdp4430_leds_gpio = {
         .name   = "leds-gpio",
         .id     = -1,
@@ -161,6 +201,7 @@ static struct platform_device sdp4430_lcd_device = {
 
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_lcd_device,
+        &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
 };
 
@@ -193,15 +234,16 @@ static struct omap_musb_board_data musb_board_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
         },
         {
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
+                .ocr_mask       = MMC_VDD_29_30,
         },
         {}      /* Terminator */
 };
@@ -235,8 +277,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
 
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed %s\n", __func__);
+                return;
+        }
+        pdata = dev->platform_data;
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
 
@@ -412,6 +460,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
                 I2C_BOARD_INFO("tmp105", 0x48),
         },
 };
+static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("hmc5843", 0x1e),
+        },
+};
 static int __init omap4_i2c_init(void)
 {
         /*
@@ -423,14 +476,36 @@ static int __init omap4_i2c_init(void)
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-        omap_register_i2c_bus(4, 400, NULL, 0);
+        omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
+                                ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
         return 0;
 }
+
+static void __init omap_sfh7741prox_init(void)
+{
+        int  error;
+
+        error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741");
+        if (error < 0) {
+                pr_err("%s:failed to request GPIO %d, error %d\n",
+                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
+                return;
+        }
+
+        error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0);
+        if (error < 0) {
+                pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n",
+                         __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
+                gpio_free(OMAP4_SFH7741_ENABLE_GPIO);
+        }
+}
+
 static void __init omap_4430sdp_init(void)
 {
         int status;
 
         omap4_i2c_init();
+        omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index e1f8dda62799..07399505312b 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -33,11 +33,11 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/usb.h>
 #include <plat/display.h>
 
 #include "mux.h"
+#include "control.h"
 
 #define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
 
@@ -125,7 +125,7 @@ static void am3517_disable_ethernet_int(void)
         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 
-void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
+static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 {
         unsigned int regval;
 
@@ -160,7 +160,6 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
 static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("s35390a", 0x30),
-                .type           = "s35390a",
         },
 };
 
@@ -368,7 +367,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
         .default_device = &am3517_evm_lcd_device,
 };
 
-struct platform_device am3517_evm_dss_device = {
+static struct platform_device am3517_evm_dss_device = {
         .name           = "omapdss",
         .id             = -1,
         .dev            = {
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 68f07f5f441a..2c6db1aaeb29 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -39,9 +39,9 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
-#include <plat/control.h>
 
 #include "mux.h"
+#include "control.h"
 
 /* LED & Switch macros */
 #define LED0_GPIO13             13
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 934d9380c372..63f764e2af3f 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -31,6 +31,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
@@ -237,8 +238,6 @@ static inline void cm_t35_init_nand(void) {}
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 #include <linux/spi/ads7846.h>
 
-#include <plat/mcspi.h>
-
 static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .turbo_mode     = 0,
         .single_channel = 1,    /* 0: slave, 1: master */
@@ -558,7 +557,7 @@ static struct twl4030_usb_data cm_t35_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int cm_t35_keymap[] = {
+static uint32_t cm_t35_keymap[] = {
         KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
         KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
         KEY(2, 0, KEY_RIGHT),   KEY(2, 1, KEY_C),       KEY(2, 2, KEY_D),
@@ -579,14 +578,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
 
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .transceiver    = 1,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
new file mode 100644
index 000000000000..1dd303e9a267
--- /dev/null
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -0,0 +1,292 @@
+/*
+ * linux/arch/arm/mach-omap2/board-cm-t3517.c
+ *
+ * Support for the CompuLab CM-T3517 modules
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/rtc-v3020.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/can/platform/ti_hecc.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/usb.h>
+#include <plat/nand.h>
+#include <plat/gpmc.h>
+
+#include <mach/am35xx.h>
+
+#include "mux.h"
+#include "control.h"
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led cm_t3517_leds[] = {
+        [0] = {
+                .gpio                   = 186,
+                .name                   = "cm-t3517:green",
+                .default_trigger        = "heartbeat",
+                .active_low             = 0,
+        },
+};
+
+static struct gpio_led_platform_data cm_t3517_led_pdata = {
+        .num_leds       = ARRAY_SIZE(cm_t3517_leds),
+        .leds           = cm_t3517_leds,
+};
+
+static struct platform_device cm_t3517_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &cm_t3517_led_pdata,
+        },
+};
+
+static void __init cm_t3517_init_leds(void)
+{
+        platform_device_register(&cm_t3517_led_device);
+}
+#else
+static inline void cm_t3517_init_leds(void) {}
+#endif
+
+#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE)
+static struct resource cm_t3517_hecc_resources[] = {
+        {
+                .start  = AM35XX_IPSS_HECC_BASE,
+                .end    = AM35XX_IPSS_HECC_BASE + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_35XX_HECC0_IRQ,
+                .end    = INT_35XX_HECC0_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ti_hecc_platform_data cm_t3517_hecc_pdata = {
+        .scc_hecc_offset        = AM35XX_HECC_SCC_HECC_OFFSET,
+        .scc_ram_offset         = AM35XX_HECC_SCC_RAM_OFFSET,
+        .hecc_ram_offset        = AM35XX_HECC_RAM_OFFSET,
+        .mbx_offset             = AM35XX_HECC_MBOX_OFFSET,
+        .int_line               = AM35XX_HECC_INT_LINE,
+        .version                = AM35XX_HECC_VERSION,
+};
+
+static struct platform_device cm_t3517_hecc_device = {
+        .name           = "ti_hecc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(cm_t3517_hecc_resources),
+        .resource       = cm_t3517_hecc_resources,
+        .dev            = {
+                .platform_data  = &cm_t3517_hecc_pdata,
+        },
+};
+
+static void cm_t3517_init_hecc(void)
+{
+        platform_device_register(&cm_t3517_hecc_device);
+}
+#else
+static inline void cm_t3517_init_hecc(void) {}
+#endif
+
+#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE)
+#define RTC_IO_GPIO             (153)
+#define RTC_WR_GPIO             (154)
+#define RTC_RD_GPIO             (160)
+#define RTC_CS_GPIO             (163)
+
+struct v3020_platform_data cm_t3517_v3020_pdata = {
+        .use_gpio       = 1,
+        .gpio_cs        = RTC_CS_GPIO,
+        .gpio_wr        = RTC_WR_GPIO,
+        .gpio_rd        = RTC_RD_GPIO,
+        .gpio_io        = RTC_IO_GPIO,
+};
+
+static struct platform_device cm_t3517_rtc_device = {
+        .name           = "v3020",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &cm_t3517_v3020_pdata,
+        }
+};
+
+static void __init cm_t3517_init_rtc(void)
+{
+        platform_device_register(&cm_t3517_rtc_device);
+}
+#else
+static inline void cm_t3517_init_rtc(void) {}
+#endif
+
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
+#define HSUSB1_RESET_GPIO       (146)
+#define HSUSB2_RESET_GPIO       (147)
+#define USB_HUB_RESET_GPIO      (152)
+
+static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = {
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
+        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
+        .reset_gpio_port[2]  = -EINVAL,
+};
+
+static int cm_t3517_init_usbh(void)
+{
+        int err;
+
+        err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst");
+        if (err) {
+                pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                gpio_direction_output(USB_HUB_RESET_GPIO, 0);
+                udelay(10);
+                gpio_set_value(USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+
+        usb_ehci_init(&cm_t3517_ehci_pdata);
+
+        return 0;
+}
+#else
+static inline int cm_t3517_init_usbh(void)
+{
+        return 0;
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+#define NAND_BLOCK_SIZE         SZ_128K
+
+static struct mtd_partition cm_t3517_nand_partitions[] = {
+        {
+                .name           = "xloader",
+                .offset         = 0,                    /* Offset = 0x00000 */
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "uboot",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+                .size           = 15 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "uboot environment",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
+                .size           = 2 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "linux",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+                .size           = 32 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "rootfs",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_nand_platform_data cm_t3517_nand_data = {
+        .parts                  = cm_t3517_nand_partitions,
+        .nr_parts               = ARRAY_SIZE(cm_t3517_nand_partitions),
+        .dma_channel            = -1,   /* disable DMA in OMAP NAND driver */
+        .cs                     = 0,
+};
+
+static void __init cm_t3517_init_nand(void)
+{
+        if (gpmc_nand_init(&cm_t3517_nand_data) < 0)
+                pr_err("CM-T3517: NAND initialization failed\n");
+}
+#else
+static inline void cm_t3517_init_nand(void) {}
+#endif
+
+static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
+};
+
+static void __init cm_t3517_init_irq(void)
+{
+        omap_board_config = cm_t3517_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
+
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+static struct omap_board_mux board_mux[] __initdata = {
+        /* GPIO186 - Green LED */
+        OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* RTC GPIOs: IO, WR#, RD#, CS# */
+        OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+        /* HSUSB1 RESET */
+        OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* HSUSB2 RESET */
+        OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* CM-T3517 USB HUB nRESET */
+        OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+static void __init cm_t3517_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+        cm_t3517_init_leds();
+        cm_t3517_init_nand();
+        cm_t3517_init_rtc();
+        cm_t3517_init_usbh();
+        cm_t3517_init_hecc();
+}
+
+MACHINE_START(CM_T3517, "Compulab CM-T3517")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = cm_t3517_init_irq,
+        .init_machine   = cm_t3517_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 2205c20a4cdb..067f4379c87f 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -44,7 +45,6 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 #include <plat/display.h>
 
 #include <plat/mcspi.h>
@@ -58,6 +58,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -105,7 +106,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -198,7 +199,7 @@ static struct platform_device devkit8000_dss_device = {
 static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index ac834aa7abf6..fd38c05bb47f 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -21,7 +21,8 @@
 #include <plat/nand.h>
 #include <plat/onenand.h>
 #include <plat/tc.h>
-#include <mach/board-flash.h>
+
+#include "board-flash.h"
 
 #define REG_FPGA_REV                    0x10
 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index b2242ae2bb6f..69befe00dd2f 100644
--- a/arch/arm/mach-omap2/include/mach/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -26,3 +26,5 @@ struct flash_partitions {
 
 extern void board_flash_init(struct flash_partitions [],
                                 char chip_sel[][GPMC_CS_NUM]);
+extern void board_nand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 69064b1c6a75..b1c2c9a11c38 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -48,10 +48,22 @@ static void __init omap_generic_init(void)
 
 static void __init omap_generic_map_io(void)
 {
-        omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
-        omap242x_map_common_io();
+        if (cpu_is_omap242x()) {
+                omap2_set_globals_242x();
+                omap242x_map_common_io();
+        } else if (cpu_is_omap243x()) {
+                omap2_set_globals_243x();
+                omap243x_map_common_io();
+        } else if (cpu_is_omap34xx()) {
+                omap2_set_globals_3xxx();
+                omap34xx_map_common_io();
+        } else if (cpu_is_omap44xx()) {
+                omap2_set_globals_443x();
+                omap44xx_map_common_io();
+        }
 }
 
+/* XXX This machine entry name should be updated */
 MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
         .boot_params    = 0x80000100,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index cc39fc866524..929993b4bf26 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -31,7 +31,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/control.h>
 #include <mach/gpio.h>
 #include <plat/usb.h>
 #include <plat/board.h>
@@ -42,6 +41,7 @@
 #include <plat/gpmc.h>
 
 #include "mux.h"
+#include "control.h"
 
 #define H4_FLASH_CS     0
 #define H4_SMC91X_CS    1
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index b62a68ba069b..5e035a58b809 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -20,6 +20,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,12 +39,61 @@
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
 #define IGEP2_GPIO_USBH_NRESET  24
-#define IGEP2_GPIO_LED0_GREEN   26
-#define IGEP2_GPIO_LED0_RED     27
-#define IGEP2_GPIO_LED1_RED     28
-#define IGEP2_GPIO_DVI_PUP      170
-#define IGEP2_GPIO_WIFI_NPD     94
-#define IGEP2_GPIO_WIFI_NRESET  95
+#define IGEP2_GPIO_LED0_GREEN   26
+#define IGEP2_GPIO_LED0_RED     27
+#define IGEP2_GPIO_LED1_RED     28
+#define IGEP2_GPIO_DVI_PUP      170
+
+#define IGEP2_RB_GPIO_WIFI_NPD     94
+#define IGEP2_RB_GPIO_WIFI_NRESET  95
+#define IGEP2_RB_GPIO_BT_NRESET    137
+#define IGEP2_RC_GPIO_WIFI_NPD     138
+#define IGEP2_RC_GPIO_WIFI_NRESET  139
+#define IGEP2_RC_GPIO_BT_NRESET    137
+
+/*
+ * IGEP2 Hardware Revision Table
+ *
+ *  --------------------------------------------------------------------------
+ * | Id. | Hw Rev.            | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET |
+ *  --------------------------------------------------------------------------
+ * |  0  | B                  |   high   |  gpio94  |   gpio95    |     -     |
+ * |  0  | B/C (B-compatible) |   high   |  gpio94  |   gpio95    |  gpio137  |
+ * |  1  | C                  |   low    |  gpio138 |   gpio139   |  gpio137  |
+ *  --------------------------------------------------------------------------
+ */
+
+#define IGEP2_BOARD_HWREV_B     0
+#define IGEP2_BOARD_HWREV_C     1
+
+static u8 hwrev;
+
+static void __init igep2_get_revision(void)
+{
+        u8 ret;
+
+        omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
+
+        if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) &&
+            (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) {
+                ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
+                if (ret == 0) {
+                        pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
+                        hwrev = IGEP2_BOARD_HWREV_C;
+                } else if (ret ==  1) {
+                        pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
+                        hwrev = IGEP2_BOARD_HWREV_B;
+                } else {
+                        pr_err("IGEP2: Unknown Hardware Revision\n");
+                        hwrev = -1;
+                }
+        } else {
+                pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
+                pr_err("IGEP2: Unknown Hardware Revision\n");
+        }
+
+        gpio_free(IGEP2_GPIO_LED1_RED);
+}
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
         defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
@@ -107,7 +157,7 @@ static struct platform_device igep2_onenand_device = {
         },
 };
 
-void __init igep2_flash_init(void)
+static void __init igep2_flash_init(void)
 {
         u8              cs = 0;
         u8              onenandcs = GPMC_CS_NUM + 1;
@@ -141,7 +191,7 @@ void __init igep2_flash_init(void)
 }
 
 #else
-void __init igep2_flash_init(void) {}
+static void __init igep2_flash_init(void) {}
 #endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -211,10 +261,6 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = {
         .supply         = "vmmc",
 };
 
-static struct regulator_consumer_supply igep2_vmmc2_supply = {
-        .supply         = "vmmc",
-};
-
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep2_vmmc1 = {
         .constraints = {
@@ -230,37 +276,95 @@ static struct regulator_init_data igep2_vmmc1 = {
         .consumer_supplies      = &igep2_vmmc1_supply,
 };
 
-/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */
-static struct regulator_init_data igep2_vmmc2 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc2_supply,
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
+#endif
         {}      /* Terminator */
 };
 
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep2_gpio_leds[] = {
+        [0] = {
+                .name                   = "gpio-led:red:d0",
+                .gpio                   = IGEP2_GPIO_LED0_RED,
+                .default_trigger        = "default-off"
+        },
+        [1] = {
+                .name                   = "gpio-led:green:d0",
+                .gpio                   = IGEP2_GPIO_LED0_GREEN,
+                .default_trigger        = "default-off",
+        },
+        [2] = {
+                .name                   = "gpio-led:red:d1",
+                .gpio                   = IGEP2_GPIO_LED1_RED,
+                .default_trigger        = "default-off",
+        },
+        [3] = {
+                .name                   = "gpio-led:green:d1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = -EINVAL, /* gets replaced */
+        },
+};
+
+static struct gpio_led_platform_data igep2_led_pdata = {
+        .leds           = igep2_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
+};
+
+static struct platform_device igep2_led_device = {
+         .name   = "leds-gpio",
+         .id     = -1,
+         .dev    = {
+                 .platform_data  =  &igep2_led_pdata,
+        },
+};
+
+static void __init igep2_leds_init(void)
+{
+        platform_device_register(&igep2_led_device);
+}
+
+#else
+static inline void igep2_leds_init(void)
+{
+        if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED0_RED, 0);
+                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
+
+        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
+                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
+
+        if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
+            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
+                gpio_export(IGEP2_GPIO_LED1_RED, 0);
+                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
+
+}
+#endif
+
 static int igep2_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -268,20 +372,48 @@ static int igep2_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
+        /*
+         * link regulators to MMC adapters ... we "know" the
          * regulators will be set up only *after* we return.
-        */
+         */
         igep2_vmmc1_supply.dev = mmc[0].dev;
-        igep2_vmmc2_supply.dev = mmc[1].dev;
+
+        /*
+         * REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+        if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) ||
+            (gpio_direction_input(gpio + 1) < 0))
+                pr_err("IGEP2: Could not obtain gpio for EHCI NOC");
+
+        /*
+         * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN
+         * (out, active low)
+         */
+        if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) ||
+            (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0))
+                pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
+
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
+            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
+                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
+        } else
+                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n");
+#else
+        igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
 
         return 0;
 };
 
-static struct twl4030_gpio_platform_data igep2_gpio_data = {
+static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
-        .use_leds       = false,
+        .use_leds       = true,
         .setup          = igep2_twl_gpio_setup,
 };
 
@@ -355,47 +487,6 @@ static void __init igep2_display_init(void)
                 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
 }
 
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-#include <linux/leds.h>
-
-static struct gpio_led igep2_gpio_leds[] = {
-        {
-                .name = "led0:red",
-                .gpio = IGEP2_GPIO_LED0_RED,
-        },
-        {
-                .name = "led0:green",
-                .default_trigger = "heartbeat",
-                .gpio = IGEP2_GPIO_LED0_GREEN,
-        },
-        {
-                .name = "led1:red",
-                .gpio = IGEP2_GPIO_LED1_RED,
-        },
-};
-
-static struct gpio_led_platform_data igep2_led_pdata = {
-        .leds           = igep2_gpio_leds,
-        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
-};
-
-static struct platform_device igep2_led_device = {
-         .name   = "leds-gpio",
-         .id     = -1,
-         .dev    = {
-                 .platform_data  =  &igep2_led_pdata,
-        },
-};
-
-static void __init igep2_init_led(void)
-{
-        platform_device_register(&igep2_led_device);
-}
-
-#else
-static inline void igep2_init_led(void) {}
-#endif
-
 static struct platform_device *igep2_devices[] __initdata = {
         &igep2_dss_device,
 };
@@ -425,14 +516,13 @@ static struct twl4030_platform_data igep2_twldata = {
         /* platform_data for children goes here */
         .usb            = &igep2_usb_data,
         .codec          = &igep2_codec_data,
-        .gpio           = &igep2_gpio_data,
+        .gpio           = &igep2_twl4030_gpio_pdata,
         .vmmc1          = &igep2_vmmc1,
-        .vmmc2          = &igep2_vmmc2,
         .vpll2          = &igep2_vpll2,
 
 };
 
-static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = {
+static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("twl4030", 0x48),
                 .flags          = I2C_CLIENT_WAKE,
@@ -441,14 +531,29 @@ static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = {
         },
 };
 
-static int __init igep2_i2c_init(void)
+static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("eeprom", 0x50),
+        },
+};
+
+static void __init igep2_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo,
-                        ARRAY_SIZE(igep2_i2c_boardinfo));
-        /* Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
-        return 0;
+        int ret;
+
+        ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo,
+                ARRAY_SIZE(igep2_i2c1_boardinfo));
+        if (ret)
+                pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret);
+
+        /*
+         * Bus 3 is attached to the DVI port where devices like the pico DLP
+         * projector don't work reliably with 400kHz
+         */
+        ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
+                ARRAY_SIZE(igep2_i2c3_boardinfo));
+        if (ret)
+                pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
 }
 
 static struct omap_musb_board_data musb_board_data = {
@@ -476,9 +581,57 @@ static struct omap_board_mux board_mux[] __initdata = {
 #define board_mux       NULL
 #endif
 
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+
+static void __init igep2_wlan_bt_init(void)
+{
+        unsigned npd, wreset, btreset;
+
+        /* GPIO's for WLAN-BT combo depends on hardware revision */
+        if (hwrev == IGEP2_BOARD_HWREV_B) {
+                npd = IGEP2_RB_GPIO_WIFI_NPD;
+                wreset = IGEP2_RB_GPIO_WIFI_NRESET;
+                btreset = IGEP2_RB_GPIO_BT_NRESET;
+        } else if (hwrev == IGEP2_BOARD_HWREV_C) {
+                npd = IGEP2_RC_GPIO_WIFI_NPD;
+                wreset = IGEP2_RC_GPIO_WIFI_NRESET;
+                btreset = IGEP2_RC_GPIO_BT_NRESET;
+        } else
+                return;
+
+        /* Set GPIO's for  WLAN-BT combo module */
+        if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) &&
+            (gpio_direction_output(npd, 1) == 0)) {
+                gpio_export(npd, 0);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n");
+
+        if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) &&
+            (gpio_direction_output(wreset, 1) == 0)) {
+                gpio_export(wreset, 0);
+                gpio_set_value(wreset, 0);
+                udelay(10);
+                gpio_set_value(wreset, 1);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n");
+
+        if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) &&
+            (gpio_direction_output(btreset, 1) == 0)) {
+                gpio_export(btreset, 0);
+        } else
+                pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n");
+}
+#else
+static inline void __init igep2_wlan_bt_init(void) { }
+#endif
+
 static void __init igep2_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        /* Get IGEP2 hardware revision */
+        igep2_get_revision();
+        /* Register I2C busses and drivers */
         igep2_i2c_init();
         platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
         omap_serial_init();
@@ -486,50 +639,16 @@ static void __init igep2_init(void)
         usb_ehci_init(&ehci_pdata);
 
         igep2_flash_init();
-        igep2_init_led();
+        igep2_leds_init();
         igep2_display_init();
         igep2_init_smsc911x();
 
-        /* GPIO userspace leds */
-#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
-        if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
-
-        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
-
-        if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_LED1_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
-#endif
-
-        /* GPIO W-LAN + Bluetooth combo module */
-        if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NPD, 0);
-/*              gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n");
+        /*
+         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
+         */
+        igep2_wlan_bt_init();
 
-        if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) {
-                gpio_export(IGEP2_GPIO_WIFI_NRESET, 0);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0);
-                udelay(10);
-                gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1);
-        } else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n");
 }
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
new file mode 100644
index 000000000000..22b0b253e16b
--- /dev/null
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (C) 2010 - ISEE 2007 SL
+ *
+ * Modified from mach-omap2/board-generic.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/usb.h>
+#include <plat/onenand.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-numonyx-m65kxxxxam.h"
+
+#define IGEP3_GPIO_LED0_GREEN   54
+#define IGEP3_GPIO_LED0_RED     53
+#define IGEP3_GPIO_LED1_RED     16
+
+#define IGEP3_GPIO_WIFI_NPD     138
+#define IGEP3_GPIO_WIFI_NRESET  139
+#define IGEP3_GPIO_BT_NRESET    137
+
+#define IGEP3_GPIO_USBH_NRESET  115
+
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+
+#define ONENAND_MAP             0x20000000
+
+/*
+ * x2 Flash built-in COMBO POP MEMORY
+ * Since the device is equipped with two DataRAMs, and two-plane NAND
+ * Flash memory array, these two component enables simultaneous program
+ * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
+ * while Plane2 has only odd blocks such as block1, block3, block5.
+ * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
+ */
+
+static struct mtd_partition igep3_onenand_partitions[] = {
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 2 * (64*(2*2048))
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 6 * (64*(2*2048)),
+        },
+        {
+                .name           = "Environment",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 2 * (64*(2*2048)),
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 12 * (64*(2*2048)),
+        },
+        {
+                .name           = "File System",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_onenand_platform_data igep3_onenand_pdata = {
+        .parts = igep3_onenand_partitions,
+        .nr_parts = ARRAY_SIZE(igep3_onenand_partitions),
+        .onenand_setup = NULL,
+        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
+};
+
+static struct platform_device igep3_onenand_device = {
+        .name           = "omap2-onenand",
+        .id             = -1,
+        .dev = {
+                .platform_data = &igep3_onenand_pdata,
+        },
+};
+
+void __init igep3_flash_init(void)
+{
+        u8 cs = 0;
+        u8 onenandcs = GPMC_CS_NUM + 1;
+
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                u32 ret;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                /* Check if NAND/oneNAND is configured */
+                if ((ret & 0xC00) == 0x800)
+                        /* NAND found */
+                        pr_err("IGEP3: Unsupported NAND found\n");
+                else {
+                        ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+
+                        if ((ret & 0x3F) == (ONENAND_MAP >> 24))
+                                /* OneNAND found */
+                                onenandcs = cs;
+                }
+        }
+
+        if (onenandcs > GPMC_CS_NUM) {
+                pr_err("IGEP3: Unable to find configuration in GPMC\n");
+                return;
+        }
+
+        igep3_onenand_pdata.cs = onenandcs;
+
+        if (platform_device_register(&igep3_onenand_device) < 0)
+                pr_err("IGEP3: Unable to register OneNAND device\n");
+}
+
+#else
+void __init igep3_flash_init(void) {}
+#endif
+
+static struct regulator_consumer_supply igep3_vmmc1_supply = {
+        .supply         = "vmmc",
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data igep3_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &igep3_vmmc1_supply,
+};
+
+static struct omap2_hsmmc_info mmc[] = {
+        [0] = {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+        [1] = {
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+#endif
+        {}      /* Terminator */
+};
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#include <linux/leds.h>
+
+static struct gpio_led igep3_gpio_leds[] = {
+        [0] = {
+                .name                   = "gpio-led:red:d0",
+                .gpio                   = IGEP3_GPIO_LED0_RED,
+                .default_trigger        = "default-off"
+        },
+        [1] = {
+                .name                   = "gpio-led:green:d0",
+                .gpio                   = IGEP3_GPIO_LED0_GREEN,
+                .default_trigger        = "default-off",
+        },
+        [2] = {
+                .name                   = "gpio-led:red:d1",
+                .gpio                   = IGEP3_GPIO_LED1_RED,
+                .default_trigger        = "default-off",
+        },
+        [3] = {
+                .name                   = "gpio-led:green:d1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = -EINVAL, /* gets replaced */
+        },
+};
+
+static struct gpio_led_platform_data igep3_led_pdata = {
+        .leds           = igep3_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep3_gpio_leds),
+};
+
+static struct platform_device igep3_led_device = {
+         .name   = "leds-gpio",
+         .id     = -1,
+         .dev    = {
+                 .platform_data = &igep3_led_pdata,
+        },
+};
+
+static void __init igep3_leds_init(void)
+{
+        platform_device_register(&igep3_led_device);
+}
+
+#else
+static inline void igep3_leds_init(void)
+{
+        if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED0_RED, 0);
+                gpio_set_value(IGEP3_GPIO_LED0_RED, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n");
+
+        if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED0_GREEN, 0);
+                gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n");
+
+        if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
+                (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_LED1_RED, 0);
+                gpio_set_value(IGEP3_GPIO_LED1_RED, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n");
+}
+#endif
+
+static int igep3_twl4030_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+        mmc[0].gpio_cd = gpio + 0;
+        omap2_hsmmc_init(mmc);
+
+        /*
+         * link regulators to MMC adapters ... we "know" the
+         * regulators will be set up only *after* we return.
+         */
+        igep3_vmmc1_supply.dev = mmc[0].dev;
+
+        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
+#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
+        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
+            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
+                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n");
+#else
+        igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+#endif
+
+        return 0;
+};
+
+static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .setup          = igep3_twl4030_gpio_setup,
+};
+
+static struct twl4030_usb_data igep3_twl4030_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static void __init igep3_init_irq(void)
+{
+        omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+static struct twl4030_platform_data igep3_twl4030_pdata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .usb            = &igep3_twl4030_usb_data,
+        .gpio           = &igep3_twl4030_gpio_pdata,
+        .vmmc1          = &igep3_vmmc1,
+};
+
+static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags          = I2C_CLIENT_WAKE,
+                .irq            = INT_34XX_SYS_NIRQ,
+                .platform_data  = &igep3_twl4030_pdata,
+        },
+};
+
+static int __init igep3_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo,
+                        ARRAY_SIZE(igep3_i2c_boardinfo));
+
+        return 0;
+}
+
+static struct omap_musb_board_data musb_board_data = {
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_OTG,
+        .power          = 100,
+};
+
+#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+
+static void __init igep3_wifi_bt_init(void)
+{
+        /* Configure MUX values for W-LAN + Bluetooth GPIO's */
+        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT);
+
+        /* Set GPIO's for  W-LAN + Bluetooth combo module */
+        if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_WIFI_NPD, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n");
+
+        if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_WIFI_NRESET, 0);
+                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0);
+                udelay(10);
+                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n");
+
+        if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) &&
+            (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) {
+                gpio_export(IGEP3_GPIO_BT_NRESET, 0);
+        } else
+                pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n");
+}
+#else
+void __init igep3_wifi_bt_init(void) {}
+#endif
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init igep3_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        /* Register I2C busses and drivers */
+        igep3_i2c_init();
+
+        omap_serial_init();
+        usb_musb_init(&musb_board_data);
+
+        igep3_flash_init();
+        igep3_leds_init();
+
+        /*
+         * WLAN-BT combo module from MuRata wich has a Marvell WLAN
+         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
+         */
+        igep3_wifi_bt_init();
+
+}
+
+MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = igep3_init_irq,
+        .init_machine   = igep3_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f28fd77bceb3..001fd9713f39 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -27,6 +27,7 @@
 #include <linux/i2c/twl.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -41,11 +42,12 @@
 #include <mach/board-zoom.h>
 
 #include <asm/delay.h>
-#include <plat/control.h>
 #include <plat/usb.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "control.h"
 
 #define LDP_SMSC911X_CS         1
 #define LDP_SMSC911X_GPIO       152
@@ -82,7 +84,7 @@ static struct platform_device ldp_smsc911x_device = {
         },
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
         KEY(2, 0, KEY_3),
@@ -362,7 +364,7 @@ static int __init omap_i2c_init(void)
 static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 3f7966873507..e823c7042ab3 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,6 +20,7 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/musb.h>
+#include <sound/tlv320aic3x.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -383,15 +384,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
         omap_mmc_notify_cover_event(mmc_device, index, *openp);
 }
 
-void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state)
-{
-        if (mmc_device == NULL)
-                return;
-
-        slot1_cover_open = !closed_state;
-        omap_mmc_notify_cover_event(mmc_device, 0, closed_state);
-}
-
 static int n8x0_mmc_late_init(struct device *dev)
 {
         int r, bit, *openp;
@@ -511,7 +503,7 @@ static struct omap_mmc_platform_data mmc1_data = {
 
 static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
 
-void __init n8x0_mmc_init(void)
+static void __init n8x0_mmc_init(void)
 
 {
         int err;
@@ -560,11 +552,6 @@ void __init n8x0_mmc_init(void)
 void __init n8x0_mmc_init(void)
 {
 }
-
-void n8x0_mmc_slot1_cover_handler(void *arg, int state)
-{
-}
-
 #endif  /* CONFIG_MMC_OMAP */
 
 #ifdef CONFIG_MENELAUS
@@ -614,29 +601,35 @@ static int n8x0_menelaus_late_init(struct device *dev)
         return 0;
 }
 
-static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = {
+#else
+static int n8x0_menelaus_late_init(struct device *dev)
+{
+        return 0;
+}
+#endif
+
+static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
+        .late_init = n8x0_menelaus_late_init,
+};
+
+static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
         {
                 I2C_BOARD_INFO("menelaus", 0x72),
                 .irq = INT_24XX_SYS_NIRQ,
+                .platform_data = &n8x0_menelaus_platform_data,
         },
 };
 
-static struct menelaus_platform_data n8x0_menelaus_platform_data = {
-        .late_init = n8x0_menelaus_late_init,
+static struct aic3x_pdata n810_aic33_data __initdata = {
+        .gpio_reset = 118,
 };
 
-static void __init n8x0_menelaus_init(void)
-{
-        n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data;
-        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
-                              ARRAY_SIZE(n8x0_i2c_board_info_1));
-}
-
-#else
-static inline void __init n8x0_menelaus_init(void)
-{
-}
-#endif
+static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x18),
+                .platform_data = &n810_aic33_data,
+        },
+};
 
 static void __init n8x0_map_io(void)
 {
@@ -653,6 +646,11 @@ static void __init n8x0_init_irq(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* I2S codec port pins for McBSP block */
+        OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -665,9 +663,14 @@ static void __init n8x0_init_machine(void)
         /* FIXME: add n810 spi devices */
         spi_register_board_info(n800_spi_board_info,
                                 ARRAY_SIZE(n800_spi_board_info));
+        omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
+                              ARRAY_SIZE(n8x0_i2c_board_info_1));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        if (machine_is_nokia_n810())
+                i2c_register_board_info(2, n810_i2c_board_info_2,
+                                        ARRAY_SIZE(n810_i2c_board_info_2));
 
         omap_serial_init();
-        n8x0_menelaus_init();
         n8x0_onenand_init();
         n8x0_mmc_init();
         n8x0_usb_init();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 9d9f5b881ee8..14f42240ae79 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -43,13 +44,100 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
+/*
+ * OMAP3 Beagle revision
+ * Run time detection of Beagle revision is done by reading GPIO.
+ * GPIO ID -
+ *      AXBX    = GPIO173, GPIO172, GPIO171: 1 1 1
+ *      C1_3    = GPIO173, GPIO172, GPIO171: 1 1 0
+ *      C4      = GPIO173, GPIO172, GPIO171: 1 0 1
+ *      XM      = GPIO173, GPIO172, GPIO171: 0 0 0
+ */
+enum {
+        OMAP3BEAGLE_BOARD_UNKN = 0,
+        OMAP3BEAGLE_BOARD_AXBX,
+        OMAP3BEAGLE_BOARD_C1_3,
+        OMAP3BEAGLE_BOARD_C4,
+        OMAP3BEAGLE_BOARD_XM,
+};
+
+static u8 omap3_beagle_version;
+
+static u8 omap3_beagle_get_rev(void)
+{
+        return omap3_beagle_version;
+}
+
+static void __init omap3_beagle_init_rev(void)
+{
+        int ret;
+        u16 beagle_rev = 0;
+
+        omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
+
+        ret = gpio_request(171, "rev_id_0");
+        if (ret < 0)
+                goto fail0;
+
+        ret = gpio_request(172, "rev_id_1");
+        if (ret < 0)
+                goto fail1;
+
+        ret = gpio_request(173, "rev_id_2");
+        if (ret < 0)
+                goto fail2;
+
+        gpio_direction_input(171);
+        gpio_direction_input(172);
+        gpio_direction_input(173);
+
+        beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
+                        | (gpio_get_value(173) << 2);
+
+        switch (beagle_rev) {
+        case 7:
+                printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
+                break;
+        case 6:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
+                break;
+        case 5:
+                printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
+                break;
+        case 0:
+                printk(KERN_INFO "OMAP3 Beagle Rev: xM\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
+                break;
+        default:
+                printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+        }
+
+        return;
+
+fail2:
+        gpio_free(172);
+fail1:
+        gpio_free(171);
+fail0:
+        printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
+        omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+
+        return;
+}
+
 static struct mtd_partition omap3beagle_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
         {
@@ -166,7 +254,7 @@ static void __init beagle_display_init(void)
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
@@ -185,7 +273,10 @@ static struct gpio_led gpio_leds[];
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+                mmc[0].gpio_wp = -EINVAL;
+        } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) ||
+                (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) {
                 omap_mux_init_gpio(23, OMAP_PIN_INPUT);
                 mmc[0].gpio_wp = 23;
         } else {
@@ -322,13 +413,19 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
         },
 };
 
+static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
+       {
+               I2C_BOARD_INFO("eeprom", 0x50),
+       },
+};
+
 static int __init omap3_beagle_i2c_init(void)
 {
         omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
                         ARRAY_SIZE(beagle_i2c_boardinfo));
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
-        omap_register_i2c_bus(3, 100, NULL, 0);
+        omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
         return 0;
 }
 
@@ -464,6 +561,7 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3_beagle_init_rev();
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 8936e4fba334..b04365c6bb10 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -31,6 +31,7 @@
 #include <linux/smsc911x.h>
 
 #include <linux/regulator/machine.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -370,7 +371,7 @@ static struct regulator_init_data omap3evm_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
         },
@@ -446,7 +447,7 @@ static struct twl4030_usb_data omap3evm_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -584,7 +585,7 @@ static int ads7846_get_pendown_state(void)
         return !gpio_get_value(OMAP3_EVM_TS_GPIO);
 }
 
-struct ads7846_platform_data ads7846_config = {
+static struct ads7846_platform_data ads7846_config = {
         .x_max                  = 0x0fff,
         .y_max                  = 0x0fff,
         .x_plate_ohms           = 180,
@@ -603,7 +604,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .single_channel = 1,    /* 0: slave, 1: master */
 };
 
-struct spi_board_info omap3evm_spi_board_info[] = {
+static struct spi_board_info omap3evm_spi_board_info[] = {
         [0] = {
                 .modalias               = "ads7846",
                 .bus_num                = 1,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
new file mode 100644
index 000000000000..5f7d2c1e7ef5
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -0,0 +1,241 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3logic.c
+ *
+ * Copyright (C) 2010 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Copyright (C) 2010 Logic Product Development, Inc.
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Modified from Beagle, EVM, and RX51
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <linux/regulator/machine.h>
+
+#include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "timer-gp.h"
+#include "control.h"
+
+#include <plat/mux.h>
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc-smsc911x.h>
+#include <plat/gpmc.h>
+#include <plat/sdrc.h>
+
+#define OMAP3LOGIC_SMSC911X_CS                  1
+
+#define OMAP3530_LV_SOM_MMC_GPIO_CD             110
+#define OMAP3530_LV_SOM_MMC_GPIO_WP             126
+#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ       152
+
+#define OMAP3_TORPEDO_MMC_GPIO_CD               127
+#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ         129
+
+static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data omap3logic_vmmc1 = {
+        .constraints = {
+                .name                   = "VMMC1",
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &omap3logic_vmmc1_supply,
+};
+
+static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .pullups        = BIT(1),
+        .pulldowns      = BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
+                        | BIT(13) | BIT(15) | BIT(16) | BIT(17),
+};
+
+static struct twl4030_platform_data omap3logic_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .gpio           = &omap3logic_gpio_data,
+        .vmmc1          = &omap3logic_vmmc1,
+};
+
+static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &omap3logic_twldata,
+        },
+};
+
+static int __init omap3logic_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo,
+                                ARRAY_SIZE(omap3logic_i2c_boardinfo));
+        return 0;
+}
+
+static struct omap2_hsmmc_info __initdata board_mmc_info[] = {
+        {
+                .name           = "external",
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        {}      /* Terminator */
+};
+
+static void __init board_mmc_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD;
+                board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP;
+                omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD;
+                omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        omap2_hsmmc_init(board_mmc_info);
+        /* link regulators to MMC adapters */
+        omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
+}
+
+static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
+        .cs             = OMAP3LOGIC_SMSC911X_CS,
+        .gpio_irq       = -EINVAL,
+        .gpio_reset     = -EINVAL,
+        .flags          = IORESOURCE_IRQ_LOWLEVEL,
+};
+
+/* TODO/FIXME (comment by Peter Barada, LogicPD):
+ * Fix the PBIAS voltage for Torpedo MMC1 pins that
+ * are used for other needs (IRQs, etc).            */
+static void omap3torpedo_fix_pbias_voltage(void)
+{
+        u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+        u32 reg;
+
+        if (machine_is_omap3_torpedo())
+        {
+                /* Set the bias for the pin */
+                reg = omap_ctrl_readl(control_pbias_offset);
+
+                reg &= ~OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg, control_pbias_offset);
+
+                /* 100ms delay required for PBIAS configuration */
+                msleep(100);
+
+                reg |= OMAP343X_PBIASLITEVMODE1;
+                reg |= OMAP343X_PBIASLITEPWRDNZ1;
+                omap_ctrl_writel(reg | 0x300, control_pbias_offset);
+        }
+}
+
+static inline void __init board_smsc911x_init(void)
+{
+        if (machine_is_omap3530_lv_som()) {
+                /* OMAP3530 LV SOM board */
+                board_smsc911x_data.gpio_irq =
+                                        OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT);
+        } else if (machine_is_omap3_torpedo()) {
+                /* OMAP3 Torpedo board */
+                board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ;
+                omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT);
+        } else {
+                /* unsupported board */
+                printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+                return;
+        }
+
+        gpmc_smsc911x_init(&board_smsc911x_data);
+}
+
+static void __init omap3logic_init_irq(void)
+{
+        omap2_init_common_hw(NULL, NULL);
+        omap_init_irq();
+        omap_gpio_init();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init omap3logic_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap3torpedo_fix_pbias_voltage();
+        omap3logic_i2c_init();
+        omap_serial_init();
+        board_mmc_init();
+        board_smsc911x_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = omap3logic_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .init_irq       = omap3logic_init_irq,
+        .init_machine   = omap3logic_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 41d6f549070c..89ed1be2d62e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -32,7 +32,9 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/gpio_keys.h>
+#include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <linux/regulator/fixed.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -276,14 +278,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card)
 static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 126,
                 .ext_clock      = 0,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
@@ -291,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         },
         {
                 .mmc            = 3,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .init_card      = pandora_wl1251_init_card,
@@ -344,6 +346,9 @@ static struct regulator_consumer_supply pandora_vmmc1_supply =
 static struct regulator_consumer_supply pandora_vmmc2_supply =
         REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
 
+static struct regulator_consumer_supply pandora_vmmc3_supply =
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
+
 static struct regulator_consumer_supply pandora_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -488,6 +493,33 @@ static struct regulator_init_data pandora_vsim = {
         .consumer_supplies      = &pandora_adac_supply,
 };
 
+/* Fixed regulator internal to Wifi module */
+static struct regulator_init_data pandora_vmmc3 = {
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &pandora_vmmc3_supply,
+};
+
+static struct fixed_voltage_config pandora_vwlan = {
+        .supply_name            = "vwlan",
+        .microvolts             = 1800000, /* 1.8V */
+        .gpio                   = PANDORA_WIFI_NRESET_GPIO,
+        .startup_delay          = 50000, /* 50ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &pandora_vmmc3,
+};
+
+static struct platform_device pandora_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &pandora_vwlan,
+        },
+};
+
 static struct twl4030_usb_data omap3pandora_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
@@ -501,6 +533,8 @@ static struct twl4030_codec_data omap3pandora_codec_data = {
         .audio = &omap3pandora_audio_data,
 };
 
+static struct twl4030_bci_platform_data pandora_bci_data;
+
 static struct twl4030_platform_data omap3pandora_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -516,6 +550,7 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .vaux4          = &pandora_vaux4,
         .vsim           = &pandora_vsim,
         .keypad         = &pandora_kp_data,
+        .bci            = &pandora_bci_data,
 };
 
 static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
@@ -644,19 +679,8 @@ static void pandora_wl1251_init(void)
         if (pandora_wl1251_pdata.irq < 0)
                 goto fail_irq;
 
-        ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset");
-        if (ret < 0)
-                goto fail_irq;
-
-        /* start powered so that it probes with MMC subsystem */
-        ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1);
-        if (ret < 0)
-                goto fail_nreset;
-
         return;
 
-fail_nreset:
-        gpio_free(PANDORA_WIFI_NRESET_GPIO);
 fail_irq:
         gpio_free(PANDORA_WIFI_IRQ_GPIO);
 fail:
@@ -668,6 +692,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_keys_gpio,
         &pandora_dss_device,
         &pandora_wl1251_data,
+        &pandora_vwlan_device,
 };
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bc5ac83bd4cf..f25272125413 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -26,6 +26,7 @@
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
+#include <linux/mmc/host.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -38,7 +39,6 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 #include <plat/display.h>
 
 #include <plat/mcspi.h>
@@ -52,6 +52,7 @@
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #define OMAP3STALKER_ETHR_START 0x2c000000
@@ -275,7 +276,7 @@ static struct regulator_init_data omap3stalker_vsim = {
 static struct omap2_hsmmc_info mmc[] = {
         {
          .mmc           = 1,
-         .wires         = 4,
+         .caps          = MMC_CAP_4_BIT_DATA,
          .gpio_cd       = -EINVAL,
          .gpio_wp       = 23,
          },
@@ -389,7 +390,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_DOWN),
         KEY(0, 2, KEY_ENTER),
@@ -564,7 +565,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .single_channel         = 1,    /* 0: slave, 1: master */
 };
 
-struct spi_board_info omap3stalker_spi_board_info[] = {
+static struct spi_board_info omap3stalker_spi_board_info[] = {
         [0] = {
                .modalias        = "ads7846",
                .bus_num         = 1,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 0e99ce584dbf..41104bb8774c 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
+#include <linux/mmc/host.h>
 
 #include <plat/mcspi.h>
 #include <linux/spi/spi.h>
@@ -47,10 +48,10 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/timer-gp.h>
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "timer-gp.h"
 
 #include <asm/setup.h>
 
@@ -61,7 +62,7 @@
 #define TB_BL_PWM_TIMER         9
 #define TB_KILL_POWER_GPIO      168
 
-unsigned long touchbook_revision;
+static unsigned long touchbook_revision;
 
 static struct mtd_partition omap3touchbook_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -108,7 +109,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
         },
         {}      /* Terminator */
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index db69bcadf4c7..702f2a63f2c1 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
@@ -33,12 +34,45 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/control.h>
-#include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include "timer-gp.h"
+
 #include "hsmmc.h"
+#include "control.h"
+
+#define GPIO_HUB_POWER          1
+#define GPIO_HUB_NRESET         62
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "pandaboard::status1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 7,
+        },
+        {
+                .name                   = "pandaboard::status2",
+                .default_trigger        = "mmc0",
+                .gpio                   = 8,
+        },
+};
 
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct platform_device *panda_devices[] __initdata = {
+        &leds_gpio,
+};
 
 static void __init omap4_panda_init_irq(void)
 {
@@ -47,6 +81,56 @@ static void __init omap4_panda_init_irq(void)
         omap_gpio_init();
 }
 
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .phy_reset  = false,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void __init omap4_ehci_init(void)
+{
+        int ret;
+
+
+        /* disable the power to the usb hub prior to init */
+        ret = gpio_request(GPIO_HUB_POWER, "hub_power");
+        if (ret) {
+                pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER);
+                goto error1;
+        }
+        gpio_export(GPIO_HUB_POWER, 0);
+        gpio_direction_output(GPIO_HUB_POWER, 0);
+        gpio_set_value(GPIO_HUB_POWER, 0);
+
+        /* reset phy+hub */
+        ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset");
+        if (ret) {
+                pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET);
+                goto error2;
+        }
+        gpio_export(GPIO_HUB_NRESET, 0);
+        gpio_direction_output(GPIO_HUB_NRESET, 0);
+        gpio_set_value(GPIO_HUB_NRESET, 0);
+        gpio_set_value(GPIO_HUB_NRESET, 1);
+
+        usb_ehci_init(&ehci_pdata);
+
+        /* enable power to hub */
+        gpio_set_value(GPIO_HUB_POWER, 1);
+        return;
+
+error2:
+        gpio_free(GPIO_HUB_POWER);
+error1:
+        pr_err("Unable to initialize EHCI power/reset\n");
+        return;
+
+}
+
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
         .mode                   = MUSB_PERIPHERAL,
@@ -56,7 +140,7 @@ static struct omap_musb_board_data musb_board_data = {
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
         },
         {}      /* Terminator */
@@ -67,10 +151,6 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
                 .supply = "vmmc",
                 .dev_name = "mmci-omap-hs.0",
         },
-        {
-                .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.1",
-        },
 };
 
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@@ -89,7 +169,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 
 static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
 {
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        struct omap_mmc_platform_data *pdata;
+
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
+                return;
+        }
+        pdata = dev->platform_data;
 
         pdata->init =   omap4_twl6030_hsmmc_late_init;
 }
@@ -156,7 +243,7 @@ static struct regulator_init_data omap4_panda_vmmc = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 2,
+        .num_consumer_supplies  = 1,
         .consumer_supplies      = omap4_panda_vmmc_supply,
 };
 
@@ -274,13 +361,13 @@ static int __init omap4_panda_i2c_init(void)
 }
 static void __init omap4_panda_init(void)
 {
-        int status;
-
         omap4_panda_i2c_init();
+        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
         /* OMAP4 Panda uses internal transceiver so register nop transceiver */
         usb_nop_xceiv_register();
+        omap4_ehci_init();
         /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
         if (!cpu_is_omap44xx())
                 usb_musb_init(&musb_board_data);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 5e528ca015a1..7053bc0b46db 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -32,6 +32,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -303,13 +304,13 @@ static void __init overo_flash_init(void)
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
         },
         {
                 .mmc            = 2,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .transceiver    = true,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 63d786bccb67..41285297eafc 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -33,6 +33,8 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include <mach/board-rx51.h>
+
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
 
@@ -185,7 +187,7 @@ static void __init rx51_add_gpio_keys(void)
 }
 #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
 
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         /*
          * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
          * connected to the ground" matrix state.
@@ -303,7 +305,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .cover_only     = true,
                 .gpio_cd        = 160,
                 .gpio_wp        = -EINVAL,
@@ -312,7 +314,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8, /* See also rx51_mmc2_remux */
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                                                /* See also rx51_mmc2_remux */
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c
index f392844195d2..a43b2c5c838b 100644
--- a/arch/arm/mach-omap2/board-rx51-sdram.c
+++ b/arch/arm/mach-omap2/board-rx51-sdram.c
@@ -43,7 +43,7 @@ struct sdram_timings {
         u32 tWTR;
 };
 
-struct omap_sdrc_params rx51_sdrc_params[4];
+static struct omap_sdrc_params rx51_sdrc_params[4];
 
 static const struct sdram_timings rx51_timings[] = {
         {
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 5a1005ba9815..85503fed4e13 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -20,6 +20,8 @@
 #include <plat/vram.h>
 #include <plat/mcspi.h>
 
+#include <mach/board-rx51.h>
+
 #include "mux.h"
 
 #define RX51_LCD_RESET_GPIO     90
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 1d7f827b0408..007ebdc6c993 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -16,6 +16,8 @@
 
 #include <plat/gpmc.h>
 
+#include <mach/board-zoom.h>
+
 #define ZOOM_SMSC911X_CS        7
 #define ZOOM_SMSC911X_GPIO      158
 #define ZOOM_QUADUART_CS        3
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index bc8232845d7a..86c9b2102952 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -18,6 +18,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -35,7 +36,7 @@
 #define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
 
 /* Zoom2 has Qwerty keyboard*/
-static int board_keymap[] = {
+static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_E),
         KEY(0, 1, KEY_R),
         KEY(0, 2, KEY_T),
@@ -199,14 +200,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "external",
                 .mmc            = 1,
-                .wires          = 4,
+                .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .power_saving   = true,
         },
         {
                 .name           = "internal",
                 .mmc            = 2,
-                .wires          = 8,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .nonremovable   = true,
@@ -348,4 +349,5 @@ void __init zoom_peripherals_init(void)
         platform_device_register(&omap_vwlan_device);
         usb_musb_init(&musb_board_data);
         enable_board_wakeup_source();
+        omap_serial_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 4ccbc32386a0..2992a9f3a585 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -24,6 +24,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index b2bb3ff971ac..5adde12c0395 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -22,6 +22,7 @@
 #include <plat/board.h>
 #include <plat/usb.h>
 
+#include "board-flash.h"
 #include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 605f531783a8..b5babf5440e4 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -395,7 +395,7 @@ void omap2_clk_disable_unused(struct clk *clk)
         if ((regval32 & (1 << clk->enable_bit)) == v)
                 return;
 
-        printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
+        pr_debug("Disabling unused clock \"%s\"\n", clk->name);
         if (cpu_is_omap34xx()) {
                 omap2_clk_enable(clk);
                 omap2_clk_disable(clk);
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 5f2066a6ba74..21f856252ad8 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -27,6 +27,7 @@
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
 
@@ -89,6 +90,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -1135,14 +1142,34 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
@@ -1159,10 +1186,14 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
@@ -1721,6 +1752,9 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
@@ -1728,6 +1762,8 @@ static struct omap_clk omap2420_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 701a1716019e..e32afcbdfb88 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -27,6 +27,7 @@
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
 
@@ -89,6 +90,12 @@ static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
         .clkdm_name     = "wkup_clkdm",
 };
 
+/* Optional external clock input for McBSP CLKS */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
 /*
  * Analog domain root source clocks
  */
@@ -1123,14 +1130,34 @@ static struct clk mcbsp1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_fck_clksel[] = {
+        { .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
 static struct clk mcbsp1_fck = {
         .name           = "mcbsp1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp2_ick = {
@@ -1147,10 +1174,14 @@ static struct clk mcbsp2_fck = {
         .name           = "mcbsp2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp3_ick = {
@@ -1167,10 +1198,14 @@ static struct clk mcbsp3_fck = {
         .name           = "mcbsp3_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP3_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp4_ick = {
@@ -1187,10 +1222,14 @@ static struct clk mcbsp4_fck = {
         .name           = "mcbsp4_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP4_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcbsp5_ick = {
@@ -1207,10 +1246,14 @@ static struct clk mcbsp5_fck = {
         .name           = "mcbsp5_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .init           = &omap2_init_clksel_parent,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MCBSP5_SHIFT,
-        .recalc         = &followparent_recalc,
+        .clksel_reg     = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk mcspi1_ick = {
@@ -1808,6 +1851,12 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
@@ -1815,6 +1864,11 @@ static struct omap_clk omap2430_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index c73906d17458..d85ecd5aebfd 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -20,7 +20,6 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
@@ -33,6 +32,7 @@
 #include "cm-regbits-34xx.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
 
 /*
  * clocks
@@ -2465,6 +2465,16 @@ static struct clk uart3_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_fck = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt2_fck = {
         .name           = "gpt2_fck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -2715,6 +2725,16 @@ static struct clk uart3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk uart4_ick = {
+        .name           = "uart4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3630_EN_UART4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -3188,6 +3208,11 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
+        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
+        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
@@ -3253,6 +3278,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
+        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
@@ -3346,9 +3373,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
+        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
+        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3372,6 +3403,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
+        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb2..1599836ba3d9 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,13 +17,15 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
  */
 
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
-
-#include <plat/control.h>
 #include <plat/clkdev_omap.h>
 
 #include "clock.h"
@@ -32,6 +34,7 @@
 #include "cm-regbits-44xx.h"
 #include "prm.h"
 #include "prm-regbits-44xx.h"
+#include "control.h"
 
 /* Root clocks */
 
@@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+static struct clk tie_low_clock_ck = {
+        .name           = "tie_low_clock_ck",
+        .rate           = 0,
+        .ops            = &clkops_null,
+};
+
 static struct clk utmi_phy_clkout_ck = {
         .name           = "utmi_phy_clkout_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp1_ck = {
         .name           = "xclk60mhsp1_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
 static struct clk xclk60mhsp2_ck = {
         .name           = "xclk60mhsp2_ck",
-        .rate           = 12000000,
+        .rate           = 60000000,
         .ops            = &clkops_null,
 };
 
@@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = {
 
 /* Module clocks and DPLL outputs */
 
-static const struct clksel_rate div2_1to2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel dpll_sys_ref_clk_div[] = {
-        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_sys_ref_clk = {
-        .name           = "dpll_sys_ref_clk",
+static struct clk abe_dpll_bypass_clk_mux_ck = {
+        .name           = "abe_dpll_bypass_clk_mux_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
-        .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
-        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel abe_dpll_refclk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk abe_dpll_refclk_mux_ck = {
         .name           = "abe_dpll_refclk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
-        .clksel         = abe_dpll_refclk_mux_sel,
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
 /* DPLL_ABE */
 static struct dpll_data dpll_abe_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &sys_clkin_ck,
+        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
         .clk_ref        = &abe_dpll_refclk_mux_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -310,6 +303,12 @@ static struct clk abe_clk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
 static const struct clksel aess_fclk_div[] = {
         { .parent = &abe_clk, .rates = div2_1to2_rates },
         { .parent = NULL },
@@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = {
 };
 
 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk core_hsd_byp_clk_mux_ck = {
         .name           = "core_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = core_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_core_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = {
 
 static struct clk dpll_core_ck = {
         .name           = "dpll_core_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_core_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_null,
@@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = {
 };
 
 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk iva_hsd_byp_clk_mux_ck = {
         .name           = "iva_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .ops            = &clkops_null,
         .recalc         = &followparent_recalc,
 };
@@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_iva_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = {
 
 static struct clk dpll_iva_ck = {
         .name           = "dpll_iva_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_iva_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = {
 static struct dpll_data dpll_mpu_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
         .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = {
 
 static struct clk dpll_mpu_ck = {
         .name           = "dpll_mpu_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_mpu_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = {
 };
 
 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
-        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 static struct clk per_hsd_byp_clk_mux_ck = {
         .name           = "per_hsd_byp_clk_mux_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .clksel         = per_hsd_byp_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
 static struct dpll_data dpll_per_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = {
 
 static struct clk dpll_per_ck = {
         .name           = "dpll_per_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_per_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = {
 /* DPLL_UNIPRO */
 static struct dpll_data dpll_unipro_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
-        .clk_bypass     = &dpll_sys_ref_clk,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = {
 
 static struct clk dpll_unipro_ck = {
         .name           = "dpll_unipro_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_unipro_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = {
 static struct dpll_data dpll_usb_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
         .clk_bypass     = &usb_hs_clk_div_ck,
-        .clk_ref        = &dpll_sys_ref_clk,
+        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
+        .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = {
         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
         .max_divider    = OMAP4430_MAX_DPLL_DIV,
         .min_divider    = 1,
-        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL
 };
 
 
 static struct clk dpll_usb_ck = {
         .name           = "dpll_usb_ck",
-        .parent         = &dpll_sys_ref_clk,
+        .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_usb_dd,
         .init           = &omap2_init_dpll_parent,
         .ops            = &clkops_omap3_noncore_dpll_ops,
@@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = {
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
         { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
+        { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
 
@@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel syc_clk_div_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
 static struct clk syc_clk_div_ck = {
         .name           = "syc_clk_div_ck",
         .parent         = &sys_clkin_ck,
-        .clksel         = dpll_sys_ref_clk_div,
+        .clksel         = syc_clk_div_div,
         .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
         .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
         .ops            = &clkops_null,
@@ -1284,13 +1288,13 @@ static struct clk aess_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk cust_efuse_fck = {
-        .name           = "cust_efuse_fck",
+static struct clk bandgap_fclk = {
+        .name           = "bandgap_fclk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_cefuse_clkdm",
-        .parent         = &sys_clkin_ck,
+        .enable_reg     = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1344,6 +1348,56 @@ static struct clk dmic_fck = {
         .clkdm_name     = "abe_clkdm",
 };
 
+static struct clk dsp_fck = {
+        .name           = "dsp_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_sys_clk = {
+        .name           = "dss_sys_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &syc_clk_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_tv_clk = {
+        .name           = "dss_tv_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &extalt_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_dss_clk = {
+        .name           = "dss_dss_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &dpll_per_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_48mhz_clk = {
+        .name           = "dss_48mhz_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_fck = {
         .name           = "dss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1354,18 +1408,18 @@ static struct clk dss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ducati_ick = {
-        .name           = "ducati_ick",
+static struct clk efuse_ctrl_cust_fck = {
+        .name           = "efuse_ctrl_cust_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "ducati_clkdm",
-        .parent         = &ducati_clk_mux_ck,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif1_ick = {
-        .name           = "emif1_ick",
+static struct clk emif1_fck = {
+        .name           = "emif1_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1429,8 @@ static struct clk emif1_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk emif2_ick = {
-        .name           = "emif2_ick",
+static struct clk emif2_fck = {
+        .name           = "emif2_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1407,42 +1461,24 @@ static struct clk fdif_fck = {
         .clkdm_name     = "iss_clkdm",
 };
 
-static const struct clksel per_sgx_fclk_div[] = {
-        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-
-static struct clk per_sgx_fclk = {
-        .name           = "per_sgx_fclk",
-        .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
-};
-
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
-        { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
+static struct clk fpka_fck = {
+        .name           = "fpka_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
-/* Merged sgx_clk_mux into gfx */
-static struct clk gfx_fck = {
-        .name           = "gfx_fck",
-        .parent         = &dpll_core_m7_ck,
-        .clksel         = sgx_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+static struct clk gpio1_dbclk = {
+        .name           = "gpio1_dbclk",
         .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l3_gfx_clkdm",
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk gpio1_ick = {
@@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio2_dbclk = {
+        .name           = "gpio2_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio3_dbclk = {
+        .name           = "gpio3_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio4_dbclk = {
+        .name           = "gpio4_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio5_dbclk = {
+        .name           = "gpio5_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk gpio6_dbclk = {
+        .name           = "gpio6_dbclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
         .ops            = &clkops_omap2_dflt,
@@ -1515,214 +1601,25 @@ static struct clk gpmc_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static const struct clksel dmt1_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-/*
- * Merged dmt1_clk_mux into gptimer1
- * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
- */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-};
-
-/*
- * Merged cm2_dm10_mux into gptimer10
- * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
- */
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm11_mux into gptimer11
- * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
- */
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm2_mux into gptimer2
- * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
- */
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm3_mux into gptimer3
- * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
- */
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-/*
- * Merged cm2_dm4_mux into gptimer4
- * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
- */
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
-};
-
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-/*
- * Merged timer5_sync_mux into gptimer5
- * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
- */
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer6_sync_mux into gptimer6
- * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
- */
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer7_sync_mux into gptimer7
- * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
- */
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged timer8_sync_mux into gptimer8
- * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
- */
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .parent         = &syc_clk_div_ck,
-        .clksel         = timer5_sync_mux_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
-        .ops            = &clkops_omap2_dflt,
-        .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-};
-
-/*
- * Merged cm2_dm9_mux into gptimer9
- * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
- */
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .parent         = &sys_clkin_ck,
-        .clksel         = dmt1_clk_mux_sel,
+/* Merged sgx_clk_mux into gpu */
+static struct clk gpu_fck = {
+        .name           = "gpu_fck",
+        .parent         = &dpll_core_m7_ck,
+        .clksel         = sgx_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
         .ops            = &clkops_omap2_dflt,
         .recalc         = &omap2_clksel_recalc,
-        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_per_clkdm",
+        .clkdm_name     = "l3_gfx_clkdm",
 };
 
 static struct clk hdq1w_fck = {
@@ -1735,11 +1632,16 @@ static struct clk hdq1w_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel hsi_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
 /* Merged hsi_fclk into hsi */
-static struct clk hsi_ick = {
-        .name           = "hsi_ick",
+static struct clk hsi_fck = {
+        .name           = "hsi_fck",
         .parent         = &dpll_per_m2x2_ck,
-        .clksel         = per_sgx_fclk_div,
+        .clksel         = hsi_fclk_div,
         .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
         .ops            = &clkops_omap2_dflt,
@@ -1791,6 +1693,26 @@ static struct clk i2c4_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ipu_fck = {
+        .name           = "ipu_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk iss_ctrlclk = {
+        .name           = "iss_ctrlclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk iss_fck = {
         .name           = "iss_fck",
         .ops            = &clkops_omap2_dflt,
@@ -1801,8 +1723,8 @@ static struct clk iss_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ivahd_ick = {
-        .name           = "ivahd_ick",
+static struct clk iva_fck = {
+        .name           = "iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk keyboard_fck = {
-        .name           = "keyboard_fck",
+static struct clk kbd_fck = {
+        .name           = "kbd_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_instr_interconnect_ick = {
-        .name           = "l3_instr_interconnect_ick",
+static struct clk l3_instr_ick = {
+        .name           = "l3_instr_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk l3_interconnect_3_ick = {
-        .name           = "l3_interconnect_3_ick",
+static struct clk l3_main_3_ick = {
+        .name           = "l3_main_3_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = {
         .clkdm_name     = "l4_per_clkdm",
 };
 
+static struct clk mcpdm_fck = {
+        .name           = "mcpdm_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk mcspi1_fck = {
         .name           = "mcspi1_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ocp_wp1_ick = {
-        .name           = "ocp_wp1_ick",
+static struct clk ocp2scp_usb_phy_phy_48m = {
+        .name           = "ocp2scp_usb_phy_phy_48m",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "l3_instr_clkdm",
-        .parent         = &l3_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pdm_fck = {
-        .name           = "pdm_fck",
+static struct clk ocp2scp_usb_phy_ick = {
+        .name           = "ocp2scp_usb_phy_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &pad_clks_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk pkaeip29_fck = {
-        .name           = "pkaeip29_fck",
+static struct clk ocp_wp_noc_ick = {
+        .name           = "ocp_wp_noc_ick",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_secure_clkdm",
-        .parent         = &l4_div_ck,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -2145,8 +2077,8 @@ static struct clk rng_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sha2md51_fck = {
-        .name           = "sha2md51_fck",
+static struct clk sha2md5_fck = {
+        .name           = "sha2md5_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sl2_ick = {
-        .name           = "sl2_ick",
+static struct clk sl2if_ick = {
+        .name           = "sl2if_ick",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
@@ -2165,6 +2097,46 @@ static struct clk sl2_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk slimbus1_fclk_1 = {
+        .name           = "slimbus1_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &func_24m_clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_0 = {
+        .name           = "slimbus1_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_fclk_2 = {
+        .name           = "slimbus1_fclk_2",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_slimbus_clk = {
+        .name           = "slimbus1_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &slimbus_clk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk slimbus1_fck = {
         .name           = "slimbus1_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2175,6 +2147,36 @@ static struct clk slimbus1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk slimbus2_fclk_1 = {
+        .name           = "slimbus2_fclk_1",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &per_abe_24m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_fclk_0 = {
+        .name           = "slimbus2_fclk_0",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_24mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_slimbus_clk = {
+        .name           = "slimbus2_slimbus_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &pad_slimbus_core_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk slimbus2_fck = {
         .name           = "slimbus2_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2185,8 +2187,8 @@ static struct clk slimbus2_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_core_fck = {
-        .name           = "sr_core_fck",
+static struct clk smartreflex_core_fck = {
+        .name           = "smartreflex_core_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2197,8 @@ static struct clk sr_core_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_iva_fck = {
-        .name           = "sr_iva_fck",
+static struct clk smartreflex_iva_fck = {
+        .name           = "smartreflex_iva_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2207,8 @@ static struct clk sr_iva_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk sr_mpu_fck = {
-        .name           = "sr_mpu_fck",
+static struct clk smartreflex_mpu_fck = {
+        .name           = "smartreflex_mpu_fck",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2217,175 @@ static struct clk sr_mpu_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk tesla_ick = {
-        .name           = "tesla_ick",
+/* Merged dmt1_clk_mux into timer1 */
+static struct clk timer1_fck = {
+        .name           = "timer1_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
-        .clkdm_name     = "tesla_clkdm",
-        .parent         = &dpll_iva_m4_ck,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* Merged cm2_dm10_mux into timer10 */
+static struct clk timer10_fck = {
+        .name           = "timer10_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm11_mux into timer11 */
+static struct clk timer11_fck = {
+        .name           = "timer11_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm2_mux into timer2 */
+static struct clk timer2_fck = {
+        .name           = "timer2_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm3_mux into timer3 */
+static struct clk timer3_fck = {
+        .name           = "timer3_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm4_mux into timer4 */
+static struct clk timer4_fck = {
+        .name           = "timer4_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged timer5_sync_mux into timer5 */
+static struct clk timer5_fck = {
+        .name           = "timer5_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer6_sync_mux into timer6 */
+static struct clk timer6_fck = {
+        .name           = "timer6_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer7_sync_mux into timer7 */
+static struct clk timer7_fck = {
+        .name           = "timer7_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer8_sync_mux into timer8 */
+static struct clk timer8_fck = {
+        .name           = "timer8_fck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged cm2_dm9_mux into timer9 */
+static struct clk timer9_fck = {
+        .name           = "timer9_fck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = abe_dpll_bypass_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
 };
 
 static struct clk uart1_fck = {
@@ -2265,105 +2428,148 @@ static struct clk uart4_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk unipro1_fck = {
-        .name           = "unipro1_fck",
+static struct clk usb_host_fs_fck = {
+        .name           = "usb_host_fs_fck",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_96m_fclk,
+        .parent         = &func_48mc_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fck = {
-        .name           = "usb_host_fck",
+static struct clk usb_host_hs_utmi_p3_clk = {
+        .name           = "usb_host_hs_utmi_p3_clk",
         .ops            = &clkops_omap2_dflt,
         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
         .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_fs_fck = {
-        .name           = "usb_host_fs_fck",
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+        .name           = "usb_host_hs_hsic60m_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &func_48mc_fclk,
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_otg_ick = {
-        .name           = "usb_otg_ick",
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+        .name           = "usb_host_hs_hsic60m_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l3_div_ck,
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_tll_ick = {
-        .name           = "usb_tll_ick",
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p1_gfclk = {
+        .name           = "utmi_p1_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p1_clk = {
+        .name           = "usb_host_hs_utmi_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
+        .parent         = &utmi_p1_gfclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usbphyocp2scp_ick = {
-        .name           = "usbphyocp2scp_ick",
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p2_gfclk = {
+        .name           = "utmi_p2_gfclk",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk usb_host_hs_utmi_p2_clk = {
+        .name           = "usb_host_hs_utmi_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
         .clkdm_name     = "l3_init_clkdm",
-        .parent         = &l4_div_ck,
+        .parent         = &utmi_p2_gfclk,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usim_fck = {
-        .name           = "usim_fck",
+static struct clk usb_host_hs_hsic480m_p1_clk = {
+        .name           = "usb_host_hs_hsic480m_p1_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
+static struct clk usb_host_hs_hsic480m_p2_clk = {
+        .name           = "usb_host_hs_hsic480m_p2_clk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .parent         = &sys_32k_ck,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &dpll_usb_m2_ck,
         .recalc         = &followparent_recalc,
 };
 
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
+static struct clk usb_host_hs_func48mclk = {
+        .name           = "usb_host_hs_func48mclk",
         .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_fck = {
+        .name           = "usb_host_hs_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
-        .clkdm_name     = "abe_clkdm",
-        .parent         = &sys_32k_ck,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
         .recalc         = &followparent_recalc,
 };
 
-/* Remaining optional clocks */
 static const struct clksel otg_60m_gfclk_sel[] = {
         { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
         { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
-static struct clk otg_60m_gfclk_ck = {
-        .name           = "otg_60m_gfclk_ck",
+static struct clk otg_60m_gfclk = {
+        .name           = "otg_60m_gfclk",
         .parent         = &utmi_phy_clkout_ck,
         .clksel         = otg_60m_gfclk_sel,
         .init           = &omap2_init_clksel_parent,
@@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-static const struct clksel stm_clk_div_div[] = {
-        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
+static struct clk usb_otg_hs_xclk = {
+        .name           = "usb_otg_hs_xclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &otg_60m_gfclk,
+        .recalc         = &followparent_recalc,
 };
 
-static struct clk stm_clk_div_ck = {
-        .name           = "stm_clk_div_ck",
-        .parent         = &pmd_stm_clock_mux_ck,
-        .clksel         = stm_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
+static struct clk usb_otg_hs_ick = {
+        .name           = "usb_otg_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
-static const struct clksel trace_clk_div_div[] = {
-        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
+static struct clk usb_phy_cm_clk32k = {
+        .name           = "usb_phy_cm_clk32k",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
 };
 
-static struct clk trace_clk_div_ck = {
-        .name           = "trace_clk_div_ck",
-        .parent         = &pmd_trace_clk_mux_ck,
-        .clksel         = trace_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-        .ops            = &clkops_null,
-        .recalc         = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap2_clksel_set_rate,
+static struct clk usb_tll_hs_usb_ch2_clk = {
+        .name           = "usb_tll_hs_usb_ch2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch0_clk = {
+        .name           = "usb_tll_hs_usb_ch0_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_usb_ch1_clk = {
+        .name           = "usb_tll_hs_usb_ch1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_hs_ick = {
+        .name           = "usb_tll_hs_ick",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
 };
 
 static const struct clksel_rate div2_14to18_rates[] = {
@@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = {
         { .parent = NULL },
 };
 
-static struct clk usim_fclk = {
-        .name           = "usim_fclk",
+static struct clk usim_ck = {
+        .name           = "usim_ck",
         .parent         = &dpll_per_m4_ck,
         .clksel         = usim_fclk_div,
         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
@@ -2430,38 +2672,79 @@ static struct clk usim_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel utmi_p1_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &usim_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wd_timer2_fck = {
+        .name           = "wd_timer2_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wd_timer3_fck = {
+        .name           = "wd_timer3_fck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* Remaining optional clocks */
+static const struct clksel stm_clk_div_div[] = {
+        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
-static struct clk utmi_p1_gfclk_ck = {
-        .name           = "utmi_p1_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p1_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+static struct clk stm_clk_div_ck = {
+        .name           = "stm_clk_div_ck",
+        .parent         = &pmd_stm_clock_mux_ck,
+        .clksel         = stm_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
         .ops            = &clkops_null,
         .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel utmi_p2_gfclk_sel[] = {
-        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
-        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
-static struct clk utmi_p2_gfclk_ck = {
-        .name           = "utmi_p2_gfclk_ck",
-        .parent         = &init_60m_fclk,
-        .clksel         = utmi_p2_gfclk_sel,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+static struct clk trace_clk_div_ck = {
+        .name           = "trace_clk_div_ck",
+        .parent         = &pmd_trace_clk_mux_ck,
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
         .ops            = &clkops_null,
         .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
 /*
@@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
@@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
-        CLK(NULL,       "cust_efuse_fck",               &cust_efuse_fck,        CK_443X),
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
+        CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK(NULL,       "ducati_ick",                   &ducati_ick,    CK_443X),
-        CLK(NULL,       "emif1_ick",                    &emif1_ick,     CK_443X),
-        CLK(NULL,       "emif2_ick",                    &emif2_ick,     CK_443X),
+        CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
+        CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
+        CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
-        CLK(NULL,       "gfx_fck",                      &gfx_fck,       CK_443X),
+        CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
+        CLK(NULL,       "gpio1_dbck",                   &gpio1_dbclk,   CK_443X),
         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
+        CLK(NULL,       "gpio2_dbck",                   &gpio2_dbclk,   CK_443X),
         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
+        CLK(NULL,       "gpio3_dbck",                   &gpio3_dbclk,   CK_443X),
         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
+        CLK(NULL,       "gpio4_dbck",                   &gpio4_dbclk,   CK_443X),
         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
+        CLK(NULL,       "gpio5_dbck",                   &gpio5_dbclk,   CK_443X),
         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
+        CLK(NULL,       "gpio6_dbck",                   &gpio6_dbclk,   CK_443X),
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
-        CLK(NULL,       "gpt1_fck",                     &gpt1_fck,      CK_443X),
-        CLK(NULL,       "gpt10_fck",                    &gpt10_fck,     CK_443X),
-        CLK(NULL,       "gpt11_fck",                    &gpt11_fck,     CK_443X),
-        CLK(NULL,       "gpt2_fck",                     &gpt2_fck,      CK_443X),
-        CLK(NULL,       "gpt3_fck",                     &gpt3_fck,      CK_443X),
-        CLK(NULL,       "gpt4_fck",                     &gpt4_fck,      CK_443X),
-        CLK(NULL,       "gpt5_fck",                     &gpt5_fck,      CK_443X),
-        CLK(NULL,       "gpt6_fck",                     &gpt6_fck,      CK_443X),
-        CLK(NULL,       "gpt7_fck",                     &gpt7_fck,      CK_443X),
-        CLK(NULL,       "gpt8_fck",                     &gpt8_fck,      CK_443X),
-        CLK(NULL,       "gpt9_fck",                     &gpt9_fck,      CK_443X),
+        CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
-        CLK(NULL,       "hsi_ick",                      &hsi_ick,       CK_443X),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
         CLK("i2c_omap.1",       "fck",                          &i2c1_fck,      CK_443X),
         CLK("i2c_omap.2",       "fck",                          &i2c2_fck,      CK_443X),
         CLK("i2c_omap.3",       "fck",                          &i2c3_fck,      CK_443X),
         CLK("i2c_omap.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
-        CLK(NULL,       "ivahd_ick",                    &ivahd_ick,     CK_443X),
-        CLK(NULL,       "keyboard_fck",                 &keyboard_fck,  CK_443X),
-        CLK(NULL,       "l3_instr_interconnect_ick",    &l3_instr_interconnect_ick,     CK_443X),
-        CLK(NULL,       "l3_interconnect_3_ick",        &l3_interconnect_3_ick, CK_443X),
+        CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
+        CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
+        CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
+        CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
@@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_fck,    CK_443X),
         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
         CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_fck,    CK_443X),
+        CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
         CLK("omap2_mcspi.1",    "fck",                          &mcspi1_fck,    CK_443X),
         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
@@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
         CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
         CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
-        CLK(NULL,       "ocp_wp1_ick",                  &ocp_wp1_ick,   CK_443X),
-        CLK(NULL,       "pdm_fck",                      &pdm_fck,       CK_443X),
-        CLK(NULL,       "pkaeip29_fck",                 &pkaeip29_fck,  CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
+        CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
+        CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
-        CLK(NULL,       "sha2md51_fck",                 &sha2md51_fck,  CK_443X),
-        CLK(NULL,       "sl2_ick",                      &sl2_ick,       CK_443X),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
+        CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
-        CLK(NULL,       "sr_core_fck",                  &sr_core_fck,   CK_443X),
-        CLK(NULL,       "sr_iva_fck",                   &sr_iva_fck,    CK_443X),
-        CLK(NULL,       "sr_mpu_fck",                   &sr_mpu_fck,    CK_443X),
-        CLK(NULL,       "tesla_ick",                    &tesla_ick,     CK_443X),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
+        CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
+        CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
+        CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
+        CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
+        CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
+        CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
+        CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
+        CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
+        CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
+        CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
+        CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK(NULL,       "unipro1_fck",                  &unipro1_fck,   CK_443X),
-        CLK(NULL,       "usb_host_fck",                 &usb_host_fck,  CK_443X),
         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK("musb_hdrc",        "ick",                          &usb_otg_ick,   CK_443X),
-        CLK(NULL,       "usb_tll_ick",                  &usb_tll_ick,   CK_443X),
-        CLK(NULL,       "usbphyocp2scp_ick",            &usbphyocp2scp_ick,     CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK("musb_hdrc",        "ick",                          &usb_otg_hs_ick,        CK_443X),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
-        CLK("omap_wdt", "fck",                          &wdt2_fck,      CK_443X),
-        CLK(NULL,       "wdt3_fck",                     &wdt3_fck,      CK_443X),
-        CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
+        CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
-        CLK(NULL,       "gpio1_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio2_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio3_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio4_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio5_dbck",                   &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpio6_dbck",                   &dummy_ck,      CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
@@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("i2c_omap.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("i2c_omap.3",       "ick",                          &dummy_ck,      CK_443X),
         CLK("i2c_omap.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.4",     "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.0",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "ick",          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "ick",          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.1",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.2",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.3",    "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap2_mcspi.4",    "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 5d80cb897489..6fb61b1a0d46 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
 
 }
 
-/**
- * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
- * @clkdm: clockdomain to initialize wkdep usecounts
- *
- * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
- * If a wakeup dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software wakeup dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
- */
-static void _init_wkdep_usecount(struct clockdomain *clkdm)
-{
-        u32 v;
-        struct clkdm_dep *cd;
-
-        if (!clkdm->wkdep_srcs)
-                return;
-
-        for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
-                             "found\n", clkdm->name, cd->clkdm_name);
-                        continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            PM_WKDEP,
-                                            (1 << cd->clkdm->dep_bit));
-
-                if (v)
-                        pr_debug("clockdomain: %s: wakeup dependency already "
-                                 "set to wake up when %s wakes\n",
-                                 clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
-        }
-}
-
-/**
- * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
- * @clkdm: clockdomain to initialize sleepdep usecounts
- *
- * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
- * If a sleep dependency is present in the hardware, the usecount will be
- * set to 1; otherwise, it will be set to 0.  Software should clear all
- * software sleep dependencies prior to calling this function if it wishes
- * to ensure that all usecounts start at 0.  No return value.
- */
-static void _init_sleepdep_usecount(struct clockdomain *clkdm)
-{
-        u32 v;
-        struct clkdm_dep *cd;
-
-        if (!cpu_is_omap34xx())
-                return;
-
-        if (!clkdm->sleepdep_srcs)
-                return;
-
-        for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
-                if (!omap_chip_is(cd->omap_chip))
-                        continue;
-
-                if (!cd->clkdm && cd->clkdm_name)
-                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
-
-                if (!cd->clkdm) {
-                        WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
-                             "not found\n", clkdm->name, cd->clkdm_name);
-                        continue;
-                }
-
-                v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
-                                            OMAP3430_CM_SLEEPDEP,
-                                            (1 << cd->clkdm->dep_bit));
-
-                if (v)
-                        pr_debug("clockdomain: %s: sleep dependency already "
-                                 "set to prevent from idling until %s "
-                                 "idles\n", clkdm->name, cd->clkdm->name);
-
-                atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
-        }
-};
-
 /* Public functions */
 
 /**
@@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms,
                         _autodep_lookup(autodep);
 
         /*
-         * Ensure that the *dep_usecount registers reflect the current
-         * state of the PRCM.
+         * Put all clockdomains into software-supervised mode; PM code
+         * should later enable hardware-supervised mode as appropriate
          */
         list_for_each_entry(clkdm, &clkdm_list, node) {
-                _init_wkdep_usecount(clkdm);
-                _init_sleepdep_usecount(clkdm);
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap2_clkdm_wakeup(clkdm);
+                else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
+                        omap2_clkdm_deny_idle(clkdm);
+
+                clkdm_clear_all_wkdeps(clkdm);
+                clkdm_clear_all_sleepdeps(clkdm);
         }
 }
 
@@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
                 if (!omap_chip_is(cd->omap_chip))
                         continue;
 
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
                 /* PRM accesses are slow, so minimize them */
                 mask |= 1 << cd->clkdm->dep_bit;
                 atomic_set(&cd->wkdep_usecount, 0);
@@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
                 if (!omap_chip_is(cd->omap_chip))
                         continue;
 
+                if (!cd->clkdm && cd->clkdm_name)
+                        cd->clkdm = _clkdm_lookup(cd->clkdm_name);
+
                 /* PRM accesses are slow, so minimize them */
                 mask |= 1 << cd->clkdm->dep_bit;
                 atomic_set(&cd->sleepdep_usecount, 0);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index fe82b79d5f3b..4f959a7d881c 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -649,6 +649,8 @@
 #define OMAP3430_ST_MCBSP2_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE_PER */
+#define OMAP3630_AUTO_UART4_MASK                        (1 << 18)
+#define OMAP3630_AUTO_UART4_SHIFT                       18
 #define OMAP3430_AUTO_GPIO6_MASK                        (1 << 17)
 #define OMAP3430_AUTO_GPIO6_SHIFT                       17
 #define OMAP3430_AUTO_GPIO5_MASK                        (1 << 16)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index ac8458e43252..0b72be433776 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -25,453 +25,459 @@
 #include "cm.h"
 
 
-/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/*
+ * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
+ * CM_TESLA_DYNAMICDEP
+ */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
-#define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
+#define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
-#define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
+#define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
-#define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
-#define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
+#define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
- * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
+ * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
+ * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
-#define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
+#define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
-#define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
-#define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
+#define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
-#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
-#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
-#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
-#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
-#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
-#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
-#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
-#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
-#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
-#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
-#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
-#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
-#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
-#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
-#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
-#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
-
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
-#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
-#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
-#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
-#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
-#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
-#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
-#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
-#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
-
-/* Used by CM_L3INIT_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               31
-#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
-#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
-#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
-#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
-#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
-#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
-#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        14
-#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
-#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
-#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
-#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
-#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
-#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
-#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
-#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
-#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
-#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
-#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
-#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
-#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
-
-/* Used by CM_EMU_CLKSTCTRL */
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             10
-#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
-#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             21
-#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              (1 << 21)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
-#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
-#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
-#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
-#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
-#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
-#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
-#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
-#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
-#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
-#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
-#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
-#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
-#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
-#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
-#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /*
- * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
+ * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
  * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
- * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL
+ * CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
-#define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
  * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
- * CM_CLKSEL_USB_60MHZ
+ * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
-#define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
-#define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
+#define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
-#define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
-#define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
-#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
-#define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
-/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
-#define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
+#define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
-#define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
-#define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
  * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
@@ -479,836 +485,869 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
-#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
-#define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
-/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+/*
+ * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
+ * CM_SHADOW_FREQ_CONFIG2
+ */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
-#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
-/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
-#define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
-#define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
-
-/* Used by CM_GFX_GFX_CLKCTRL */
-#define OMAP4430_CLKSEL_PER_192M_SHIFT                          25
-#define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
+#define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
-#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
-#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
-#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
  * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
-#define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
-#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
-#define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
+#define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
-#define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
+#define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
- * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
- * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
- * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
- * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
- * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
- * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
+ * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
+ * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
+ * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
+ * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
+ * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+ * CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
-#define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
+#define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
-#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
+#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
-#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
+#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
-#define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
+#define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
-#define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
+#define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /*
- * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
- * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
- * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
- * CM_SSC_DELTAMSTEP_DPLL_MPU
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+ * CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
-#define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
+#define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             2
-#define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
+#define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 2)
 
 /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         0
-#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DLL_RESET_SHIFT                                3
-#define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
-#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
+/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
-#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
-#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
-#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
-#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
-#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
-#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
-#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
-#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
-#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
-#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
-#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
-#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
-
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 1
-#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
-#define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
+#define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
-#define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
+#define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
-#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
-#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
-#define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
+#define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
-#define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
+#define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
- * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
-#define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
+#define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
-#define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
+#define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
-#define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
+#define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
-#define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
+#define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
-#define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
+#define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
-#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
- * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
-#define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
+#define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
-#define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
+#define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
-#define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
+#define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
-#define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
+#define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
-/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
-#define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
+#define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
-/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
-#define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
+#define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
-#define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
+#define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
-#define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
+#define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
-/* Used by CM_SHADOW_FREQ_CONFIG2 */
+/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
-#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
-#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
-#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
-#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
-#define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
-/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+/*
+ * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
-#define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
+#define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
-#define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
+#define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
-#define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
+#define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
-#define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
+#define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
-#define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
+#define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
-#define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
+#define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
- * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
+ * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
-#define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
+#define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
-#define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
+#define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
- * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
- * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
+ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
+ * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
+ * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
-#define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
+#define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
-#define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
+#define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
-/* Used by CM_L3_1_DYNAMICDEP */
+/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
-#define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
+#define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
-#define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
+#define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
-/* Used by CM_L3_2_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
-#define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
+#define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
-#define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
+#define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
-/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE
+ */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
-#define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
+#define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
-#define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
+#define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
-#define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
- * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
-#define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
+#define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
- * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_MPU_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
-#define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
+#define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
- * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
- * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
- * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
+ * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
-#define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
+#define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
-#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
+#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
- * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
- * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
- * CM_SSC_MODFREQDIV_DPLL_MPU
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
-#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
-
-/*
- * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
- * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
- * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
- * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
- * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
- * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
- * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
- * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
- * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
- * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
- * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
- * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
- * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
- * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
- * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
- * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
- * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
- * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
- * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
+
+/*
+ * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
+ * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
- * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
- * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
- * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
- * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
- * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
- * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
+ * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
+ * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
+ * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
+ * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
+ * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
+ * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
-#define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
+#define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
-#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
-/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
-#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         9
-#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
+/* Used by CM_ALWON_USBPHY_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
- * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
-#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
+
+/* Used by CM_WKUP_USIM_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
-#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
-#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
-#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
-#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
-#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
-#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
-#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
-#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
-#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
-#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
-#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
-#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
-#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
-#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
-#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
-#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
-#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
-#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
-#define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
-/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
-#define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
+#define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
-#define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
-#define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
+#define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
  * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
@@ -1316,159 +1355,173 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
-#define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         0
-#define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
-
-/* Used by CM_EMU_OVERRIDE_DPLL_PER */
-#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        8
-#define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
+#define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
-#define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
+#define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
-#define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
+#define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
-#define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
+#define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
-#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
+#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
-#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
-/* Used by CM_DYN_DEP_PRESCAL */
+/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
 #define OMAP4430_PRESCAL_SHIFT                                  0
-#define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
+#define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
-/* Used by REVISION_CM2, REVISION_CM1 */
-#define OMAP4430_REV_SHIFT                                      0
-#define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /*
- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+ * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
  */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
-#define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
-#define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
+#define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
-#define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
+#define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
-#define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
+#define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
-#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
- * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
  * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
  * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
- * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
-#define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
+#define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
- * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
- * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
- * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
-#define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
+#define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
- * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
- * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
- * CM_DIV_M2_DPLL_MPU
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
-#define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /*
- * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
- * CM_DIV_M3_DPLL_CORE
+ * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
  */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
-#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
-/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
-#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
- * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /*
- * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_CORE
+ * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
-#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
+ * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
+ */
+#define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
-#define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
+#define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
-/* Used by CM_L4CFG_DYNAMICDEP */
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
-#define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
+#define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
-#define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
+#define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
- * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
+ * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
+ * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
-#define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
+#define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
+
+/* Used by REVISION_CM1, REVISION_CM2 */
+#define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 336d94889e5b..3c35a87cb90c 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -195,6 +195,42 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
 
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET        0x0024
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
+#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
+#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
+#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
+
 /* CM2 */
 
 /* CM2.OCP_SOCKET_CM2 register offsets */
@@ -252,8 +288,6 @@
 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET           0x0070
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
 #define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
@@ -296,6 +330,8 @@
 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
 #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
+#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
 
 /* CM2.CORE_CM2 register offsets */
 #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
@@ -578,4 +614,54 @@
 #define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
+#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
+#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
+#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
+#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
+#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
+#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
+#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
+#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
+#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
+#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
+#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
+#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
+#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
+#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
+#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
 #endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index b101091e95d6..f8a660a1a4a6 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -43,7 +43,6 @@
  *                 using separate functional clock
  *   0x3 disabled: Module is disabled and cannot be accessed
  *
- * TODO: Need to handle module accessible in idle state
  */
 int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
 {
@@ -52,9 +51,11 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
         if (!clkctrl_reg)
                 return 0;
 
-        omap_test_timeout(((__raw_readl(clkctrl_reg) &
-                            OMAP4430_IDLEST_MASK) == 0),
-                          MAX_MODULE_READY_TIME, i);
+        omap_test_timeout((
+                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
+                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
+                  OMAP4430_IDLEST_SHIFT) == 0x2)),
+                MAX_MODULE_READY_TIME, i);
 
         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
new file mode 100644
index 000000000000..778929f7e92d
--- /dev/null
+++ b/arch/arm/mach-omap2/common.c
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/mach-omap2/common.c
+ *
+ * Code common to all OMAP2+ machines.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2010 Nokia Corporation
+ * Tony Lindgren <tony@atomide.com>
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+#include <plat/board.h>
+#include <plat/mux.h>
+
+#include <plat/clock.h>
+
+#include "sdrc.h"
+#include "control.h"
+
+/* Global address base setup code */
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
+{
+        omap2_set_globals_tap(omap2_globals);
+        omap2_set_globals_sdrc(omap2_globals);
+        omap2_set_globals_control(omap2_globals);
+        omap2_set_globals_prcm(omap2_globals);
+}
+
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2420)
+
+static struct omap_globals omap242x_globals = {
+        .class  = OMAP242X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
+        .sdrc   = OMAP2420_SDRC_BASE,
+        .sms    = OMAP2420_SMS_BASE,
+        .ctrl   = OMAP242X_CTRL_BASE,
+        .prm    = OMAP2420_PRM_BASE,
+        .cm     = OMAP2420_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
+};
+
+void __init omap2_set_globals_242x(void)
+{
+        __omap2_set_globals(&omap242x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP2430)
+
+static struct omap_globals omap243x_globals = {
+        .class  = OMAP243X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
+        .sdrc   = OMAP243X_SDRC_BASE,
+        .sms    = OMAP243X_SMS_BASE,
+        .ctrl   = OMAP243X_CTRL_BASE,
+        .prm    = OMAP2430_PRM_BASE,
+        .cm     = OMAP2430_CM_BASE,
+        .uart1_phys     = OMAP2_UART1_BASE,
+        .uart2_phys     = OMAP2_UART2_BASE,
+        .uart3_phys     = OMAP2_UART3_BASE,
+};
+
+void __init omap2_set_globals_243x(void)
+{
+        __omap2_set_globals(&omap243x_globals);
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3)
+
+static struct omap_globals omap3_globals = {
+        .class  = OMAP343X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
+        .sdrc   = OMAP343X_SDRC_BASE,
+        .sms    = OMAP343X_SMS_BASE,
+        .ctrl   = OMAP343X_CTRL_BASE,
+        .prm    = OMAP3430_PRM_BASE,
+        .cm     = OMAP3430_CM_BASE,
+        .uart1_phys     = OMAP3_UART1_BASE,
+        .uart2_phys     = OMAP3_UART2_BASE,
+        .uart3_phys     = OMAP3_UART3_BASE,
+        .uart4_phys     = OMAP3_UART4_BASE,     /* Only on 3630 */
+};
+
+void __init omap2_set_globals_3xxx(void)
+{
+        __omap2_set_globals(&omap3_globals);
+}
+
+void __init omap3_map_io(void)
+{
+        omap2_set_globals_3xxx();
+        omap34xx_map_common_io();
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4)
+static struct omap_globals omap4_globals = {
+        .class  = OMAP443X_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
+        .ctrl   = OMAP443X_SCM_BASE,
+        .ctrl_pad       = OMAP443X_CTRL_BASE,
+        .prm    = OMAP4430_PRM_BASE,
+        .cm     = OMAP4430_CM_BASE,
+        .cm2    = OMAP4430_CM2_BASE,
+        .uart1_phys     = OMAP4_UART1_BASE,
+        .uart2_phys     = OMAP4_UART2_BASE,
+        .uart3_phys     = OMAP4_UART3_BASE,
+        .uart4_phys     = OMAP4_UART4_BASE,
+};
+
+void __init omap2_set_globals_443x(void)
+{
+        omap2_set_globals_tap(&omap4_globals);
+        omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
+}
+#endif
+
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20eef2306..1fa3294b6048 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -16,15 +16,18 @@
 #include <linux/io.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/sdrc.h>
+
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "prm.h"
 #include "sdrc.h"
+#include "pm.h"
+#include "control.h"
 
 static void __iomem *omap2_ctrl_base;
+static void __iomem *omap4_ctrl_pad_base;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 struct omap3_scratchpad {
@@ -137,6 +140,7 @@ static struct omap3_control_regs control_context;
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 
 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
+#define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 
 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 {
@@ -145,6 +149,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
                 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
                 WARN_ON(!omap2_ctrl_base);
         }
+
+        /* Static mapping, never released */
+        if (omap2_globals->ctrl_pad) {
+                omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
+                WARN_ON(!omap4_ctrl_pad_base);
+        }
 }
 
 void __iomem *omap_ctrl_base_get(void)
@@ -182,6 +192,23 @@ void omap_ctrl_writel(u32 val, u16 offset)
         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 }
 
+/*
+ * On OMAP4 control pad are not addressable from control
+ * core base. So the common omap_ctrl_read/write APIs breaks
+ * Hence export separate APIs to manage the omap4 pad control
+ * registers. This APIs will work only for OMAP4
+ */
+
+u32 omap4_ctrl_pad_readl(u16 offset)
+{
+        return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
+void omap4_ctrl_pad_writel(u32 val, u16 offset)
+{
+        __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+}
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
@@ -190,7 +217,7 @@ void omap_ctrl_writel(u32 val, u16 offset)
 void omap3_clear_scratchpad_contents(void)
 {
         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
-        u32 *v_addr;
+        void __iomem *v_addr;
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
         if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
@@ -206,7 +233,7 @@ void omap3_clear_scratchpad_contents(void)
 /* Populate the scratchpad structure with restore structure */
 void omap3_save_scratchpad_contents(void)
 {
-        void * __iomem scratchpad_address;
+        void  __iomem *scratchpad_address;
         u32 arm_context_addr;
         struct omap3_scratchpad scratchpad_contents;
         struct omap3_scratchpad_prcm_block prcm_block_contents;
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
new file mode 100644
index 000000000000..b6c6b7c450b3
--- /dev/null
+++ b/arch/arm/mach-omap2/control.h
@@ -0,0 +1,368 @@
+/*
+ * arch/arm/mach-omap2/control.h
+ *
+ * OMAP2/3/4 System Control Module definitions
+ *
+ * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008, 2010 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
+#define __ARCH_ARM_MACH_OMAP2_CONTROL_H
+
+#include <mach/io.h>
+#include <mach/ctrl_module_core_44xx.h>
+#include <mach/ctrl_module_wkup_44xx.h>
+#include <mach/ctrl_module_pad_core_44xx.h>
+#include <mach/ctrl_module_pad_wkup_44xx.h>
+
+#ifndef __ASSEMBLY__
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#else
+#define OMAP242X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
+#define OMAP243X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
+#define OMAP343X_CTRL_REGADDR(reg)                                      \
+                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
+ * OMAP24XX and OMAP34XX.
+ */
+
+/* Control submodule offsets */
+
+#define OMAP2_CONTROL_INTERFACE         0x000
+#define OMAP2_CONTROL_PADCONFS          0x030
+#define OMAP2_CONTROL_GENERAL           0x270
+#define OMAP343X_CONTROL_MEM_WKUP       0x600
+#define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
+#define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
+
+/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
+
+#define OMAP2_CONTROL_SYSCONFIG         (OMAP2_CONTROL_INTERFACE + 0x10)
+
+/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */
+#define OMAP2_CONTROL_DEVCONF0          (OMAP2_CONTROL_GENERAL + 0x0004)
+#define OMAP2_CONTROL_MSUSPENDMUX_0     (OMAP2_CONTROL_GENERAL + 0x0020)
+#define OMAP2_CONTROL_MSUSPENDMUX_1     (OMAP2_CONTROL_GENERAL + 0x0024)
+#define OMAP2_CONTROL_MSUSPENDMUX_2     (OMAP2_CONTROL_GENERAL + 0x0028)
+#define OMAP2_CONTROL_MSUSPENDMUX_3     (OMAP2_CONTROL_GENERAL + 0x002c)
+#define OMAP2_CONTROL_MSUSPENDMUX_4     (OMAP2_CONTROL_GENERAL + 0x0030)
+#define OMAP2_CONTROL_MSUSPENDMUX_5     (OMAP2_CONTROL_GENERAL + 0x0034)
+#define OMAP2_CONTROL_SEC_CTRL          (OMAP2_CONTROL_GENERAL + 0x0040)
+#define OMAP2_CONTROL_RPUB_KEY_H_0      (OMAP2_CONTROL_GENERAL + 0x0090)
+#define OMAP2_CONTROL_RPUB_KEY_H_1      (OMAP2_CONTROL_GENERAL + 0x0094)
+#define OMAP2_CONTROL_RPUB_KEY_H_2      (OMAP2_CONTROL_GENERAL + 0x0098)
+#define OMAP2_CONTROL_RPUB_KEY_H_3      (OMAP2_CONTROL_GENERAL + 0x009c)
+
+/* 242x-only CONTROL_GENERAL register offsets */
+#define OMAP242X_CONTROL_DEVCONF        OMAP2_CONTROL_DEVCONF0 /* match TRM */
+#define OMAP242X_CONTROL_OCM_RAM_PERM   (OMAP2_CONTROL_GENERAL + 0x0068)
+
+/* 243x-only CONTROL_GENERAL register offsets */
+/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */
+#define OMAP243X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP243X_CONTROL_CSIRXFE        (OMAP2_CONTROL_GENERAL + 0x007c)
+#define OMAP243X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP243X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP243X_CONTROL_IVA2_GEMCFG    (OMAP2_CONTROL_GENERAL + 0x0198)
+#define OMAP243X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x0230)
+
+/* 24xx-only CONTROL_GENERAL register offsets */
+#define OMAP24XX_CONTROL_DEBOBS         (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP24XX_CONTROL_EMU_SUPPORT    (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP24XX_CONTROL_SEC_TEST       (OMAP2_CONTROL_GENERAL + 0x0044)
+#define OMAP24XX_CONTROL_PSA_CTRL       (OMAP2_CONTROL_GENERAL + 0x0048)
+#define OMAP24XX_CONTROL_PSA_CMD        (OMAP2_CONTROL_GENERAL + 0x004c)
+#define OMAP24XX_CONTROL_PSA_VALUE      (OMAP2_CONTROL_GENERAL + 0x0050)
+#define OMAP24XX_CONTROL_SEC_EMU        (OMAP2_CONTROL_GENERAL + 0x0060)
+#define OMAP24XX_CONTROL_SEC_TAP        (OMAP2_CONTROL_GENERAL + 0x0064)
+#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD        (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD  (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD   (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP24XX_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP24XX_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP24XX_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0088)
+#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c)
+#define OMAP24XX_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP24XX_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00a4)
+#define OMAP24XX_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP24XX_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP24XX_CONTROL_CUST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP24XX_CONTROL_CUST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP24XX_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c0)
+#define OMAP24XX_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00c4)
+#define OMAP24XX_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP24XX_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP24XX_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP24XX_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP24XX_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP24XX_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP24XX_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP24XX_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00e4)
+
+#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0)
+
+/* 34xx-only CONTROL_GENERAL register offsets */
+#define OMAP343X_CONTROL_PADCONF_OFF    (OMAP2_CONTROL_GENERAL + 0x0000)
+#define OMAP343X_CONTROL_MEM_DFTRW0     (OMAP2_CONTROL_GENERAL + 0x0008)
+#define OMAP343X_CONTROL_MEM_DFTRW1     (OMAP2_CONTROL_GENERAL + 0x000c)
+#define OMAP343X_CONTROL_DEVCONF1       (OMAP2_CONTROL_GENERAL + 0x0068)
+#define OMAP343X_CONTROL_CSIRXFE                (OMAP2_CONTROL_GENERAL + 0x006c)
+#define OMAP343X_CONTROL_SEC_STATUS             (OMAP2_CONTROL_GENERAL + 0x0070)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS         (OMAP2_CONTROL_GENERAL + 0x0074)
+#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG   (OMAP2_CONTROL_GENERAL + 0x0078)
+#define OMAP343X_CONTROL_STATUS                 (OMAP2_CONTROL_GENERAL + 0x0080)
+#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084)
+#define OMAP343X_CONTROL_RPUB_KEY_H_4   (OMAP2_CONTROL_GENERAL + 0x00a0)
+#define OMAP343X_CONTROL_RAND_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00a8)
+#define OMAP343X_CONTROL_RAND_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00ac)
+#define OMAP343X_CONTROL_RAND_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00b0)
+#define OMAP343X_CONTROL_RAND_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00b4)
+#define OMAP343X_CONTROL_TEST_KEY_0     (OMAP2_CONTROL_GENERAL + 0x00c8)
+#define OMAP343X_CONTROL_TEST_KEY_1     (OMAP2_CONTROL_GENERAL + 0x00cc)
+#define OMAP343X_CONTROL_TEST_KEY_2     (OMAP2_CONTROL_GENERAL + 0x00d0)
+#define OMAP343X_CONTROL_TEST_KEY_3     (OMAP2_CONTROL_GENERAL + 0x00d4)
+#define OMAP343X_CONTROL_TEST_KEY_4     (OMAP2_CONTROL_GENERAL + 0x00d8)
+#define OMAP343X_CONTROL_TEST_KEY_5     (OMAP2_CONTROL_GENERAL + 0x00dc)
+#define OMAP343X_CONTROL_TEST_KEY_6     (OMAP2_CONTROL_GENERAL + 0x00e0)
+#define OMAP343X_CONTROL_TEST_KEY_7     (OMAP2_CONTROL_GENERAL + 0x00e4)
+#define OMAP343X_CONTROL_TEST_KEY_8     (OMAP2_CONTROL_GENERAL + 0x00e8)
+#define OMAP343X_CONTROL_TEST_KEY_9     (OMAP2_CONTROL_GENERAL + 0x00ec)
+#define OMAP343X_CONTROL_TEST_KEY_10    (OMAP2_CONTROL_GENERAL + 0x00f0)
+#define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
+#define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
+#define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
+#define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
+#define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
+                                        + ((i) >> 1) * 4 + (!((i) & 1)) * 2)
+#define OMAP343X_CONTROL_PROG_IO0       (OMAP2_CONTROL_GENERAL + 0x01D4)
+#define OMAP343X_CONTROL_PROG_IO1       (OMAP2_CONTROL_GENERAL + 0x01D8)
+#define OMAP343X_CONTROL_DSS_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E0)
+#define OMAP343X_CONTROL_CORE_DPLL_SPREADING    (OMAP2_CONTROL_GENERAL + 0x01E4)
+#define OMAP343X_CONTROL_PER_DPLL_SPREADING     (OMAP2_CONTROL_GENERAL + 0x01E8)
+#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC)
+#define OMAP343X_CONTROL_PBIAS_LITE     (OMAP2_CONTROL_GENERAL + 0x02B0)
+#define OMAP343X_CONTROL_TEMP_SENSOR    (OMAP2_CONTROL_GENERAL + 0x02B4)
+#define OMAP343X_CONTROL_SRAMLDO4       (OMAP2_CONTROL_GENERAL + 0x02B8)
+#define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
+#define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
+
+/* AM35XX only CONTROL_GENERAL register offsets */
+#define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
+#define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
+#define AM35XX_CONTROL_DEVCONF3         (OMAP2_CONTROL_GENERAL + 0x0314)
+#define AM35XX_CONTROL_CBA_PRIORITY     (OMAP2_CONTROL_GENERAL + 0x0320)
+#define AM35XX_CONTROL_LVL_INTR_CLEAR   (OMAP2_CONTROL_GENERAL + 0x0324)
+#define AM35XX_CONTROL_IP_SW_RESET      (OMAP2_CONTROL_GENERAL + 0x0328)
+#define AM35XX_CONTROL_IPSS_CLK_CTRL    (OMAP2_CONTROL_GENERAL + 0x032C)
+
+/* 34xx PADCONF register offsets */
+#define OMAP343X_PADCONF_ETK(i)         (OMAP2_CONTROL_PADCONFS + 0x5a8 + \
+                                                (i)*2)
+#define OMAP343X_PADCONF_ETK_CLK        OMAP343X_PADCONF_ETK(0)
+#define OMAP343X_PADCONF_ETK_CTL        OMAP343X_PADCONF_ETK(1)
+#define OMAP343X_PADCONF_ETK_D0         OMAP343X_PADCONF_ETK(2)
+#define OMAP343X_PADCONF_ETK_D1         OMAP343X_PADCONF_ETK(3)
+#define OMAP343X_PADCONF_ETK_D2         OMAP343X_PADCONF_ETK(4)
+#define OMAP343X_PADCONF_ETK_D3         OMAP343X_PADCONF_ETK(5)
+#define OMAP343X_PADCONF_ETK_D4         OMAP343X_PADCONF_ETK(6)
+#define OMAP343X_PADCONF_ETK_D5         OMAP343X_PADCONF_ETK(7)
+#define OMAP343X_PADCONF_ETK_D6         OMAP343X_PADCONF_ETK(8)
+#define OMAP343X_PADCONF_ETK_D7         OMAP343X_PADCONF_ETK(9)
+#define OMAP343X_PADCONF_ETK_D8         OMAP343X_PADCONF_ETK(10)
+#define OMAP343X_PADCONF_ETK_D9         OMAP343X_PADCONF_ETK(11)
+#define OMAP343X_PADCONF_ETK_D10        OMAP343X_PADCONF_ETK(12)
+#define OMAP343X_PADCONF_ETK_D11        OMAP343X_PADCONF_ETK(13)
+#define OMAP343X_PADCONF_ETK_D12        OMAP343X_PADCONF_ETK(14)
+#define OMAP343X_PADCONF_ETK_D13        OMAP343X_PADCONF_ETK(15)
+#define OMAP343X_PADCONF_ETK_D14        OMAP343X_PADCONF_ETK(16)
+#define OMAP343X_PADCONF_ETK_D15        OMAP343X_PADCONF_ETK(17)
+
+/* 34xx GENERAL_WKUP regist offsets */
+#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \
+                                                0x008 + (i))
+#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008)
+#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C)
+#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010)
+#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
+#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+
+/* 34xx D2D idle-related pins, handled by PM core */
+#define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
+#define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
+
+/*
+ * REVISIT: This list of registers is not comprehensive - there are more
+ * that should be added.
+ */
+
+/*
+ * Control module register bit defines - these should eventually go into
+ * their own regbits file.  Some of these will be complicated, depending
+ * on the device type (general-purpose, emulator, test, secure, bad, other)
+ * and the security mode (secure, non-secure, don't care)
+ */
+/* CONTROL_DEVCONF0 bits */
+#define OMAP2_MMCSDIO1ADPCLKISEL        (1 << 24) /* MMC1 loop back clock */
+#define OMAP24XX_USBSTANDBYCTRL         (1 << 15)
+#define OMAP2_MCBSP2_CLKS_MASK          (1 << 6)
+#define OMAP2_MCBSP1_FSR_MASK           (1 << 4)
+#define OMAP2_MCBSP1_CLKR_MASK          (1 << 3)
+#define OMAP2_MCBSP1_CLKS_MASK          (1 << 2)
+
+/* CONTROL_DEVCONF1 bits */
+#define OMAP243X_MMC1_ACTIVE_OVERWRITE  (1 << 31)
+#define OMAP2_MMCSDIO2ADPCLKISEL        (1 << 6) /* MMC2 loop back clock */
+#define OMAP2_MCBSP5_CLKS_MASK          (1 << 4) /* > 242x */
+#define OMAP2_MCBSP4_CLKS_MASK          (1 << 2) /* > 242x */
+#define OMAP2_MCBSP3_CLKS_MASK          (1 << 0) /* > 242x */
+
+/* CONTROL_STATUS bits */
+#define OMAP2_DEVICETYPE_MASK           (0x7 << 8)
+#define OMAP2_SYSBOOT_5_MASK            (1 << 5)
+#define OMAP2_SYSBOOT_4_MASK            (1 << 4)
+#define OMAP2_SYSBOOT_3_MASK            (1 << 3)
+#define OMAP2_SYSBOOT_2_MASK            (1 << 2)
+#define OMAP2_SYSBOOT_1_MASK            (1 << 1)
+#define OMAP2_SYSBOOT_0_MASK            (1 << 0)
+
+/* CONTROL_PBIAS_LITE bits */
+#define OMAP343X_PBIASLITESUPPLY_HIGH1  (1 << 15)
+#define OMAP343X_PBIASLITEVMODEERROR1   (1 << 11)
+#define OMAP343X_PBIASSPEEDCTRL1        (1 << 10)
+#define OMAP343X_PBIASLITEPWRDNZ1       (1 << 9)
+#define OMAP343X_PBIASLITEVMODE1        (1 << 8)
+#define OMAP343X_PBIASLITESUPPLY_HIGH0  (1 << 7)
+#define OMAP343X_PBIASLITEVMODEERROR0   (1 << 3)
+#define OMAP2_PBIASSPEEDCTRL0           (1 << 2)
+#define OMAP2_PBIASLITEPWRDNZ0          (1 << 1)
+#define OMAP2_PBIASLITEVMODE0           (1 << 0)
+
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL   (1 << 20)
+
+/* CONTROL_IVA2_BOOTMOD bits */
+#define OMAP3_IVA2_BOOTMOD_SHIFT        0
+#define OMAP3_IVA2_BOOTMOD_MASK         (0xf << 0)
+#define OMAP3_IVA2_BOOTMOD_IDLE         (0x1 << 0)
+
+/* CONTROL_PADCONF_X bits */
+#define OMAP3_PADCONF_WAKEUPEVENT0      (1 << 15)
+#define OMAP3_PADCONF_WAKEUPENABLE0     (1 << 14)
+
+#define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
+#define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
+#define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+
+/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
+#define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
+#define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
+#define AM35XX_CPGMAC_C0_TX_PULSE_CLR   BIT(3)
+#define AM35XX_USBOTGSS_INT_CLR         BIT(4)
+#define AM35XX_VPFE_CCDC_VD0_INT_CLR    BIT(5)
+#define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
+#define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
+
+/*AM35XX CONTROL_IP_SW_RESET bits*/
+#define AM35XX_USBOTGSS_SW_RST          BIT(0)
+#define AM35XX_CPGMACSS_SW_RST          BIT(1)
+#define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
+#define AM35XX_HECC_SW_RST              BIT(3)
+#define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
+
+/*
+ * CONTROL OMAP STATUS register to identify OMAP3 features
+ */
+#define OMAP3_CONTROL_OMAP_STATUS       0x044c
+
+#define OMAP3_SGX_SHIFT                 13
+#define OMAP3_SGX_MASK                  (3 << OMAP3_SGX_SHIFT)
+#define         FEAT_SGX_FULL           0
+#define         FEAT_SGX_HALF           1
+#define         FEAT_SGX_NONE           2
+
+#define OMAP3_IVA_SHIFT                 12
+#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define         FEAT_IVA                0
+#define         FEAT_IVA_NONE           1
+
+#define OMAP3_L2CACHE_SHIFT             10
+#define OMAP3_L2CACHE_MASK              (3 << OMAP3_L2CACHE_SHIFT)
+#define         FEAT_L2CACHE_NONE       0
+#define         FEAT_L2CACHE_64KB       1
+#define         FEAT_L2CACHE_128KB      2
+#define         FEAT_L2CACHE_256KB      3
+
+#define OMAP3_ISP_SHIFT                 5
+#define OMAP3_ISP_MASK                  (1 << OMAP3_ISP_SHIFT)
+#define         FEAT_ISP                0
+#define         FEAT_ISP_NONE           1
+
+#define OMAP3_NEON_SHIFT                4
+#define OMAP3_NEON_MASK                 (1 << OMAP3_NEON_SHIFT)
+#define         FEAT_NEON               0
+#define         FEAT_NEON_NONE          1
+
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_ARCH_OMAP2PLUS
+extern void __iomem *omap_ctrl_base_get(void);
+extern u8 omap_ctrl_readb(u16 offset);
+extern u16 omap_ctrl_readw(u16 offset);
+extern u32 omap_ctrl_readl(u16 offset);
+extern u32 omap4_ctrl_pad_readl(u16 offset);
+extern void omap_ctrl_writeb(u8 val, u16 offset);
+extern void omap_ctrl_writew(u16 val, u16 offset);
+extern void omap_ctrl_writel(u32 val, u16 offset);
+extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
+
+extern void omap3_save_scratchpad_contents(void);
+extern void omap3_clear_scratchpad_contents(void);
+extern u32 *get_restore_pointer(void);
+extern u32 *get_es3_restore_pointer(void);
+extern u32 omap3_arm_context[128];
+extern void omap3_control_save_context(void);
+extern void omap3_control_restore_context(void);
+
+#else
+#define omap_ctrl_base_get()            0
+#define omap_ctrl_readb(x)              0
+#define omap_ctrl_readw(x)              0
+#define omap_ctrl_readl(x)              0
+#define omap4_ctrl_pad_readl(x)         0
+#define omap_ctrl_writeb(x, y)          WARN_ON(1)
+#define omap_ctrl_writew(x, y)          WARN_ON(1)
+#define omap_ctrl_writel(x, y)          WARN_ON(1)
+#define omap4_ctrl_pad_writel(x, y)     WARN_ON(1)
+#endif
+#endif  /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */
+
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 3d3d035db9af..0d50b45d041c 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -29,10 +29,10 @@
 #include <plat/irqs.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
-#include <plat/control.h>
 #include <plat/serial.h>
 
 #include "pm.h"
+#include "control.h"
 
 #ifdef CONFIG_CPU_IDLE
 
@@ -60,7 +60,8 @@ struct omap3_processor_cx {
 
 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
 struct omap3_processor_cx current_cx_state;
-struct powerdomain *mpu_pd, *core_pd;
+struct powerdomain *mpu_pd, *core_pd, *per_pd;
+struct powerdomain *cam_pd;
 
 /*
  * The latencies/thresholds for various C states have
@@ -233,14 +234,60 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                                struct cpuidle_state *state)
 {
         struct cpuidle_state *new_state = next_valid_state(dev, state);
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
+        u32 cam_state;
+        struct omap3_processor_cx *cx;
+        int ret;
 
         if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
                 BUG_ON(!dev->safe_state);
                 new_state = dev->safe_state;
+                goto select_state;
         }
 
+        cx = cpuidle_get_statedata(state);
+        core_next_state = cx->core_state;
+
+        /*
+         * FIXME: we currently manage device-specific idle states
+         *        for PER and CORE in combination with CPU-specific
+         *        idle states.  This is wrong, and device-specific
+         *        idle managment needs to be separated out into 
+         *        its own code.
+         */
+
+        /*
+         * Prevent idle completely if CAM is active.
+         * CAM does not have wakeup capability in OMAP3.
+         */
+        cam_state = pwrdm_read_pwrst(cam_pd);
+        if (cam_state == PWRDM_POWER_ON) {
+                new_state = dev->safe_state;
+                goto select_state;
+        }
+
+        /*
+         * Prevent PER off if CORE is not in retention or off as this
+         * would disable PER wakeups completely.
+         */
+        per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
+        if ((per_next_state == PWRDM_POWER_OFF) &&
+            (core_next_state > PWRDM_POWER_RET))
+                per_next_state = PWRDM_POWER_RET;
+
+        /* Are we changing PER target state? */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_next_state);
+
+select_state:
         dev->last_state = new_state;
-        return omap3_enter_idle(dev, new_state);
+        ret = omap3_enter_idle(dev, new_state);
+
+        /* Restore original PER state if it was modified */
+        if (per_next_state != per_saved_state)
+                pwrdm_set_next_pwrst(per_pd, per_saved_state);
+
+        return ret;
 }
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
@@ -328,7 +375,8 @@ void omap_init_power_states(void)
                         cpuidle_params_table[OMAP3_STATE_C2].threshold;
         omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
         omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
+        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
+                                CPUIDLE_FLAG_CHECK_BM;
 
         /* C3 . MPU CSWR + Core inactive */
         omap3_power_states[OMAP3_STATE_C3].valid =
@@ -426,6 +474,8 @@ int __init omap3_idle_init(void)
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
+        per_pd = pwrdm_lookup("per_pwrdm");
+        cam_pd = pwrdm_lookup("cam_pwrdm");
 
         omap_init_power_states();
         cpuidle_register_driver(&omap3_idle_driver);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c5cf1ba08a6f..5a0c148e23bc 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -9,12 +9,12 @@
  * (at your option) any later version.
  */
 
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -22,15 +22,17 @@
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include <plat/control.h>
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mcbsp.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
 #include "mux.h"
+#include "control.h"
 
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
@@ -538,7 +540,7 @@ static inline void omap_init_sham(void) { }
 
 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
 
-#ifdef CONFIG_ARCH_OMAP24XX
+#ifdef CONFIG_ARCH_OMAP2
 static struct resource omap2_aes_resources[] = {
         {
                 .start  = OMAP24XX_SEC_AES_BASE,
@@ -560,7 +562,7 @@ static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
 #define omap2_aes_resources_sz          0
 #endif
 
-#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_ARCH_OMAP3
 static struct resource omap3_aes_resources[] = {
         {
                 .start  = OMAP34XX_SEC_AES_BASE,
@@ -732,7 +734,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                 omap_mux_init_signal("sdmmc_dat0", 0);
                 omap_mux_init_signal("sdmmc_dat_dir0", 0);
                 omap_mux_init_signal("sdmmc_cmd_dir", 0);
-                if (mmc_controller->slots[0].wires == 4) {
+                if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
                         omap_mux_init_signal("sdmmc_dat1", 0);
                         omap_mux_init_signal("sdmmc_dat2", 0);
                         omap_mux_init_signal("sdmmc_dat3", 0);
@@ -760,8 +762,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 OMAP_PIN_INPUT_PULLUP);
                         omap_mux_init_signal("sdmmc1_dat0",
                                 OMAP_PIN_INPUT_PULLUP);
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                 omap_mux_init_signal("sdmmc1_dat1",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc1_dat2",
@@ -769,7 +771,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 omap_mux_init_signal("sdmmc1_dat3",
                                         OMAP_PIN_INPUT_PULLUP);
                         }
-                        if (mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                                MMC_CAP_8_BIT_DATA) {
                                 omap_mux_init_signal("sdmmc1_dat4",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc1_dat5",
@@ -793,8 +796,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
                          * in the board-*.c files
                          */
-                        if (mmc_controller->slots[0].wires == 4 ||
-                                mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
                                 omap_mux_init_signal("sdmmc2_dat1",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc2_dat2",
@@ -802,7 +805,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                                 omap_mux_init_signal("sdmmc2_dat3",
                                         OMAP_PIN_INPUT_PULLUP);
                         }
-                        if (mmc_controller->slots[0].wires == 8) {
+                        if (mmc_controller->slots[0].caps &
+                                                        MMC_CAP_8_BIT_DATA) {
                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
                                         OMAP_PIN_INPUT_PULLUP);
                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
@@ -853,13 +857,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                 case 3:
                         if (!cpu_is_omap44xx())
                                 return;
-                        base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
+                        base = OMAP4_MMC4_BASE;
                         irq = OMAP44XX_IRQ_MMC4;
                         break;
                 case 4:
                         if (!cpu_is_omap44xx())
                                 return;
-                        base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
+                        base = OMAP4_MMC5_BASE;
                         irq = OMAP44XX_IRQ_MMC5;
                         break;
                 default:
@@ -870,10 +874,8 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                         size = OMAP2420_MMC_SIZE;
                         name = "mmci-omap";
                 } else if (cpu_is_omap44xx()) {
-                        if (i < 3) {
-                                base += OMAP4_MMC_REG_OFFSET;
+                        if (i < 3)
                                 irq += OMAP44XX_IRQ_GIC_START;
-                        }
                         size = OMAP4_HSMMC_SIZE;
                         name = "mmci-omap-hs";
                 } else {
@@ -949,11 +951,72 @@ static inline void omap_init_vout(void) {}
 
 /*-------------------------------------------------------------------------*/
 
+/*
+ * Inorder to avoid any assumptions from bootloader regarding WDT
+ * settings, WDT module is reset during init. This enables the watchdog
+ * timer. Hence it is required to disable the watchdog after the WDT reset
+ * during init. Otherwise the system would reboot as per the default
+ * watchdog timer registers settings.
+ */
+#define OMAP_WDT_WPS    (0x34)
+#define OMAP_WDT_SPR    (0x48)
+
+static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
+{
+        void __iomem *base;
+        int ret;
+
+        if (!oh) {
+                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+                return -EINVAL;
+        }
+
+        base = omap_hwmod_get_mpu_rt_va(oh);
+        if (!base) {
+                pr_err("%s: Could not get the base address for %s\n",
+                                oh->name, __func__);
+                return -EINVAL;
+        }
+
+        /* Enable the clocks before accessing the WDT registers */
+        ret = omap_hwmod_enable(oh);
+        if (ret) {
+                pr_err("%s: Could not enable clocks for %s\n",
+                                oh->name, __func__);
+                return ret;
+        }
+
+        /* sequence required to disable watchdog */
+        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        __raw_writel(0x5555, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        ret = omap_hwmod_idle(oh);
+        if (ret)
+                pr_err("%s: Could not disable clocks for %s\n",
+                                oh->name, __func__);
+
+        return ret;
+}
+
+static void __init omap_disable_wdt(void)
+{
+        if (cpu_class_is_omap2())
+                omap_hwmod_for_each_by_class("wd_timer",
+                                                omap2_disable_wdt, NULL);
+        return;
+}
+
 static int __init omap2_init_devices(void)
 {
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
+        omap_disable_wdt();
         omap_hsmmc_reset();
         omap_init_audio();
         omap_init_camera();
@@ -969,3 +1032,39 @@ static int __init omap2_init_devices(void)
         return 0;
 }
 arch_initcall(omap2_init_devices);
+
+#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+struct omap_device_pm_latency omap_wdt_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static int __init omap_init_wdt(void)
+{
+        int id = -1;
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        char *oh_name = "wd_timer2";
+        char *dev_name = "omap_wdt";
+
+        if (!cpu_class_is_omap2())
+                return 0;
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up wd_timer%d hwmod\n", id);
+                return -EINVAL;
+        }
+
+        od = omap_device_build(dev_name, id, oh, NULL, 0,
+                                omap_wdt_latency,
+                                ARRAY_SIZE(omap_wdt_latency), 0);
+        WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
+                                dev_name, oh->name);
+        return 0;
+}
+subsys_initcall(omap_init_wdt);
+#endif
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
new file mode 100644
index 000000000000..703f150dd01d
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -0,0 +1,113 @@
+/*
+ * linux/arch/arm/mach-omap2/gpmc-smsc911x.c
+ *
+ * Copyright (C) 2009 Li-Pro.Net
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+
+#include <plat/board.h>
+#include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
+
+static struct omap_smsc911x_platform_data *gpmc_cfg;
+
+static struct resource gpmc_smsc911x_resources[] = {
+        [0] = {
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config gpmc_smsc911x_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT,
+};
+
+static struct platform_device gpmc_smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(gpmc_smsc911x_resources),
+        .resource       = gpmc_smsc911x_resources,
+        .dev            = {
+                .platform_data = &gpmc_smsc911x_config,
+        },
+};
+
+/*
+ * Initialize smsc911x device connected to the GPMC. Note that we
+ * assume that pin multiplexing is done in the board-*.c file,
+ * or in the bootloader.
+ */
+void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
+{
+        unsigned long cs_mem_base;
+        int ret;
+
+        gpmc_cfg = board_data;
+
+        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
+                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
+                return;
+        }
+
+        gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
+        gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
+
+        if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) {
+                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
+                                gpmc_cfg->gpio_irq);
+                goto free1;
+        }
+
+        gpio_direction_input(gpmc_cfg->gpio_irq);
+        gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
+        gpmc_smsc911x_resources[1].flags |=
+                                        (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
+
+        if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
+                ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset");
+                if (ret) {
+                        printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n",
+                                        gpmc_cfg->gpio_reset);
+                        goto free2;
+                }
+
+                gpio_direction_output(gpmc_cfg->gpio_reset, 1);
+                gpio_set_value(gpmc_cfg->gpio_reset, 0);
+                msleep(100);
+                gpio_set_value(gpmc_cfg->gpio_reset, 1);
+        }
+
+        if (platform_device_register(&gpmc_smsc911x_device) < 0) {
+                printk(KERN_ERR "Unable to register smsc911x device\n");
+                gpio_free(gpmc_cfg->gpio_reset);
+                goto free2;
+        }
+
+        return;
+
+free2:
+        gpio_free(gpmc_cfg->gpio_irq);
+free1:
+        gpmc_cs_free(gpmc_cfg->cs);
+
+        printk(KERN_ERR "Could not initialize smsc911x\n");
+}
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index c8f647b6205e..34272e4863fd 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,11 +14,11 @@
 #include <linux/string.h>
 #include <linux/delay.h>
 #include <mach/hardware.h>
-#include <plat/control.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
 
 #include "hsmmc.h"
+#include "control.h"
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
          *
          * FIXME handle VMMC1A as needed ...
          */
-        reg = omap_ctrl_readl(control_pbias_offset);
-        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                        OMAP4_USBC1_ICUSB_PWRDNZ);
-        omap_ctrl_writel(reg, control_pbias_offset);
+        reg = omap4_ctrl_pad_readl(control_pbias_offset);
+        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                OMAP4_MMC1_PWRDNZ_MASK |
+                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+        omap4_ctrl_pad_writel(reg, control_pbias_offset);
 }
 
 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
         u32 reg;
 
         if (power_on) {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ;
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
                 if ((1 << vdd) <= MMC_VDD_165_195)
-                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE;
+                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
                 else
-                        reg |= OMAP4_MMC1_PBIASLITE_VMODE;
-                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ |
-                                                OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
+                        reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
                 /* 4 microsec delay for comparator to generate an error*/
                 udelay(4);
-                reg = omap_ctrl_readl(control_pbias_offset);
-                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) {
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
                         pr_err("Pbias Voltage is not same as LDO\n");
                         /* Caution : On VMODE_ERROR Power Down MMC IO */
-                        reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ);
-                        omap_ctrl_writel(reg, control_pbias_offset);
+                        reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
+                                OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                        omap4_ctrl_pad_writel(reg, control_pbias_offset);
                 }
         } else {
-                reg = omap_ctrl_readl(control_pbias_offset);
-                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ |
-                        OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ |
-                        OMAP4_USBC1_ICUSB_PWRDNZ);
-                omap_ctrl_writel(reg, control_pbias_offset);
+                reg = omap4_ctrl_pad_readl(control_pbias_offset);
+                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
+                        OMAP4_MMC1_PWRDNZ_MASK |
+                        OMAP4_MMC1_PBIASLITE_VMODE_MASK |
+                        OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
+                omap4_ctrl_pad_writel(reg, control_pbias_offset);
         }
 }
 
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
                 }
         } else {
-                control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE;
-                control_mmc1 = OMAP44XX_CONTROL_MMC1;
-                reg = omap_ctrl_readl(control_mmc1);
-                reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1);
-                reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 |
-                        OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3);
-                reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL |
-                        OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL);
-                omap_ctrl_writel(reg, control_mmc1);
+                control_pbias_offset =
+                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
+                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
+                reg = omap4_ctrl_pad_readl(control_mmc1);
+                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
+                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
+                reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
+                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
+                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
+                omap4_ctrl_pad_writel(reg, control_mmc1);
         }
 
         for (c = controllers; c->mmc; c++) {
@@ -258,9 +263,13 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                                 "mmc%islot%i", c->mmc, 1);
                 mmc->slots[0].name = hc->name;
                 mmc->nr_slots = 1;
-                mmc->slots[0].wires = c->wires;
+                mmc->slots[0].caps = c->caps;
                 mmc->slots[0].internal_clock = !c->ext_clock;
                 mmc->dma_mask = 0xffffffff;
+                if (cpu_is_omap44xx())
+                        mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
+                else
+                        mmc->reg_offset = 0;
 
                 mmc->get_context_loss_count = hsmmc_get_context_loss;
 
@@ -298,6 +307,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                 else
                         mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
+                if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+                        mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+
                 switch (c->mmc) {
                 case 1:
                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
@@ -316,16 +328,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
                         }
 
                         /* Omap3630 HSMMC1 supports only 4-bit */
-                        if (cpu_is_omap3630() && c->wires > 4) {
-                                c->wires = 4;
-                                mmc->slots[0].wires = c->wires;
+                        if (cpu_is_omap3630() &&
+                                        (c->caps & MMC_CAP_8_BIT_DATA)) {
+                                c->caps &= ~MMC_CAP_8_BIT_DATA;
+                                c->caps |= MMC_CAP_4_BIT_DATA;
+                                mmc->slots[0].caps = c->caps;
                         }
                         break;
                 case 2:
                         if (c->ext_clock)
                                 c->transceiver = 1;
-                        if (c->transceiver && c->wires > 4)
-                                c->wires = 4;
+                        if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+                                c->caps &= ~MMC_CAP_8_BIT_DATA;
+                                c->caps |= MMC_CAP_4_BIT_DATA;
+                        }
                         /* FALLTHROUGH */
                 case 3:
                         if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 0f8a2e6ee284..f119348827d4 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -10,7 +10,8 @@ struct mmc_card;
 
 struct omap2_hsmmc_info {
         u8      mmc;            /* controller 1/2/3 */
-        u8      wires;          /* 1/4/8 wires */
+        u32     caps;           /* 4/8 wires and any additional host
+                                 * capabilities OR'd (ref. linux/mmc/host.h) */
         bool    transceiver;    /* MMC-2 option */
         bool    ext_clock;      /* use external pin for input clock */
         bool    cover_only;     /* No card detect - just cover switch */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9a879f959509..5f9086c65e48 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -22,11 +22,12 @@
 #include <asm/cputype.h>
 
 #include <plat/common.h>
-#include <plat/control.h>
 #include <plat/cpu.h>
 
 #include <mach/id.h>
 
+#include "control.h"
+
 static struct omap_chip_id omap_chip;
 static unsigned int omap_revision;
 
@@ -60,7 +61,7 @@ int omap_type(void)
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
-                val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
+                val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
         } else {
                 pr_err("Cannot detect omap type!\n");
                 goto out;
@@ -298,7 +299,6 @@ static void __init omap4_check_revision(void)
         u32 idcode;
         u16 hawkeye;
         u8 rev;
-        char *rev_name = "ES1.0";
 
         /*
          * The IC rev detection is done with hawkeye and rev.
@@ -309,14 +309,39 @@ static void __init omap4_check_revision(void)
         hawkeye = (idcode >> 12) & 0xffff;
         rev = (idcode >> 28) & 0xff;
 
-        if ((hawkeye == 0xb852) && (rev == 0x0)) {
-                omap_revision = OMAP4430_REV_ES1_0;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES1;
-                pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
-                return;
+        /*
+         * Few initial ES2.0 samples IDCODE is same as ES1.0
+         * Use ARM register to detect the correct ES version
+         */
+        if (!rev) {
+                idcode = read_cpuid(CPUID_ID);
+                rev = (idcode & 0xf) - 1;
+        }
+
+        switch (hawkeye) {
+        case 0xb852:
+                switch (rev) {
+                case 0:
+                        omap_revision = OMAP4430_REV_ES1_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+                        break;
+                case 1:
+                        omap_revision = OMAP4430_REV_ES2_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                        break;
+                default:
+                        omap_revision = OMAP4430_REV_ES2_0;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+        }
+        break;
+        default:
+                /* Unknown default to latest silicon rev as default*/
+                omap_revision = OMAP4430_REV_ES2_0;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES2;
         }
 
-        pr_err("Unknown OMAP4 CPU id\n");
+        pr_info("OMAP%04x ES%d.0\n",
+                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
 }
 
 #define OMAP3_SHOW_FEATURE(feat)                \
@@ -361,30 +386,54 @@ static void __init omap3_cpuinfo(void)
                 strcpy(cpu_name, "OMAP3503");
         }
 
-        switch (rev) {
-        case OMAP_REVBITS_00:
-                strcpy(cpu_rev, "1.0");
-                break;
-        case OMAP_REVBITS_01:
-                strcpy(cpu_rev, "1.1");
-                break;
-        case OMAP_REVBITS_02:
-                strcpy(cpu_rev, "1.2");
-                break;
-        case OMAP_REVBITS_10:
-                strcpy(cpu_rev, "2.0");
-                break;
-        case OMAP_REVBITS_20:
-                strcpy(cpu_rev, "2.1");
-                break;
-        case OMAP_REVBITS_30:
-                strcpy(cpu_rev, "3.0");
-                break;
-        case OMAP_REVBITS_40:
-        /* FALLTHROUGH */
-        default:
-                /* Use the latest known revision as default */
-                strcpy(cpu_rev, "3.1");
+        if (cpu_is_omap3630()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "1.1");
+                        break;
+                case OMAP_REVBITS_02:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.2");
+                }
+        } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "1.1");
+                }
+        } else {
+                switch (rev) {
+                case OMAP_REVBITS_00:
+                        strcpy(cpu_rev, "1.0");
+                        break;
+                case OMAP_REVBITS_01:
+                        strcpy(cpu_rev, "2.0");
+                        break;
+                case OMAP_REVBITS_02:
+                        strcpy(cpu_rev, "2.1");
+                        break;
+                case OMAP_REVBITS_03:
+                        strcpy(cpu_rev, "3.0");
+                        break;
+                case OMAP_REVBITS_04:
+                        strcpy(cpu_rev, "3.1");
+                        break;
+                case OMAP_REVBITS_05:
+                        /* FALLTHROUGH */
+                default:
+                        /* Use the latest known revision as default */
+                        strcpy(cpu_rev, "3.1.2");
+                }
         }
 
         /* Print verbose information */
diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h
new file mode 100644
index 000000000000..b76f49e7eed5
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-rx51.h
@@ -0,0 +1,11 @@
+/*
+ * Defines for rx51 boards
+ */
+
+#ifndef _OMAP_BOARD_RX51_H
+#define _OMAP_BOARD_RX51_H
+
+extern void __init rx51_peripherals_init(void);
+extern void __init rx51_video_mem_init(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index 80591fda8f8f..f93ca3928c3b 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,12 +1,8 @@
 /*
  * Defines for zoom boards
  */
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-
 #define ZOOM_NAND_CS    0
 
-extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs);
 extern int __init zoom_debugboard_init(void);
 extern void __init zoom_peripherals_init(void);
 
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 000000000000..2f7ac70a20d8
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
+/*
+ * OMAP44xx CTRL_MODULE_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_CORE                                  0x4a002000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_CORE_IP_REVISION                      0x0000
+#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO                        0x0004
+#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG                     0x0010
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0                0x0200
+#define OMAP4_CTRL_MODULE_CORE_ID_CODE                          0x0204
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1                0x0208
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2                0x020c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3                0x0210
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0               0x0214
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1               0x0218
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF                0x021c
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP            0x0228
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP                0x0260
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0              0x0264
+#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
+#define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
+#define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
+#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL         0x0324
+#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL        0x0328
+#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR                      0x032c
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0                0x0330
+#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1                0x0334
+#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL                 0x033c
+#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL                      0x0340
+#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL                    0x0350
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL             0x0400
+#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU                   0x0408
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0               0x042c
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1               0x0430
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2               0x0434
+#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3               0x0438
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0                    0x0440
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1                    0x0444
+#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2                    0x0448
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL           0x044c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL             0x0450
+#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL          0x0454
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0             0x0480
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1             0x0484
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2             0x0488
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3             0x048c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4             0x0490
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5             0x0494
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6             0x0498
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7             0x049c
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8             0x04a0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9             0x04a4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10            0x04a8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11            0x04ac
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12            0x04b0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13            0x04b4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14            0x04b8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15            0x04bc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16            0x04c0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17            0x04c4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18            0x04c8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19            0x04cc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20            0x04d0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21            0x04d4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22            0x04d8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23            0x04dc
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24            0x04e0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25            0x04e4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26            0x04e8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27            0x04ec
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28            0x04f0
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29            0x04f4
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30            0x04f8
+#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31            0x04fc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                       30
+#define OMAP4_IP_REV_SCHEME_MASK                        (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                         16
+#define OMAP4_IP_REV_FUNC_MASK                          (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                          11
+#define OMAP4_IP_REV_RTL_MASK                           (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                        8
+#define OMAP4_IP_REV_MAJOR_MASK                         (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                       6
+#define OMAP4_IP_REV_CUSTOM_MASK                        (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                        0
+#define OMAP4_IP_REV_MINOR_MASK                         (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                           0
+#define OMAP4_IP_HWINFO_MASK                            (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT               2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                (0x3 << 2)
+
+/* STD_FUSE_DIE_ID_0 */
+#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_0_MASK                    (0xffffffff << 0)
+
+/* ID_CODE */
+#define OMAP4_STD_FUSE_IDCODE_SHIFT                     0
+#define OMAP4_STD_FUSE_IDCODE_MASK                      (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_1 */
+#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_1_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_2 */
+#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_2_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_DIE_ID_3 */
+#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT                   0
+#define OMAP4_STD_FUSE_DIE_ID_3_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_0 */
+#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_0_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_PROD_ID_1 */
+#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT                  0
+#define OMAP4_STD_FUSE_PROD_ID_1_MASK                   (0xffffffff << 0)
+
+/* STD_FUSE_USB_CONF */
+#define OMAP4_USB_PROD_ID_SHIFT                         16
+#define OMAP4_USB_PROD_ID_MASK                          (0xffff << 16)
+#define OMAP4_USB_VENDOR_ID_SHIFT                       0
+#define OMAP4_USB_VENDOR_ID_MASK                        (0xffff << 0)
+
+/* STD_FUSE_OPP_VDD_WKUP */
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT               0
+#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK                (0xffffffff << 0)
+
+/* STD_FUSE_OPP_BGAP */
+#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT                   0
+#define OMAP4_STD_FUSE_OPP_BGAP_MASK                    (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_0 */
+#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK                  (0xffffffff << 0)
+
+/* STD_FUSE_OPP_DPLL_1 */
+#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT                 0
+#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK                  (0xffffffff << 0)
+
+/* STATUS */
+#define OMAP4_ATTILA_CONF_SHIFT                         11
+#define OMAP4_ATTILA_CONF_MASK                          (0x3 << 11)
+#define OMAP4_DEVICE_TYPE_SHIFT                         8
+#define OMAP4_DEVICE_TYPE_MASK                          (0x7 << 8)
+#define OMAP4_SYS_BOOT_SHIFT                            0
+#define OMAP4_SYS_BOOT_MASK                             (0xff << 0)
+
+/* DEV_CONF */
+#define OMAP4_DEV_CONF_SHIFT                            1
+#define OMAP4_DEV_CONF_MASK                             (0x7fffffff << 1)
+#define OMAP4_USBPHY_PD_SHIFT                           0
+#define OMAP4_USBPHY_PD_MASK                            (1 << 0)
+
+/* LDOVBB_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOVBB_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT              26
+#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK               (1 << 26)
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT               21
+#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK                (0x1f << 21)
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT              16
+#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK               (0x1f << 16)
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT              10
+#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK               (1 << 10)
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT               5
+#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK                (0x1f << 5)
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT              0
+#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK               (0x1f << 0)
+
+/* LDOSRAM_IVA_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_MPU_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT         26
+#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK          (1 << 26)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT          21
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK           (0x1f << 21)
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT         16
+#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK          (0x1f << 16)
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT         10
+#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK          (1 << 10)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT          5
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK           (0x1f << 5)
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT         0
+#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK          (0x1f << 0)
+
+/* LDOSRAM_CORE_VOLTAGE_CTRL */
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT        26
+#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK         (1 << 26)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT         21
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK          (0x1f << 21)
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT        16
+#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK         (0x1f << 16)
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT        10
+#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK         (1 << 10)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT         5
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK          (0x1f << 5)
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT        0
+#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK         (0x1f << 0)
+
+/* TEMP_SENSOR */
+#define OMAP4_BGAP_TEMPSOFF_SHIFT                       12
+#define OMAP4_BGAP_TEMPSOFF_MASK                        (1 << 12)
+#define OMAP4_BGAP_TSHUT_SHIFT                          11
+#define OMAP4_BGAP_TSHUT_MASK                           (1 << 11)
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT           10
+#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK            (1 << 10)
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT                9
+#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK                 (1 << 9)
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT               8
+#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK                (1 << 8)
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT              0
+#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK               (0xff << 0)
+
+/* DPLL_NWELL_TRIM_0 */
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT        29
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK         (1 << 29)
+#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT                 24
+#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK                  (0x1f << 24)
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_PER_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT        11
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK         (1 << 11)
+#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT                 6
+#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK                  (0x1f << 6)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT        5
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK         (1 << 5)
+#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT                 0
+#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK                  (0x1f << 0)
+
+/* DPLL_NWELL_TRIM_1 */
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT     29
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK      (1 << 29)
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT              24
+#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK               (0x1f << 24)
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT        23
+#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK         (1 << 23)
+#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT                 18
+#define OMAP4_DPLL_USB_NWELL_TRIM_MASK                  (0x1f << 18)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT       17
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK        (1 << 17)
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT                12
+#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK                 (0x1f << 12)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT       11
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK        (1 << 11)
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT                6
+#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK                 (0x1f << 6)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT       5
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK        (1 << 5)
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT                0
+#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK                 (0x1f << 0)
+
+/* USBOTGHS_CONTROL */
+#define OMAP4_DISCHRGVBUS_SHIFT                         8
+#define OMAP4_DISCHRGVBUS_MASK                          (1 << 8)
+#define OMAP4_CHRGVBUS_SHIFT                            7
+#define OMAP4_CHRGVBUS_MASK                             (1 << 7)
+#define OMAP4_DRVVBUS_SHIFT                             6
+#define OMAP4_DRVVBUS_MASK                              (1 << 6)
+#define OMAP4_IDPULLUP_SHIFT                            5
+#define OMAP4_IDPULLUP_MASK                             (1 << 5)
+#define OMAP4_IDDIG_SHIFT                               4
+#define OMAP4_IDDIG_MASK                                (1 << 4)
+#define OMAP4_SESSEND_SHIFT                             3
+#define OMAP4_SESSEND_MASK                              (1 << 3)
+#define OMAP4_VBUSVALID_SHIFT                           2
+#define OMAP4_VBUSVALID_MASK                            (1 << 2)
+#define OMAP4_BVALID_SHIFT                              1
+#define OMAP4_BVALID_MASK                               (1 << 1)
+#define OMAP4_AVALID_SHIFT                              0
+#define OMAP4_AVALID_MASK                               (1 << 0)
+
+/* DSS_CONTROL */
+#define OMAP4_DSS_MUX6_SELECT_SHIFT                     0
+#define OMAP4_DSS_MUX6_SELECT_MASK                      (1 << 0)
+
+/* HWOBS_CONTROL */
+#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT                    3
+#define OMAP4_HWOBS_CLKDIV_SEL_MASK                     (0x1f << 3)
+#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT                 2
+#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK                  (1 << 2)
+#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT                  1
+#define OMAP4_HWOBS_ALL_ONE_MODE_MASK                   (1 << 1)
+#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT                  0
+#define OMAP4_HWOBS_MACRO_ENABLE_MASK                   (1 << 0)
+
+/* DEBOBS_FINAL_MUX_SEL */
+#define OMAP4_SELECT_SHIFT                              0
+#define OMAP4_SELECT_MASK                               (0xffffffff << 0)
+
+/* DEBOBS_MMR_MPU */
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT               0
+#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK                (0xf << 0)
+
+/* CONF_SDMA_REQ_SEL0 */
+#define OMAP4_MULT_SHIFT                                0
+#define OMAP4_MULT_MASK                                 (0x7f << 0)
+
+/* CONF_CLK_SEL0 */
+#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL0_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL1 */
+#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL1_MASK                   (0x7 << 0)
+
+/* CONF_CLK_SEL2 */
+#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT                  0
+#define OMAP4_MULT_CONF_CLK_SEL2_MASK                   (0x7 << 0)
+
+/* CONF_DPLL_FREQLOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT         0
+#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK          (0x7 << 0)
+
+/* CONF_DPLL_TINITZ_SEL */
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT           0
+#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK            (0x7 << 0)
+
+/* CONF_DPLL_PHASELOCK_SEL */
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT        0
+#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK         (0x7 << 0)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_MODE_SHIFT                                0
+#define OMAP4_MODE_MASK                                 (0xf << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 000000000000..c88420de1151
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE                              0x4a100000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION                  0x0000
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO                    0x0004
+#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG                 0x0010
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0        0x01d8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1        0x01dc
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2        0x01e0
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3        0x01e4
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4        0x01e8
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5        0x01ec
+#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6        0x01f0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE         0x05a4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0   0x05a8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1   0x05ac
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0   0x05b0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1   0x05b4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0   0x05b8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1   0x05bc
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2   0x05c0
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC            0x05c4
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS              0x05c8
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE            0x0600
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0                0x0604
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX            0x0608
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC                0x060c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY          0x0610
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2                 0x0614
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY               0x0618
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP              0x061c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE          0x0620
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1                0x0624
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1                 0x0628
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI                  0x062c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB                  0x0630
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ                  0x0634
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0          0x0638
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1          0x063c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2          0x0640
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3          0x0644
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0          0x0648
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1          0x064c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2          0x0650
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3          0x0654
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD             0x0658
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C                  0x065c
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW        0x0660
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R         0x0664
+#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0      0x0668
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1              0x0700
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2              0x0704
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3              0x0708
+#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4              0x070c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT               31
+#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK                (1 << 31)
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT               30
+#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK                (1 << 30)
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT               16
+#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK                (1 << 16)
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT              11
+#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK               (1 << 11)
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT              10
+#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK               (1 << 10)
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT               9
+#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK                (1 << 9)
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT               8
+#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK                (1 << 8)
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT               6
+#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK                (1 << 6)
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT               5
+#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK                (1 << 5)
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT               4
+#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK                (1 << 4)
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT               3
+#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK                (1 << 3)
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT               0
+#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK                (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_1 */
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT            30
+#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK             (1 << 30)
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT              29
+#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 29)
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT              28
+#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 28)
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT              27
+#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 27)
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT              26
+#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 26)
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT              25
+#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK               (1 << 25)
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT              24
+#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK               (1 << 24)
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT              23
+#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK               (1 << 23)
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT              22
+#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK               (1 << 22)
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT              20
+#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK               (1 << 20)
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT           15
+#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK            (1 << 15)
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT               13
+#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK                (1 << 13)
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT               12
+#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK                (1 << 12)
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT             11
+#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK              (1 << 11)
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT               2
+#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK                (1 << 2)
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT               1
+#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK                (1 << 1)
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_2 */
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        31
+#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 31)
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT         30
+#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 30)
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT          29
+#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 29)
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT          28
+#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 28)
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT        27
+#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK         (1 << 27)
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT            25
+#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK             (1 << 25)
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT            24
+#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK             (1 << 24)
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT            23
+#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK             (1 << 23)
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            22
+#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 22)
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            21
+#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 21)
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            20
+#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 20)
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            19
+#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 19)
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT             18
+#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 18)
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             17
+#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 17)
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT         16
+#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK          (1 << 16)
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT         15
+#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK          (1 << 15)
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      14
+#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 14)
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        13
+#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 13)
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     12
+#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 12)
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     11
+#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 11)
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     10
+#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 10)
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     9
+#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 9)
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     8
+#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 8)
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     7
+#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 7)
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     6
+#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 6)
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     5
+#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 5)
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      4
+#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 4)
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      3
+#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 3)
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      2
+#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 2)
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      1
+#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 1)
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT        0
+#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK         (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_3 */
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT             29
+#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK              (1 << 29)
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT             28
+#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 28)
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            27
+#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 27)
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            26
+#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 26)
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT             25
+#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 25)
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT               19
+#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 19)
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT               18
+#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK                (1 << 18)
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT               17
+#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK                (1 << 17)
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT                16
+#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK                 (1 << 16)
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT               7
+#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK                (1 << 7)
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT         6
+#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK          (1 << 6)
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT          5
+#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK           (1 << 5)
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        4
+#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 4)
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT        3
+#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 3)
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT         2
+#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK          (1 << 2)
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT          1
+#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK           (1 << 1)
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT          0
+#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK           (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_4 */
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT             31
+#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 31)
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT             30
+#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 30)
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT      29
+#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK       (1 << 29)
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT        28
+#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK         (1 << 28)
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT     27
+#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK      (1 << 27)
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT     26
+#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK      (1 << 26)
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT     25
+#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK      (1 << 25)
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT     24
+#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK      (1 << 24)
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT     23
+#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK      (1 << 23)
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT     22
+#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK      (1 << 22)
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT     21
+#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK      (1 << 21)
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT     20
+#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK      (1 << 20)
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT      19
+#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK       (1 << 19)
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT      18
+#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK       (1 << 18)
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT      17
+#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK       (1 << 17)
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT      16
+#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK       (1 << 16)
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT               15
+#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK                (1 << 15)
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT               14
+#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK                (1 << 14)
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT             13
+#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK              (1 << 13)
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT            12
+#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK             (1 << 12)
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT            11
+#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK             (1 << 11)
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT             10
+#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 10)
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT            9
+#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK             (1 << 9)
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT            8
+#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK             (1 << 8)
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT            7
+#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK             (1 << 7)
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT            6
+#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK             (1 << 6)
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT          3
+#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK           (1 << 3)
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT          2
+#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK           (1 << 2)
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT           1
+#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK            (1 << 1)
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT         0
+#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK          (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_5 */
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT              31
+#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK               (1 << 31)
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT              30
+#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK               (1 << 30)
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT               29
+#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK                (1 << 29)
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT               28
+#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK                (1 << 28)
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT               27
+#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK                (1 << 27)
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT               26
+#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK                (1 << 26)
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT               25
+#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK                (1 << 25)
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT               22
+#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK                (1 << 22)
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT               21
+#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK                (1 << 21)
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT              19
+#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK               (1 << 19)
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT              16
+#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK               (1 << 16)
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT              15
+#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK               (1 << 15)
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT              14
+#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK               (1 << 14)
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT              13
+#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK               (1 << 13)
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT              12
+#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK               (1 << 12)
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT             9
+#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 9)
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT             8
+#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 8)
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT             7
+#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 7)
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT             6
+#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 6)
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT             5
+#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK              (1 << 5)
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT             4
+#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK              (1 << 4)
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT             3
+#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK              (1 << 3)
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT             2
+#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK              (1 << 2)
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT             1
+#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK              (1 << 1)
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT             0
+#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK              (1 << 0)
+
+/* PADCONF_WAKEUPEVENT_6 */
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT              7
+#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK               (1 << 7)
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT              6
+#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK               (1 << 6)
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT              5
+#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK               (1 << 5)
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT              4
+#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK               (1 << 4)
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT              3
+#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK               (1 << 3)
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT              1
+#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK               (1 << 1)
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT              0
+#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK               (1 << 0)
+
+/* CONTROL_PADCONF_GLOBAL */
+#define OMAP4_FORCE_OFFMODE_EN_SHIFT                            31
+#define OMAP4_FORCE_OFFMODE_EN_MASK                             (1 << 31)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_BANK0_SHIFT                               31
+#define OMAP4_VDDS_DV_BANK0_MASK                                (1 << 31)
+#define OMAP4_VDDS_DV_BANK1_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK1_MASK                                (1 << 30)
+#define OMAP4_VDDS_DV_BANK3_SHIFT                               29
+#define OMAP4_VDDS_DV_BANK3_MASK                                (1 << 29)
+#define OMAP4_VDDS_DV_BANK4_SHIFT                               28
+#define OMAP4_VDDS_DV_BANK4_MASK                                (1 << 28)
+#define OMAP4_VDDS_DV_BANK5_SHIFT                               27
+#define OMAP4_VDDS_DV_BANK5_MASK                                (1 << 27)
+#define OMAP4_VDDS_DV_BANK6_SHIFT                               26
+#define OMAP4_VDDS_DV_BANK6_MASK                                (1 << 26)
+#define OMAP4_VDDS_DV_C2C_SHIFT                                 25
+#define OMAP4_VDDS_DV_C2C_MASK                                  (1 << 25)
+#define OMAP4_VDDS_DV_CAM_SHIFT                                 24
+#define OMAP4_VDDS_DV_CAM_MASK                                  (1 << 24)
+#define OMAP4_VDDS_DV_GPMC_SHIFT                                23
+#define OMAP4_VDDS_DV_GPMC_MASK                                 (1 << 23)
+#define OMAP4_VDDS_DV_SDMMC2_SHIFT                              22
+#define OMAP4_VDDS_DV_SDMMC2_MASK                               (1 << 22)
+
+/* CONTROL_SMART1IO_PADCONF_0 */
+#define OMAP4_ABE_DR0_SC_SHIFT                                  30
+#define OMAP4_ABE_DR0_SC_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_SC_SHIFT                                  28
+#define OMAP4_CAM_DR0_SC_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_SC_SHIFT                                 26
+#define OMAP4_FREF_DR2_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_SC_SHIFT                                 24
+#define OMAP4_FREF_DR3_SC_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_SC_SHIFT                                 22
+#define OMAP4_GPIO_DR8_SC_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_SC_SHIFT                                 20
+#define OMAP4_GPIO_DR9_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_SC_SHIFT                                 18
+#define OMAP4_GPMC_DR2_SC_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_SC_SHIFT                                 16
+#define OMAP4_GPMC_DR3_SC_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_SC_SHIFT                                 14
+#define OMAP4_GPMC_DR6_SC_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_SC_SHIFT                                 12
+#define OMAP4_HDMI_DR0_SC_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_SC_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_SC_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_SC_SHIFT                                8
+#define OMAP4_UART1_DR0_SC_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_SC_SHIFT                                6
+#define OMAP4_UART3_DR0_SC_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_SC_SHIFT                                4
+#define OMAP4_UART3_DR1_SC_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_SC_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_SC_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_SC_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_SC_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART1IO_PADCONF_1 */
+#define OMAP4_ABE_DR0_LB_SHIFT                                  30
+#define OMAP4_ABE_DR0_LB_MASK                                   (0x3 << 30)
+#define OMAP4_CAM_DR0_LB_SHIFT                                  28
+#define OMAP4_CAM_DR0_LB_MASK                                   (0x3 << 28)
+#define OMAP4_FREF_DR2_LB_SHIFT                                 26
+#define OMAP4_FREF_DR2_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR3_LB_SHIFT                                 24
+#define OMAP4_FREF_DR3_LB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR8_LB_SHIFT                                 22
+#define OMAP4_GPIO_DR8_LB_MASK                                  (0x3 << 22)
+#define OMAP4_GPIO_DR9_LB_SHIFT                                 20
+#define OMAP4_GPIO_DR9_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPMC_DR2_LB_SHIFT                                 18
+#define OMAP4_GPMC_DR2_LB_MASK                                  (0x3 << 18)
+#define OMAP4_GPMC_DR3_LB_SHIFT                                 16
+#define OMAP4_GPMC_DR3_LB_MASK                                  (0x3 << 16)
+#define OMAP4_GPMC_DR6_LB_SHIFT                                 14
+#define OMAP4_GPMC_DR6_LB_MASK                                  (0x3 << 14)
+#define OMAP4_HDMI_DR0_LB_SHIFT                                 12
+#define OMAP4_HDMI_DR0_LB_MASK                                  (0x3 << 12)
+#define OMAP4_MCSPI1_DR0_LB_SHIFT                               10
+#define OMAP4_MCSPI1_DR0_LB_MASK                                (0x3 << 10)
+#define OMAP4_UART1_DR0_LB_SHIFT                                8
+#define OMAP4_UART1_DR0_LB_MASK                                 (0x3 << 8)
+#define OMAP4_UART3_DR0_LB_SHIFT                                6
+#define OMAP4_UART3_DR0_LB_MASK                                 (0x3 << 6)
+#define OMAP4_UART3_DR1_LB_SHIFT                                4
+#define OMAP4_UART3_DR1_LB_MASK                                 (0x3 << 4)
+#define OMAP4_UNIPRO_DR0_LB_SHIFT                               2
+#define OMAP4_UNIPRO_DR0_LB_MASK                                (0x3 << 2)
+#define OMAP4_UNIPRO_DR1_LB_SHIFT                               0
+#define OMAP4_UNIPRO_DR1_LB_MASK                                (0x3 << 0)
+
+/* CONTROL_SMART2IO_PADCONF_0 */
+#define OMAP4_C2C_DR0_LB_SHIFT                                  31
+#define OMAP4_C2C_DR0_LB_MASK                                   (1 << 31)
+#define OMAP4_DPM_DR1_LB_SHIFT                                  30
+#define OMAP4_DPM_DR1_LB_MASK                                   (1 << 30)
+#define OMAP4_DPM_DR2_LB_SHIFT                                  29
+#define OMAP4_DPM_DR2_LB_MASK                                   (1 << 29)
+#define OMAP4_DPM_DR3_LB_SHIFT                                  28
+#define OMAP4_DPM_DR3_LB_MASK                                   (1 << 28)
+#define OMAP4_GPIO_DR0_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR0_LB_MASK                                  (1 << 27)
+#define OMAP4_GPIO_DR1_LB_SHIFT                                 26
+#define OMAP4_GPIO_DR1_LB_MASK                                  (1 << 26)
+#define OMAP4_GPIO_DR10_LB_SHIFT                                25
+#define OMAP4_GPIO_DR10_LB_MASK                                 (1 << 25)
+#define OMAP4_GPIO_DR2_LB_SHIFT                                 24
+#define OMAP4_GPIO_DR2_LB_MASK                                  (1 << 24)
+#define OMAP4_GPMC_DR0_LB_SHIFT                                 23
+#define OMAP4_GPMC_DR0_LB_MASK                                  (1 << 23)
+#define OMAP4_GPMC_DR1_LB_SHIFT                                 22
+#define OMAP4_GPMC_DR1_LB_MASK                                  (1 << 22)
+#define OMAP4_GPMC_DR4_LB_SHIFT                                 21
+#define OMAP4_GPMC_DR4_LB_MASK                                  (1 << 21)
+#define OMAP4_GPMC_DR5_LB_SHIFT                                 20
+#define OMAP4_GPMC_DR5_LB_MASK                                  (1 << 20)
+#define OMAP4_GPMC_DR7_LB_SHIFT                                 19
+#define OMAP4_GPMC_DR7_LB_MASK                                  (1 << 19)
+#define OMAP4_HSI2_DR0_LB_SHIFT                                 18
+#define OMAP4_HSI2_DR0_LB_MASK                                  (1 << 18)
+#define OMAP4_HSI2_DR1_LB_SHIFT                                 17
+#define OMAP4_HSI2_DR1_LB_MASK                                  (1 << 17)
+#define OMAP4_HSI2_DR2_LB_SHIFT                                 16
+#define OMAP4_HSI2_DR2_LB_MASK                                  (1 << 16)
+#define OMAP4_KPD_DR0_LB_SHIFT                                  15
+#define OMAP4_KPD_DR0_LB_MASK                                   (1 << 15)
+#define OMAP4_KPD_DR1_LB_SHIFT                                  14
+#define OMAP4_KPD_DR1_LB_MASK                                   (1 << 14)
+#define OMAP4_PDM_DR0_LB_SHIFT                                  13
+#define OMAP4_PDM_DR0_LB_MASK                                   (1 << 13)
+#define OMAP4_SDMMC2_DR0_LB_SHIFT                               12
+#define OMAP4_SDMMC2_DR0_LB_MASK                                (1 << 12)
+#define OMAP4_SDMMC3_DR0_LB_SHIFT                               11
+#define OMAP4_SDMMC3_DR0_LB_MASK                                (1 << 11)
+#define OMAP4_SDMMC4_DR0_LB_SHIFT                               10
+#define OMAP4_SDMMC4_DR0_LB_MASK                                (1 << 10)
+#define OMAP4_SDMMC4_DR1_LB_SHIFT                               9
+#define OMAP4_SDMMC4_DR1_LB_MASK                                (1 << 9)
+#define OMAP4_SPI3_DR0_LB_SHIFT                                 8
+#define OMAP4_SPI3_DR0_LB_MASK                                  (1 << 8)
+#define OMAP4_SPI3_DR1_LB_SHIFT                                 7
+#define OMAP4_SPI3_DR1_LB_MASK                                  (1 << 7)
+#define OMAP4_UART3_DR2_LB_SHIFT                                6
+#define OMAP4_UART3_DR2_LB_MASK                                 (1 << 6)
+#define OMAP4_UART3_DR3_LB_SHIFT                                5
+#define OMAP4_UART3_DR3_LB_MASK                                 (1 << 5)
+#define OMAP4_UART3_DR4_LB_SHIFT                                4
+#define OMAP4_UART3_DR4_LB_MASK                                 (1 << 4)
+#define OMAP4_UART3_DR5_LB_SHIFT                                3
+#define OMAP4_UART3_DR5_LB_MASK                                 (1 << 3)
+#define OMAP4_USBA0_DR1_LB_SHIFT                                2
+#define OMAP4_USBA0_DR1_LB_MASK                                 (1 << 2)
+#define OMAP4_USBA_DR2_LB_SHIFT                                 1
+#define OMAP4_USBA_DR2_LB_MASK                                  (1 << 1)
+
+/* CONTROL_SMART2IO_PADCONF_1 */
+#define OMAP4_USBB1_DR0_LB_SHIFT                                31
+#define OMAP4_USBB1_DR0_LB_MASK                                 (1 << 31)
+#define OMAP4_USBB2_DR0_LB_SHIFT                                30
+#define OMAP4_USBB2_DR0_LB_MASK                                 (1 << 30)
+#define OMAP4_USBA0_DR0_LB_SHIFT                                29
+#define OMAP4_USBA0_DR0_LB_MASK                                 (1 << 29)
+
+/* CONTROL_SMART3IO_PADCONF_0 */
+#define OMAP4_DMIC_DR0_MB_SHIFT                                 30
+#define OMAP4_DMIC_DR0_MB_MASK                                  (0x3 << 30)
+#define OMAP4_GPIO_DR3_MB_SHIFT                                 28
+#define OMAP4_GPIO_DR3_MB_MASK                                  (0x3 << 28)
+#define OMAP4_GPIO_DR4_MB_SHIFT                                 26
+#define OMAP4_GPIO_DR4_MB_MASK                                  (0x3 << 26)
+#define OMAP4_GPIO_DR5_MB_SHIFT                                 24
+#define OMAP4_GPIO_DR5_MB_MASK                                  (0x3 << 24)
+#define OMAP4_GPIO_DR6_MB_SHIFT                                 22
+#define OMAP4_GPIO_DR6_MB_MASK                                  (0x3 << 22)
+#define OMAP4_HSI_DR1_MB_SHIFT                                  20
+#define OMAP4_HSI_DR1_MB_MASK                                   (0x3 << 20)
+#define OMAP4_HSI_DR2_MB_SHIFT                                  18
+#define OMAP4_HSI_DR2_MB_MASK                                   (0x3 << 18)
+#define OMAP4_HSI_DR3_MB_SHIFT                                  16
+#define OMAP4_HSI_DR3_MB_MASK                                   (0x3 << 16)
+#define OMAP4_MCBSP2_DR0_MB_SHIFT                               14
+#define OMAP4_MCBSP2_DR0_MB_MASK                                (0x3 << 14)
+#define OMAP4_MCSPI4_DR0_MB_SHIFT                               12
+#define OMAP4_MCSPI4_DR0_MB_MASK                                (0x3 << 12)
+#define OMAP4_MCSPI4_DR1_MB_SHIFT                               10
+#define OMAP4_MCSPI4_DR1_MB_MASK                                (0x3 << 10)
+#define OMAP4_SDMMC3_DR0_MB_SHIFT                               8
+#define OMAP4_SDMMC3_DR0_MB_MASK                                (0x3 << 8)
+#define OMAP4_SPI2_DR0_MB_SHIFT                                 0
+#define OMAP4_SPI2_DR0_MB_MASK                                  (0x3 << 0)
+
+/* CONTROL_SMART3IO_PADCONF_1 */
+#define OMAP4_SPI2_DR1_MB_SHIFT                                 30
+#define OMAP4_SPI2_DR1_MB_MASK                                  (0x3 << 30)
+#define OMAP4_SPI2_DR2_MB_SHIFT                                 28
+#define OMAP4_SPI2_DR2_MB_MASK                                  (0x3 << 28)
+#define OMAP4_UART2_DR0_MB_SHIFT                                26
+#define OMAP4_UART2_DR0_MB_MASK                                 (0x3 << 26)
+#define OMAP4_UART2_DR1_MB_SHIFT                                24
+#define OMAP4_UART2_DR1_MB_MASK                                 (0x3 << 24)
+#define OMAP4_UART4_DR0_MB_SHIFT                                22
+#define OMAP4_UART4_DR0_MB_MASK                                 (0x3 << 22)
+#define OMAP4_HSI_DR0_MB_SHIFT                                  20
+#define OMAP4_HSI_DR0_MB_MASK                                   (0x3 << 20)
+
+/* CONTROL_SMART3IO_PADCONF_2 */
+#define OMAP4_DMIC_DR0_LB_SHIFT                                 31
+#define OMAP4_DMIC_DR0_LB_MASK                                  (1 << 31)
+#define OMAP4_GPIO_DR3_LB_SHIFT                                 30
+#define OMAP4_GPIO_DR3_LB_MASK                                  (1 << 30)
+#define OMAP4_GPIO_DR4_LB_SHIFT                                 29
+#define OMAP4_GPIO_DR4_LB_MASK                                  (1 << 29)
+#define OMAP4_GPIO_DR5_LB_SHIFT                                 28
+#define OMAP4_GPIO_DR5_LB_MASK                                  (1 << 28)
+#define OMAP4_GPIO_DR6_LB_SHIFT                                 27
+#define OMAP4_GPIO_DR6_LB_MASK                                  (1 << 27)
+#define OMAP4_HSI_DR1_LB_SHIFT                                  26
+#define OMAP4_HSI_DR1_LB_MASK                                   (1 << 26)
+#define OMAP4_HSI_DR2_LB_SHIFT                                  25
+#define OMAP4_HSI_DR2_LB_MASK                                   (1 << 25)
+#define OMAP4_HSI_DR3_LB_SHIFT                                  24
+#define OMAP4_HSI_DR3_LB_MASK                                   (1 << 24)
+#define OMAP4_MCBSP2_DR0_LB_SHIFT                               23
+#define OMAP4_MCBSP2_DR0_LB_MASK                                (1 << 23)
+#define OMAP4_MCSPI4_DR0_LB_SHIFT                               22
+#define OMAP4_MCSPI4_DR0_LB_MASK                                (1 << 22)
+#define OMAP4_MCSPI4_DR1_LB_SHIFT                               21
+#define OMAP4_MCSPI4_DR1_LB_MASK                                (1 << 21)
+#define OMAP4_SLIMBUS2_DR0_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR0_LB_MASK                              (1 << 18)
+#define OMAP4_SPI2_DR0_LB_SHIFT                                 16
+#define OMAP4_SPI2_DR0_LB_MASK                                  (1 << 16)
+#define OMAP4_SPI2_DR1_LB_SHIFT                                 15
+#define OMAP4_SPI2_DR1_LB_MASK                                  (1 << 15)
+#define OMAP4_SPI2_DR2_LB_SHIFT                                 14
+#define OMAP4_SPI2_DR2_LB_MASK                                  (1 << 14)
+#define OMAP4_UART2_DR0_LB_SHIFT                                13
+#define OMAP4_UART2_DR0_LB_MASK                                 (1 << 13)
+#define OMAP4_UART2_DR1_LB_SHIFT                                12
+#define OMAP4_UART2_DR1_LB_MASK                                 (1 << 12)
+#define OMAP4_UART4_DR0_LB_SHIFT                                11
+#define OMAP4_UART4_DR0_LB_MASK                                 (1 << 11)
+#define OMAP4_HSI_DR0_LB_SHIFT                                  10
+#define OMAP4_HSI_DR0_LB_MASK                                   (1 << 10)
+
+/* CONTROL_USBB_HSIC */
+#define OMAP4_USBB2_DR1_SR_SHIFT                                30
+#define OMAP4_USBB2_DR1_SR_MASK                                 (0x3 << 30)
+#define OMAP4_USBB2_DR1_I_SHIFT                                 27
+#define OMAP4_USBB2_DR1_I_MASK                                  (0x7 << 27)
+#define OMAP4_USBB1_DR1_SR_SHIFT                                25
+#define OMAP4_USBB1_DR1_SR_MASK                                 (0x3 << 25)
+#define OMAP4_USBB1_DR1_I_SHIFT                                 22
+#define OMAP4_USBB1_DR1_I_MASK                                  (0x7 << 22)
+#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT                          20
+#define OMAP4_USBB1_HSIC_DATA_WD_MASK                           (0x3 << 20)
+#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT                        18
+#define OMAP4_USBB1_HSIC_STROBE_WD_MASK                         (0x3 << 18)
+#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT                          16
+#define OMAP4_USBB2_HSIC_DATA_WD_MASK                           (0x3 << 16)
+#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT                        14
+#define OMAP4_USBB2_HSIC_STROBE_WD_MASK                         (0x3 << 14)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           13
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 13)
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT                  11
+#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 11)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         10
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 10)
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT                8
+#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 8)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT           7
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK            (1 << 7)
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT                  5
+#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK                   (0x3 << 5)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT         4
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK          (1 << 4)
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT                2
+#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK                 (0x3 << 2)
+
+/* CONTROL_SLIMBUS */
+#define OMAP4_SLIMBUS1_DR0_MB_SHIFT                             30
+#define OMAP4_SLIMBUS1_DR0_MB_MASK                              (0x3 << 30)
+#define OMAP4_SLIMBUS1_DR1_MB_SHIFT                             28
+#define OMAP4_SLIMBUS1_DR1_MB_MASK                              (0x3 << 28)
+#define OMAP4_SLIMBUS2_DR0_MB_SHIFT                             26
+#define OMAP4_SLIMBUS2_DR0_MB_MASK                              (0x3 << 26)
+#define OMAP4_SLIMBUS2_DR1_MB_SHIFT                             24
+#define OMAP4_SLIMBUS2_DR1_MB_MASK                              (0x3 << 24)
+#define OMAP4_SLIMBUS2_DR2_MB_SHIFT                             22
+#define OMAP4_SLIMBUS2_DR2_MB_MASK                              (0x3 << 22)
+#define OMAP4_SLIMBUS2_DR3_MB_SHIFT                             20
+#define OMAP4_SLIMBUS2_DR3_MB_MASK                              (0x3 << 20)
+#define OMAP4_SLIMBUS1_DR0_LB_SHIFT                             19
+#define OMAP4_SLIMBUS1_DR0_LB_MASK                              (1 << 19)
+#define OMAP4_SLIMBUS2_DR1_LB_SHIFT                             18
+#define OMAP4_SLIMBUS2_DR1_LB_MASK                              (1 << 18)
+
+/* CONTROL_PBIASLITE */
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT                     31
+#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK                      (1 << 31)
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT                30
+#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 30)
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT                  29
+#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK                   (1 << 29)
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT                       28
+#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK                        (1 << 28)
+#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT                        27
+#define OMAP4_USIM_PBIASLITE_VMODE_MASK                         (1 << 27)
+#define OMAP4_MMC1_PWRDNZ_SHIFT                                 26
+#define OMAP4_MMC1_PWRDNZ_MASK                                  (1 << 26)
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT                     25
+#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK                      (1 << 25)
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT                24
+#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK                 (1 << 24)
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT                  23
+#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK                   (1 << 23)
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT                       22
+#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK                        (1 << 22)
+#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT                        21
+#define OMAP4_MMC1_PBIASLITE_VMODE_MASK                         (1 << 21)
+#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT                          20
+#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK                           (1 << 20)
+
+/* CONTROL_I2C_0 */
+#define OMAP4_I2C4_SDA_GLFENB_SHIFT                             31
+#define OMAP4_I2C4_SDA_GLFENB_MASK                              (1 << 31)
+#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT                          29
+#define OMAP4_I2C4_SDA_LOAD_BITS_MASK                           (0x3 << 29)
+#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT                         28
+#define OMAP4_I2C4_SDA_PULLUPRESX_MASK                          (1 << 28)
+#define OMAP4_I2C3_SDA_GLFENB_SHIFT                             27
+#define OMAP4_I2C3_SDA_GLFENB_MASK                              (1 << 27)
+#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT                          25
+#define OMAP4_I2C3_SDA_LOAD_BITS_MASK                           (0x3 << 25)
+#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT                         24
+#define OMAP4_I2C3_SDA_PULLUPRESX_MASK                          (1 << 24)
+#define OMAP4_I2C2_SDA_GLFENB_SHIFT                             23
+#define OMAP4_I2C2_SDA_GLFENB_MASK                              (1 << 23)
+#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT                          21
+#define OMAP4_I2C2_SDA_LOAD_BITS_MASK                           (0x3 << 21)
+#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT                         20
+#define OMAP4_I2C2_SDA_PULLUPRESX_MASK                          (1 << 20)
+#define OMAP4_I2C1_SDA_GLFENB_SHIFT                             19
+#define OMAP4_I2C1_SDA_GLFENB_MASK                              (1 << 19)
+#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT                          17
+#define OMAP4_I2C1_SDA_LOAD_BITS_MASK                           (0x3 << 17)
+#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT                         16
+#define OMAP4_I2C1_SDA_PULLUPRESX_MASK                          (1 << 16)
+#define OMAP4_I2C4_SCL_GLFENB_SHIFT                             15
+#define OMAP4_I2C4_SCL_GLFENB_MASK                              (1 << 15)
+#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT                          13
+#define OMAP4_I2C4_SCL_LOAD_BITS_MASK                           (0x3 << 13)
+#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT                         12
+#define OMAP4_I2C4_SCL_PULLUPRESX_MASK                          (1 << 12)
+#define OMAP4_I2C3_SCL_GLFENB_SHIFT                             11
+#define OMAP4_I2C3_SCL_GLFENB_MASK                              (1 << 11)
+#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT                          9
+#define OMAP4_I2C3_SCL_LOAD_BITS_MASK                           (0x3 << 9)
+#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT                         8
+#define OMAP4_I2C3_SCL_PULLUPRESX_MASK                          (1 << 8)
+#define OMAP4_I2C2_SCL_GLFENB_SHIFT                             7
+#define OMAP4_I2C2_SCL_GLFENB_MASK                              (1 << 7)
+#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT                          5
+#define OMAP4_I2C2_SCL_LOAD_BITS_MASK                           (0x3 << 5)
+#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT                         4
+#define OMAP4_I2C2_SCL_PULLUPRESX_MASK                          (1 << 4)
+#define OMAP4_I2C1_SCL_GLFENB_SHIFT                             3
+#define OMAP4_I2C1_SCL_GLFENB_MASK                              (1 << 3)
+#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT                          1
+#define OMAP4_I2C1_SCL_LOAD_BITS_MASK                           (0x3 << 1)
+#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT                         0
+#define OMAP4_I2C1_SCL_PULLUPRESX_MASK                          (1 << 0)
+
+/* CONTROL_CAMERA_RX */
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT                   31
+#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK                    (1 << 31)
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT                   29
+#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK                    (0x3 << 29)
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT                   24
+#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK                    (0x1f << 24)
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT                     22
+#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK                      (0x3 << 22)
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT                    21
+#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK                     (1 << 21)
+#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT                      19
+#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK                       (0x3 << 19)
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT                    18
+#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK                     (1 << 18)
+#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT                      16
+#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK                       (0x3 << 16)
+
+/* CONTROL_AVDAC */
+#define OMAP4_AVDAC_ACEN_SHIFT                                  31
+#define OMAP4_AVDAC_ACEN_MASK                                   (1 << 31)
+#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT                           30
+#define OMAP4_AVDAC_TVOUTBYPASS_MASK                            (1 << 30)
+#define OMAP4_AVDAC_INPUTINV_SHIFT                              29
+#define OMAP4_AVDAC_INPUTINV_MASK                               (1 << 29)
+#define OMAP4_AVDAC_CTL_SHIFT                                   13
+#define OMAP4_AVDAC_CTL_MASK                                    (0xffff << 13)
+#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT                            12
+#define OMAP4_AVDAC_CTL_WR_ACK_MASK                             (1 << 12)
+
+/* CONTROL_HDMI_TX_PHY */
+#define OMAP4_HDMITXPHY_PADORDER_SHIFT                          31
+#define OMAP4_HDMITXPHY_PADORDER_MASK                           (1 << 31)
+#define OMAP4_HDMITXPHY_TXVALID_SHIFT                           30
+#define OMAP4_HDMITXPHY_TXVALID_MASK                            (1 << 30)
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT                       29
+#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK                        (1 << 29)
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT                      28
+#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK                       (1 << 28)
+
+/* CONTROL_MMC2 */
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT                       31
+#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK                        (1 << 31)
+
+/* CONTROL_DSIPHY */
+#define OMAP4_DSI2_LANEENABLE_SHIFT                             29
+#define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
+#define OMAP4_DSI1_LANEENABLE_SHIFT                             24
+#define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
+
+/* CONTROL_MCBSPLP */
+#define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
+#define OMAP4_ALBCTRLRX_FSX_MASK                                (1 << 31)
+#define OMAP4_ALBCTRLRX_CLKX_SHIFT                              30
+#define OMAP4_ALBCTRLRX_CLKX_MASK                               (1 << 30)
+#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT                            29
+#define OMAP4_ABE_MCBSP1_DR_EN_MASK                             (1 << 29)
+
+/* CONTROL_USB2PHYCORE */
+#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT                       31
+#define OMAP4_USB2PHY_AUTORESUME_EN_MASK                        (1 << 31)
+#define OMAP4_USB2PHY_DISCHGDET_SHIFT                           30
+#define OMAP4_USB2PHY_DISCHGDET_MASK                            (1 << 30)
+#define OMAP4_USB2PHY_GPIOMODE_SHIFT                            29
+#define OMAP4_USB2PHY_GPIOMODE_MASK                             (1 << 29)
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT                     28
+#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK                      (1 << 28)
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT                    27
+#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK                     (1 << 27)
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT                    26
+#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK                     (1 << 26)
+#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT                         25
+#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK                          (1 << 25)
+#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT                        24
+#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK                         (1 << 24)
+#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT                      21
+#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK                       (0x7 << 21)
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT                     20
+#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK                      (1 << 20)
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT                     19
+#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK                      (1 << 19)
+#define OMAP4_USB2PHY_DATADET_SHIFT                             18
+#define OMAP4_USB2PHY_DATADET_MASK                              (1 << 18)
+#define OMAP4_USB2PHY_SINKONDP_SHIFT                            17
+#define OMAP4_USB2PHY_SINKONDP_MASK                             (1 << 17)
+#define OMAP4_USB2PHY_SRCONDM_SHIFT                             16
+#define OMAP4_USB2PHY_SRCONDM_MASK                              (1 << 16)
+#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT                       15
+#define OMAP4_USB2PHY_RESTARTCHGDET_MASK                        (1 << 15)
+#define OMAP4_USB2PHY_CHGDETDONE_SHIFT                          14
+#define OMAP4_USB2PHY_CHGDETDONE_MASK                           (1 << 14)
+#define OMAP4_USB2PHY_CHGDETECTED_SHIFT                         13
+#define OMAP4_USB2PHY_CHGDETECTED_MASK                          (1 << 13)
+#define OMAP4_USB2PHY_MCPCPUEN_SHIFT                            12
+#define OMAP4_USB2PHY_MCPCPUEN_MASK                             (1 << 12)
+#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT                          11
+#define OMAP4_USB2PHY_MCPCMODEEN_MASK                           (1 << 11)
+#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT                       10
+#define OMAP4_USB2PHY_RESETDONEMCLK_MASK                        (1 << 10)
+#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT                       9
+#define OMAP4_USB2PHY_UTMIRESETDONE_MASK                        (1 << 9)
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT                    8
+#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK                     (1 << 8)
+#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT                       7
+#define OMAP4_USB2PHY_DATAPOLARITYN_MASK                        (1 << 7)
+#define OMAP4_USBDPLL_FREQLOCK_SHIFT                            6
+#define OMAP4_USBDPLL_FREQLOCK_MASK                             (1 << 6)
+#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT                       5
+#define OMAP4_USB2PHY_RESETDONETCLK_MASK                        (1 << 5)
+
+/* CONTROL_I2C_1 */
+#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT                         31
+#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK                          (1 << 31)
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT                      29
+#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK                       (0x3 << 29)
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT                     28
+#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK                      (1 << 28)
+#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT                         27
+#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK                          (1 << 27)
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT                      25
+#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK                       (0x3 << 25)
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT                     24
+#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK                      (1 << 24)
+#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT                         23
+#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK                          (1 << 23)
+#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT                          22
+#define OMAP4_HDMI_DDC_SDA_NMODE_MASK                           (1 << 22)
+#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT                         21
+#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK                          (1 << 21)
+#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT                          20
+#define OMAP4_HDMI_DDC_SCL_NMODE_MASK                           (1 << 20)
+
+/* CONTROL_MMC1 */
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT                      31
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK                       (1 << 31)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT                      30
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK                       (1 << 30)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT                      29
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK                       (1 << 29)
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT                      28
+#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK                       (1 << 28)
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT                        27
+#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK                         (1 << 27)
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT                        26
+#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK                         (1 << 26)
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT                        25
+#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK                         (1 << 25)
+#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT                         24
+#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK                          (1 << 24)
+#define OMAP4_USB_FD_CDEN_SHIFT                                 23
+#define OMAP4_USB_FD_CDEN_MASK                                  (1 << 23)
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT                        22
+#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK                         (1 << 22)
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT                        21
+#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK                         (1 << 21)
+
+/* CONTROL_HSI */
+#define OMAP4_HSI1_CALLOOP_SEL_SHIFT                            31
+#define OMAP4_HSI1_CALLOOP_SEL_MASK                             (1 << 31)
+#define OMAP4_HSI1_CALMUX_SEL_SHIFT                             30
+#define OMAP4_HSI1_CALMUX_SEL_MASK                              (1 << 30)
+#define OMAP4_HSI2_CALLOOP_SEL_SHIFT                            29
+#define OMAP4_HSI2_CALLOOP_SEL_MASK                             (1 << 29)
+#define OMAP4_HSI2_CALMUX_SEL_SHIFT                             28
+#define OMAP4_HSI2_CALMUX_SEL_MASK                              (1 << 28)
+
+/* CONTROL_USB */
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT           31
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK            (1 << 31)
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT           30
+#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK            (1 << 30)
+
+/* CONTROL_HDQ */
+#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT                              31
+#define OMAP4_HDQ_SIO_PWRDNZ_MASK                               (1 << 31)
+
+/* CONTROL_LPDDR2IO1_0 */
+#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_1 */
+#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO1_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO1_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO1_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO1_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO1_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO1_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO1_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO1_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO1_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO1_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO1_2 */
+#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO1_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO1_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO1_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO1_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO1_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO1_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO1_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO1_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO1_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO1_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO1_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO1_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO1_3 */
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_LPDDR2IO2_0 */
+#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR4_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR4_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR4_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR4_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR3_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR3_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR3_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR3_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR2_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR2_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR2_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR2_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR1_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR1_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR1_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR1_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_1 */
+#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT                            30
+#define OMAP4_LPDDR2IO2_GR8_SR_MASK                             (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR8_I_SHIFT                             27
+#define OMAP4_LPDDR2IO2_GR8_I_MASK                              (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT                            25
+#define OMAP4_LPDDR2IO2_GR8_WD_MASK                             (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT                            22
+#define OMAP4_LPDDR2IO2_GR7_SR_MASK                             (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR7_I_SHIFT                             19
+#define OMAP4_LPDDR2IO2_GR7_I_MASK                              (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT                            17
+#define OMAP4_LPDDR2IO2_GR7_WD_MASK                             (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR6_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR6_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR6_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR6_WD_MASK                             (0x3 << 9)
+#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT                            6
+#define OMAP4_LPDDR2IO2_GR5_SR_MASK                             (0x3 << 6)
+#define OMAP4_LPDDR2IO2_GR5_I_SHIFT                             3
+#define OMAP4_LPDDR2IO2_GR5_I_MASK                              (0x7 << 3)
+#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT                            1
+#define OMAP4_LPDDR2IO2_GR5_WD_MASK                             (0x3 << 1)
+
+/* CONTROL_LPDDR2IO2_2 */
+#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT                           30
+#define OMAP4_LPDDR2IO2_GR11_SR_MASK                            (0x3 << 30)
+#define OMAP4_LPDDR2IO2_GR11_I_SHIFT                            27
+#define OMAP4_LPDDR2IO2_GR11_I_MASK                             (0x7 << 27)
+#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT                           25
+#define OMAP4_LPDDR2IO2_GR11_WD_MASK                            (0x3 << 25)
+#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT                           22
+#define OMAP4_LPDDR2IO2_GR10_SR_MASK                            (0x3 << 22)
+#define OMAP4_LPDDR2IO2_GR10_I_SHIFT                            19
+#define OMAP4_LPDDR2IO2_GR10_I_MASK                             (0x7 << 19)
+#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT                           17
+#define OMAP4_LPDDR2IO2_GR10_WD_MASK                            (0x3 << 17)
+#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT                            14
+#define OMAP4_LPDDR2IO2_GR9_SR_MASK                             (0x3 << 14)
+#define OMAP4_LPDDR2IO2_GR9_I_SHIFT                             11
+#define OMAP4_LPDDR2IO2_GR9_I_MASK                              (0x7 << 11)
+#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT                            9
+#define OMAP4_LPDDR2IO2_GR9_WD_MASK                             (0x3 << 9)
+
+/* CONTROL_LPDDR2IO2_3 */
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT                       31
+#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK                        (1 << 31)
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT                       30
+#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK                        (1 << 30)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT                   29
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK                    (1 << 29)
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT                   28
+#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK                    (1 << 28)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT                    27
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK                     (1 << 27)
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT                    26
+#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK                     (1 << 26)
+#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT                        25
+#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK                         (1 << 25)
+#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT                        24
+#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK                         (1 << 24)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT                  23
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK                   (1 << 23)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT                  22
+#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK                   (1 << 22)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT                   21
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK                    (1 << 21)
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT                   20
+#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK                    (1 << 20)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT                  19
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK                   (1 << 19)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT                  18
+#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK                   (1 << 18)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT                   17
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK                    (1 << 17)
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT                   16
+#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK                    (1 << 16)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT                       15
+#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK                        (1 << 15)
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT                       14
+#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK                        (1 << 14)
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT                        13
+#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK                         (1 << 13)
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT                        12
+#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK                         (1 << 12)
+
+/* CONTROL_BUS_HOLD */
+#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT                            31
+#define OMAP4_ABE_DMIC_DIN3_EN_MASK                             (1 << 31)
+#define OMAP4_MCSPI1_CS3_EN_SHIFT                               30
+#define OMAP4_MCSPI1_CS3_EN_MASK                                (1 << 30)
+
+/* CONTROL_C2C */
+#define OMAP4_MIRROR_MODE_EN_SHIFT                              31
+#define OMAP4_MIRROR_MODE_EN_MASK                               (1 << 31)
+#define OMAP4_C2C_SPARE_SHIFT                                   24
+#define OMAP4_C2C_SPARE_MASK                                    (0x7f << 24)
+
+/* CORE_CONTROL_SPARE_RW */
+#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_CORE_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R */
+#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_CORE_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* CORE_CONTROL_SPARE_R_C0 */
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+/* CONTROL_EFUSE_1 */
+#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT                            24
+#define OMAP4_AVDAC_TRIM_BYTE3_MASK                             (0x7f << 24)
+#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT                            16
+#define OMAP4_AVDAC_TRIM_BYTE2_MASK                             (0xff << 16)
+#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT                            8
+#define OMAP4_AVDAC_TRIM_BYTE1_MASK                             (0xff << 8)
+#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT                            0
+#define OMAP4_AVDAC_TRIM_BYTE0_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_2 */
+#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT                         31
+#define OMAP4_EFUSE_SMART2TEST_P0_MASK                          (1 << 31)
+#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT                         30
+#define OMAP4_EFUSE_SMART2TEST_P1_MASK                          (1 << 30)
+#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT                         29
+#define OMAP4_EFUSE_SMART2TEST_P2_MASK                          (1 << 29)
+#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT                         28
+#define OMAP4_EFUSE_SMART2TEST_P3_MASK                          (1 << 28)
+#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT                         27
+#define OMAP4_EFUSE_SMART2TEST_N0_MASK                          (1 << 27)
+#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT                         26
+#define OMAP4_EFUSE_SMART2TEST_N1_MASK                          (1 << 26)
+#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT                         25
+#define OMAP4_EFUSE_SMART2TEST_N2_MASK                          (1 << 25)
+#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT                         24
+#define OMAP4_EFUSE_SMART2TEST_N3_MASK                          (1 << 24)
+#define OMAP4_LPDDR2_PTV_N1_SHIFT                               23
+#define OMAP4_LPDDR2_PTV_N1_MASK                                (1 << 23)
+#define OMAP4_LPDDR2_PTV_N2_SHIFT                               22
+#define OMAP4_LPDDR2_PTV_N2_MASK                                (1 << 22)
+#define OMAP4_LPDDR2_PTV_N3_SHIFT                               21
+#define OMAP4_LPDDR2_PTV_N3_MASK                                (1 << 21)
+#define OMAP4_LPDDR2_PTV_N4_SHIFT                               20
+#define OMAP4_LPDDR2_PTV_N4_MASK                                (1 << 20)
+#define OMAP4_LPDDR2_PTV_N5_SHIFT                               19
+#define OMAP4_LPDDR2_PTV_N5_MASK                                (1 << 19)
+#define OMAP4_LPDDR2_PTV_P1_SHIFT                               18
+#define OMAP4_LPDDR2_PTV_P1_MASK                                (1 << 18)
+#define OMAP4_LPDDR2_PTV_P2_SHIFT                               17
+#define OMAP4_LPDDR2_PTV_P2_MASK                                (1 << 17)
+#define OMAP4_LPDDR2_PTV_P3_SHIFT                               16
+#define OMAP4_LPDDR2_PTV_P3_MASK                                (1 << 16)
+#define OMAP4_LPDDR2_PTV_P4_SHIFT                               15
+#define OMAP4_LPDDR2_PTV_P4_MASK                                (1 << 15)
+#define OMAP4_LPDDR2_PTV_P5_SHIFT                               14
+#define OMAP4_LPDDR2_PTV_P5_MASK                                (1 << 14)
+
+/* CONTROL_EFUSE_3 */
+#define OMAP4_STD_FUSE_SPARE_1_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_1_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_2_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_2_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_3_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_3_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_4_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_4_MASK                             (0xff << 0)
+
+/* CONTROL_EFUSE_4 */
+#define OMAP4_STD_FUSE_SPARE_5_SHIFT                            24
+#define OMAP4_STD_FUSE_SPARE_5_MASK                             (0xff << 24)
+#define OMAP4_STD_FUSE_SPARE_6_SHIFT                            16
+#define OMAP4_STD_FUSE_SPARE_6_MASK                             (0xff << 16)
+#define OMAP4_STD_FUSE_SPARE_7_SHIFT                            8
+#define OMAP4_STD_FUSE_SPARE_7_MASK                             (0xff << 8)
+#define OMAP4_STD_FUSE_SPARE_8_SHIFT                            0
+#define OMAP4_STD_FUSE_SPARE_8_MASK                             (0xff << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 000000000000..17c9b37042c0
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
+/*
+ * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP                                      0x4a31e000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION                          0x0000
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO                            0x0004
+#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG                         0x0010
+#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0                0x007c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0       0x05a0
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1       0x05a4
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE                 0x05a8
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR              0x05ac
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO                       0x0600
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2                        0x0604
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG                         0x0608
+#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS                          0x060c
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW                0x0614
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R                 0x0618
+#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0              0x061c
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT                               30
+#define OMAP4_IP_REV_SCHEME_MASK                                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                                 16
+#define OMAP4_IP_REV_FUNC_MASK                                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                                  11
+#define OMAP4_IP_REV_RTL_MASK                                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                                8
+#define OMAP4_IP_REV_MAJOR_MASK                                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT                               6
+#define OMAP4_IP_REV_CUSTOM_MASK                                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                                0
+#define OMAP4_IP_REV_MINOR_MASK                                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                                   0
+#define OMAP4_IP_HWINFO_MASK                                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT                       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK                        (0x3 << 2)
+
+/* PADCONF_WAKEUPEVENT_0 */
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT               24
+#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK                (1 << 24)
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT               23
+#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK                (1 << 23)
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT          22
+#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK           (1 << 22)
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT              21
+#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK               (1 << 21)
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT               20
+#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK                (1 << 20)
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT             19
+#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK              (1 << 19)
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT              18
+#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK               (1 << 18)
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT              17
+#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK               (1 << 17)
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT    16
+#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK     (1 << 16)
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT            15
+#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK             (1 << 15)
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT           14
+#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK            (1 << 14)
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT                13
+#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK                 (1 << 13)
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT          12
+#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 12)
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT          11
+#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 11)
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT          10
+#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 10)
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT          9
+#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK           (1 << 9)
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT          8
+#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK           (1 << 8)
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT         7
+#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK          (1 << 7)
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT                 6
+#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK                  (1 << 6)
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT                 5
+#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK                  (1 << 5)
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT            4
+#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK             (1 << 4)
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT                 3
+#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK                  (1 << 3)
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT              2
+#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK               (1 << 2)
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT                1
+#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK                 (1 << 1)
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT                 0
+#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK                  (1 << 0)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_0 */
+#define OMAP4_FREF_DR0_SC_SHIFT                                 30
+#define OMAP4_FREF_DR0_SC_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_SC_SHIFT                                 28
+#define OMAP4_FREF_DR1_SC_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_SC_SHIFT                                 26
+#define OMAP4_FREF_DR4_SC_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_SC_SHIFT                                 24
+#define OMAP4_FREF_DR5_SC_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_SC_SHIFT                                 22
+#define OMAP4_FREF_DR6_SC_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_SC_SHIFT                                 20
+#define OMAP4_FREF_DR7_SC_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_SC_SHIFT                                 18
+#define OMAP4_GPIO_DR7_SC_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_SC_SHIFT                                  14
+#define OMAP4_DPM_DR0_SC_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_SC_SHIFT                                  12
+#define OMAP4_SIM_DR0_SC_MASK                                   (0x3 << 12)
+
+/* CONTROL_SMART1NOPMIO_PADCONF_1 */
+#define OMAP4_FREF_DR0_LB_SHIFT                                 30
+#define OMAP4_FREF_DR0_LB_MASK                                  (0x3 << 30)
+#define OMAP4_FREF_DR1_LB_SHIFT                                 28
+#define OMAP4_FREF_DR1_LB_MASK                                  (0x3 << 28)
+#define OMAP4_FREF_DR4_LB_SHIFT                                 26
+#define OMAP4_FREF_DR4_LB_MASK                                  (0x3 << 26)
+#define OMAP4_FREF_DR5_LB_SHIFT                                 24
+#define OMAP4_FREF_DR5_LB_MASK                                  (0x3 << 24)
+#define OMAP4_FREF_DR6_LB_SHIFT                                 22
+#define OMAP4_FREF_DR6_LB_MASK                                  (0x3 << 22)
+#define OMAP4_FREF_DR7_LB_SHIFT                                 20
+#define OMAP4_FREF_DR7_LB_MASK                                  (0x3 << 20)
+#define OMAP4_GPIO_DR7_LB_SHIFT                                 18
+#define OMAP4_GPIO_DR7_LB_MASK                                  (0x3 << 18)
+#define OMAP4_DPM_DR0_LB_SHIFT                                  14
+#define OMAP4_DPM_DR0_LB_MASK                                   (0x3 << 14)
+#define OMAP4_SIM_DR0_LB_SHIFT                                  12
+#define OMAP4_SIM_DR0_LB_MASK                                   (0x3 << 12)
+
+/* CONTROL_PADCONF_MODE */
+#define OMAP4_VDDS_DV_FREF_SHIFT                                31
+#define OMAP4_VDDS_DV_FREF_MASK                                 (1 << 31)
+#define OMAP4_VDDS_DV_BANK2_SHIFT                               30
+#define OMAP4_VDDS_DV_BANK2_MASK                                (1 << 30)
+
+/* CONTROL_XTAL_OSCILLATOR */
+#define OMAP4_OSCILLATOR_BOOST_SHIFT                            31
+#define OMAP4_OSCILLATOR_BOOST_MASK                             (1 << 31)
+#define OMAP4_OSCILLATOR_OS_OUT_SHIFT                           30
+#define OMAP4_OSCILLATOR_OS_OUT_MASK                            (1 << 30)
+
+/* CONTROL_USIMIO */
+#define OMAP4_PAD_USIM_CLK_LOW_SHIFT                            31
+#define OMAP4_PAD_USIM_CLK_LOW_MASK                             (1 << 31)
+#define OMAP4_PAD_USIM_RST_LOW_SHIFT                            29
+#define OMAP4_PAD_USIM_RST_LOW_MASK                             (1 << 29)
+#define OMAP4_USIM_PWRDNZ_SHIFT                                 28
+#define OMAP4_USIM_PWRDNZ_MASK                                  (1 << 28)
+
+/* CONTROL_I2C_2 */
+#define OMAP4_SR_SDA_GLFENB_SHIFT                               31
+#define OMAP4_SR_SDA_GLFENB_MASK                                (1 << 31)
+#define OMAP4_SR_SDA_LOAD_BITS_SHIFT                            29
+#define OMAP4_SR_SDA_LOAD_BITS_MASK                             (0x3 << 29)
+#define OMAP4_SR_SDA_PULLUPRESX_SHIFT                           28
+#define OMAP4_SR_SDA_PULLUPRESX_MASK                            (1 << 28)
+#define OMAP4_SR_SCL_GLFENB_SHIFT                               27
+#define OMAP4_SR_SCL_GLFENB_MASK                                (1 << 27)
+#define OMAP4_SR_SCL_LOAD_BITS_SHIFT                            25
+#define OMAP4_SR_SCL_LOAD_BITS_MASK                             (0x3 << 25)
+#define OMAP4_SR_SCL_PULLUPRESX_SHIFT                           24
+#define OMAP4_SR_SCL_PULLUPRESX_MASK                            (1 << 24)
+
+/* CONTROL_JTAG */
+#define OMAP4_JTAG_NTRST_EN_SHIFT                               31
+#define OMAP4_JTAG_NTRST_EN_MASK                                (1 << 31)
+#define OMAP4_JTAG_TCK_EN_SHIFT                                 30
+#define OMAP4_JTAG_TCK_EN_MASK                                  (1 << 30)
+#define OMAP4_JTAG_RTCK_EN_SHIFT                                29
+#define OMAP4_JTAG_RTCK_EN_MASK                                 (1 << 29)
+#define OMAP4_JTAG_TDI_EN_SHIFT                                 28
+#define OMAP4_JTAG_TDI_EN_MASK                                  (1 << 28)
+#define OMAP4_JTAG_TDO_EN_SHIFT                                 27
+#define OMAP4_JTAG_TDO_EN_MASK                                  (1 << 27)
+
+/* CONTROL_SYS */
+#define OMAP4_SYS_NRESWARM_PIPU_SHIFT                           31
+#define OMAP4_SYS_NRESWARM_PIPU_MASK                            (1 << 31)
+
+/* WKUP_CONTROL_SPARE_RW */
+#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT                       0
+#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK                        (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R */
+#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT                        0
+#define OMAP4_WKUP_CONTROL_SPARE_R_MASK                         (0xffffffff << 0)
+
+/* WKUP_CONTROL_SPARE_R_C0 */
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT                     31
+#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK                      (1 << 31)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT                     30
+#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK                      (1 << 30)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT                     29
+#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK                      (1 << 29)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT                     28
+#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK                      (1 << 28)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT                     27
+#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK                      (1 << 27)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT                     26
+#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK                      (1 << 26)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT                     25
+#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK                      (1 << 25)
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT                     24
+#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK                      (1 << 24)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 000000000000..a0af9baec3f7
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
+/*
+ * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ * Santosh Shilimkar (santosh.shilimkar@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
+
+
+/* Base address */
+#define OMAP4_CTRL_MODULE_WKUP                          0x4a30c000
+
+/* Registers offset */
+#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION              0x0000
+#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO                0x0004
+#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG             0x0010
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0     0x0460
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1     0x0464
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2     0x0468
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3     0x046c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4     0x0470
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5     0x0474
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6     0x0478
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7     0x047c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8     0x0480
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9     0x0484
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10    0x0488
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11    0x048c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12    0x0490
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13    0x0494
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14    0x0498
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15    0x049c
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16    0x04a0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17    0x04a4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18    0x04a8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19    0x04ac
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20    0x04b0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21    0x04b4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22    0x04b8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23    0x04bc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24    0x04c0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25    0x04c4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26    0x04c8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27    0x04cc
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28    0x04d0
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29    0x04d4
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30    0x04d8
+#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31    0x04dc
+
+/* Registers shifts and masks */
+
+/* IP_REVISION */
+#define OMAP4_IP_REV_SCHEME_SHIFT               30
+#define OMAP4_IP_REV_SCHEME_MASK                (0x3 << 30)
+#define OMAP4_IP_REV_FUNC_SHIFT                 16
+#define OMAP4_IP_REV_FUNC_MASK                  (0xfff << 16)
+#define OMAP4_IP_REV_RTL_SHIFT                  11
+#define OMAP4_IP_REV_RTL_MASK                   (0x1f << 11)
+#define OMAP4_IP_REV_MAJOR_SHIFT                8
+#define OMAP4_IP_REV_MAJOR_MASK                 (0x7 << 8)
+#define OMAP4_IP_REV_CUSTOM_SHIFT               6
+#define OMAP4_IP_REV_CUSTOM_MASK                (0x3 << 6)
+#define OMAP4_IP_REV_MINOR_SHIFT                0
+#define OMAP4_IP_REV_MINOR_MASK                 (0x3f << 0)
+
+/* IP_HWINFO */
+#define OMAP4_IP_HWINFO_SHIFT                   0
+#define OMAP4_IP_HWINFO_MASK                    (0xffffffff << 0)
+
+/* IP_SYSCONFIG */
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT       2
+#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK        (0x3 << 2)
+
+/* CONF_DEBUG_SEL_TST_0 */
+#define OMAP4_WKUP_MODE_SHIFT                   0
+#define OMAP4_WKUP_MODE_MASK                            (1 << 0)
+
+#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b9ea70bce563..40562ddd3ee4 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -36,6 +36,7 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "io.h"
 
 #include <plat/omap-pm.h>
 #include <plat/powerdomain.h>
@@ -323,6 +324,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
                 omap2430_hwmod_init();
         else if (cpu_is_omap34xx())
                 omap3xxx_hwmod_init();
+        else if (cpu_is_omap44xx())
+                omap44xx_hwmod_init();
+
         /* The OPP tables have to be registered before a clk init */
         omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
 
@@ -342,9 +346,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 #ifndef CONFIG_PM_RUNTIME
         skip_setup_idle = 1;
 #endif
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())   /* FIXME: OMAP4 */
-                omap_hwmod_late_init(skip_setup_idle);
-
+        omap_hwmod_late_init(skip_setup_idle);
         if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
new file mode 100644
index 000000000000..fd230c6cded5
--- /dev/null
+++ b/arch/arm/mach-omap2/io.h
@@ -0,0 +1,7 @@
+
+#ifndef __MACH_OMAP2_IO_H__
+#define __MACH_OMAP2_IO_H__
+
+extern int __init omap_sram_init(void);
+
+#endif /*  __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 26aeef560aa3..32eeabe9d2ab 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -47,7 +47,6 @@ static struct omap_irq_bank {
 } __attribute__ ((aligned(4))) irq_banks[] = {
         {
                 /* MPU INTC */
-                .base_reg       = 0,
                 .nr_irqs        = 96,
         },
 };
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 42dbfa46e656..40ddecab93a9 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         l = mbox_read_reg(p->irqenable);
@@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
         l = mbox_read_reg(p->irqdisable);
         l &= ~bit;
@@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
 
         mbox_write_reg(bit, p->irqstatus);
@@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
                 omap_mbox_type_t irq)
 {
-        struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
+        struct omap_mbox2_priv *p = mbox->priv;
         u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
         u32 enable = mbox_read_reg(p->irqenable);
         u32 status = mbox_read_reg(p->irqstatus);
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 467aae245781..f9c9df5b5ff1 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -23,29 +23,86 @@
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
-#include "mux.h"
+#include "control.h"
 
-static void omap2_mcbsp2_mux_setup(void)
+
+/* McBSP internal signal muxing functions */
+
+void omap2_mcbsp1_mux_clkr_src(u8 mux)
 {
-        omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
-        omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
-        omap_mux_init_gpio(117, OMAP_PULL_ENA);
-        /*
-         * TODO: Need to add MUX settings for OMAP 2430 SDP
-         */
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == CLKR_SRC_CLKR)
+                v &= ~OMAP2_MCBSP1_CLKR_MASK;
+        else if (mux == CLKR_SRC_CLKX)
+                v |= OMAP2_MCBSP1_CLKR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
 
-static void omap2_mcbsp_request(unsigned int id)
+void omap2_mcbsp1_mux_fsr_src(u8 mux)
 {
-        if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
-                omap2_mcbsp2_mux_setup();
+        u32 v;
+
+        v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+        if (mux == FSR_SRC_FSR)
+                v &= ~OMAP2_MCBSP1_FSR_MASK;
+        else if (mux == FSR_SRC_FSX)
+                v |= OMAP2_MCBSP1_FSR_MASK;
+        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 }
+EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
 
-static struct omap_mcbsp_ops omap2_mcbsp_ops = {
-        .request        = omap2_mcbsp_request,
-};
+/* McBSP CLKS source switching function */
+
+int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
+{
+        struct omap_mcbsp *mcbsp;
+        struct clk *fck_src;
+        char *fck_src_name;
+        int r;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
+                return -EINVAL;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
+                fck_src_name = "pad_fck";
+        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
+                fck_src_name = "prcm_fck";
+        else
+                return -EINVAL;
+
+        fck_src = clk_get(mcbsp->dev, fck_src_name);
+        if (IS_ERR_OR_NULL(fck_src)) {
+                pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
+                       fck_src_name);
+                return -EINVAL;
+        }
+
+        clk_disable(mcbsp->fclk);
+
+        r = clk_set_parent(mcbsp->fclk, fck_src);
+        if (IS_ERR_VALUE(r)) {
+                pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
+                       "clks", fck_src_name);
+                clk_put(fck_src);
+                return -EINVAL;
+        }
+
+        clk_enable(mcbsp->fclk);
+
+        clk_put(fck_src);
+
+        return 0;
+}
+EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
+
+
+/* Platform data */
 
 #ifdef CONFIG_ARCH_OMAP2420
 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
@@ -55,7 +112,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -63,7 +119,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -82,7 +137,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP24XX_MCBSP2_BASE,
@@ -90,7 +144,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP3_BASE,
@@ -98,7 +151,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP4_BASE,
@@ -106,7 +158,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP2430_MCBSP5_BASE,
@@ -114,7 +165,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -133,7 +183,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -143,7 +192,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x500, /* The FIFO has 1024 + 256 locations */
         },
         {
@@ -153,7 +201,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -162,7 +209,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
         {
@@ -171,7 +217,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .ops            = &omap2_mcbsp_ops,
                 .buffer_size    = 0x80, /* The FIFO has 128 locations */
         },
 };
@@ -189,28 +234,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP1,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP2_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP2,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP3_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP3,
-                .ops            = &omap2_mcbsp_ops,
         },
         {
                 .phys_base      = OMAP44XX_MCBSP4_BASE,
                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
                 .tx_irq         = OMAP44XX_IRQ_MCBSP4,
-                .ops            = &omap2_mcbsp_ops,
         },
 };
 #define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ab403b2ed26b..074536ae401f 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -23,12 +23,11 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
  */
-#include <linux/module.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <linux/ctype.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -36,8 +35,7 @@
 
 #include <asm/system.h>
 
-#include <plat/control.h>
-
+#include "control.h"
 #include "mux.h"
 
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
@@ -87,7 +85,7 @@ static char *omap_mux_options;
 int __init omap_mux_init_gpio(int gpio, int val)
 {
         struct omap_mux_entry *e;
-        struct omap_mux *gpio_mux;
+        struct omap_mux *gpio_mux = NULL;
         u16 old_mode;
         u16 mux_mode;
         int found = 0;
@@ -127,17 +125,16 @@ int __init omap_mux_init_gpio(int gpio, int val)
         return 0;
 }
 
-int __init omap_mux_init_signal(char *muxname, int val)
+int __init omap_mux_init_signal(const char *muxname, int val)
 {
         struct omap_mux_entry *e;
-        char *m0_name = NULL, *mode_name = NULL;
-        int found = 0;
+        const char *mode_name;
+        int found = 0, mode0_len = 0;
 
         mode_name = strchr(muxname, '.');
         if (mode_name) {
-                *mode_name = '\0';
+                mode0_len = strlen(muxname) - strlen(mode_name);
                 mode_name++;
-                m0_name = muxname;
         } else {
                 mode_name = muxname;
         }
@@ -147,9 +144,11 @@ int __init omap_mux_init_signal(char *muxname, int val)
                 char *m0_entry = m->muxnames[0];
                 int i;
 
-                if (m0_name && strcmp(m0_name, m0_entry))
+                /* First check for full name in mode0.muxmode format */
+                if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
                         continue;
 
+                /* Then check for muxmode only */
                 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
                         char *mode_cur = m->muxnames[i];
 
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a8e040c2c7e9..350c04f27383 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -120,7 +120,7 @@ int omap_mux_init_gpio(int gpio, int val);
  * @muxname:            Mux name in mode0_name.signal_name format
  * @val:                Options for the mux register value
  */
-int omap_mux_init_signal(char *muxname, int val);
+int omap_mux_init_signal(const char *muxname, int val);
 
 #else
 
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index fdb04a7eb8aa..414af5434456 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = {
  * Balls for 447-pin POP package
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2420_pop_ball[] = {
+static struct omap_ball __initdata omap2420_pop_ball[] = {
         _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
         _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
         _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 7dcaaa8af32a..84d2c5a7ecd7 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = {
  * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
  */
 #ifdef CONFIG_DEBUG_FS
-struct omap_ball __initdata omap2430_pop_ball[] = {
+static struct omap_ball __initdata omap2430_pop_ball[] = {
         _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
         _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
         _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index f64d7eea3451..574e54ea3ab7 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = {
  * Signals different on CUS package compared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_mux __initdata omap3_cus_subset[] = {
+static struct omap_mux __initdata omap3_cus_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1077,7 +1077,7 @@ struct omap_mux __initdata omap3_cus_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CUS)
-struct omap_ball __initdata omap3_cus_ball[] = {
+static struct omap_ball __initdata omap3_cus_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
@@ -1269,7 +1269,7 @@ struct omap_ball __initdata omap3_cus_ball[] = {
  * Signals different on CBB package comapared to superset
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_mux __initdata omap3_cbb_subset[] = {
+static struct omap_mux __initdata omap3_cbb_subset[] = {
         _OMAP3_MUXENTRY(CAM_D10, 109,
                 "cam_d10", NULL, NULL, NULL,
                 "gpio_109", NULL, NULL, "safe_mode"),
@@ -1390,7 +1390,7 @@ struct omap_mux __initdata omap3_cbb_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined(CONFIG_OMAP_PACKAGE_CBB)
-struct omap_ball __initdata omap3_cbb_ball[] = {
+static struct omap_ball __initdata omap3_cbb_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
@@ -1600,7 +1600,7 @@ struct omap_ball __initdata omap3_cbb_ball[] = {
  * Signals different on 36XX CBP package comapared to 34XX CBC package
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
-struct omap_mux __initdata omap36xx_cbp_subset[] = {
+static struct omap_mux __initdata omap36xx_cbp_subset[] = {
         _OMAP3_MUXENTRY(CAM_D0, 99,
                 "cam_d0", NULL, "csi2_dx2", NULL,
                 "gpio_99", NULL, NULL, "safe_mode"),
@@ -1818,7 +1818,7 @@ struct omap_mux __initdata omap36xx_cbp_subset[] = {
  */
 #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
                 && defined (CONFIG_OMAP_PACKAGE_CBP)
-struct omap_ball __initdata omap36xx_cbp_ball[] = {
+static struct omap_ball __initdata omap36xx_cbp_ball[] = {
         _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
         _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
         _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13dc9794dcc2..923f9f5f91ce 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void)
         omap_smc1(0x102, 0x1);
 
         /*
-         * 32KB way size, 16-way associativity,
-         * parity disabled
+         * 16-way associativity, parity disabled
+         * Way size - 32KB (es1.0)
+         * Way size - 64KB (es2.0 +)
          */
-        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+        else
+                l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cb911d7d1a3c..5a30658444d0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -13,10 +13,102 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * This code manages "OMAP modules" (on-chip devices) and their
- * integration with Linux device driver and bus code.
- *
- * References:
+ * Introduction
+ * ------------
+ * One way to view an OMAP SoC is as a collection of largely unrelated
+ * IP blocks connected by interconnects.  The IP blocks include
+ * devices such as ARM processors, audio serial interfaces, UARTs,
+ * etc.  Some of these devices, like the DSP, are created by TI;
+ * others, like the SGX, largely originate from external vendors.  In
+ * TI's documentation, on-chip devices are referred to as "OMAP
+ * modules."  Some of these IP blocks are identical across several
+ * OMAP versions.  Others are revised frequently.
+ *
+ * These OMAP modules are tied together by various interconnects.
+ * Most of the address and data flow between modules is via OCP-based
+ * interconnects such as the L3 and L4 buses; but there are other
+ * interconnects that distribute the hardware clock tree, handle idle
+ * and reset signaling, supply power, and connect the modules to
+ * various pads or balls on the OMAP package.
+ *
+ * OMAP hwmod provides a consistent way to describe the on-chip
+ * hardware blocks and their integration into the rest of the chip.
+ * This description can be automatically generated from the TI
+ * hardware database.  OMAP hwmod provides a standard, consistent API
+ * to reset, enable, idle, and disable these hardware blocks.  And
+ * hwmod provides a way for other core code, such as the Linux device
+ * code or the OMAP power management and address space mapping code,
+ * to query the hardware database.
+ *
+ * Using hwmod
+ * -----------
+ * Drivers won't call hwmod functions directly.  That is done by the
+ * omap_device code, and in rare occasions, by custom integration code
+ * in arch/arm/ *omap*.  The omap_device code includes functions to
+ * build a struct platform_device using omap_hwmod data, and that is
+ * currently how hwmod data is communicated to drivers and to the
+ * Linux driver model.  Most drivers will call omap_hwmod functions only
+ * indirectly, via pm_runtime*() functions.
+ *
+ * From a layering perspective, here is where the OMAP hwmod code
+ * fits into the kernel software stack:
+ *
+ *            +-------------------------------+
+ *            |      Device driver code       |
+ *            |      (e.g., drivers/)         |
+ *            +-------------------------------+
+ *            |      Linux driver model       |
+ *            |     (platform_device /        |
+ *            |  platform_driver data/code)   |
+ *            +-------------------------------+
+ *            | OMAP core-driver integration  |
+ *            |(arch/arm/mach-omap2/devices.c)|
+ *            +-------------------------------+
+ *            |      omap_device code         |
+ *            | (../plat-omap/omap_device.c)  |
+ *            +-------------------------------+
+ *   ---->    |    omap_hwmod code/data       |    <-----
+ *            | (../mach-omap2/omap_hwmod*)   |
+ *            +-------------------------------+
+ *            | OMAP clock/PRCM/register fns  |
+ *            | (__raw_{read,write}l, clk*)   |
+ *            +-------------------------------+
+ *
+ * Device drivers should not contain any OMAP-specific code or data in
+ * them.  They should only contain code to operate the IP block that
+ * the driver is responsible for.  This is because these IP blocks can
+ * also appear in other SoCs, either from TI (such as DaVinci) or from
+ * other manufacturers; and drivers should be reusable across other
+ * platforms.
+ *
+ * The OMAP hwmod code also will attempt to reset and idle all on-chip
+ * devices upon boot.  The goal here is for the kernel to be
+ * completely self-reliant and independent from bootloaders.  This is
+ * to ensure a repeatable configuration, both to ensure consistent
+ * runtime behavior, and to make it easier for others to reproduce
+ * bugs.
+ *
+ * OMAP module activity states
+ * ---------------------------
+ * The hwmod code considers modules to be in one of several activity
+ * states.  IP blocks start out in an UNKNOWN state, then once they
+ * are registered via the hwmod code, proceed to the REGISTERED state.
+ * Once their clock names are resolved to clock pointers, the module
+ * enters the CLKS_INITED state; and finally, once the module has been
+ * reset and the integration registers programmed, the INITIALIZED state
+ * is entered.  The hwmod code will then place the module into either
+ * the IDLE state to save power, or in the case of a critical system
+ * module, the ENABLED state.
+ *
+ * OMAP core integration code can then call omap_hwmod*() functions
+ * directly to move the module between the IDLE, ENABLED, and DISABLED
+ * states, as needed.  This is done during both the PM idle loop, and
+ * in the OMAP core integration code's implementation of the PM runtime
+ * functions.
+ *
+ * References
+ * ----------
+ * This is a partial list.
  * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
  * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
  * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
@@ -50,11 +142,13 @@
 #include <plat/powerdomain.h>
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
+#include <plat/prcm.h>
 
 #include "cm.h"
+#include "prm.h"
 
-/* Maximum microseconds to wait for OMAP module to reset */
-#define MAX_MODULE_RESET_WAIT           10000
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
 
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
@@ -90,7 +184,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh)
 
         /* XXX ensure module interface clock is up */
 
-        oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 
         if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
                 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
@@ -117,7 +211,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
 
         if (oh->_sysc_cache != v) {
                 oh->_sysc_cache = v;
-                omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs);
+                omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
         }
 }
 
@@ -544,6 +638,36 @@ static int _disable_clocks(struct omap_hwmod *oh)
         return 0;
 }
 
+static void _enable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_enable(oc->_clk);
+                }
+}
+
+static void _disable_optional_clocks(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_opt_clk *oc;
+        int i;
+
+        pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
+
+        for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
+                if (oc->_clk) {
+                        pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
+                                 oc->_clk->name);
+                        clk_disable(oc->_clk);
+                }
+}
+
 /**
  * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
  * @oh: struct omap_hwmod *
@@ -622,7 +746,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 }
 
 /**
- * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG
+ * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module out of slave
@@ -630,7 +754,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
  * as SWSUP_MSUSPEND, force the module out of master standby;
  * otherwise, configure it for smart-standby.  No return value.
  */
-static void _sysc_enable(struct omap_hwmod *oh)
+static void _enable_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -653,14 +777,6 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
-        if (sf & SYSC_HAS_AUTOIDLE) {
-                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
-                        0 : 1;
-                _set_module_autoidle(oh, idlemode, &v);
-        }
-
-        /* XXX OCP ENAWAKEUP bit? */
-
         /*
          * XXX The clock framework should handle this, by
          * calling into this code.  But this must wait until the
@@ -671,10 +787,25 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
         _write_sysconfig(v, oh);
+
+        /* If slave is in SMARTIDLE, also enable wakeup */
+        if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+                _enable_wakeup(oh);
+
+        /*
+         * Set the autoidle bit only after setting the smartidle bit
+         * Setting this will not have any impact on the other modules.
+         */
+        if (sf & SYSC_HAS_AUTOIDLE) {
+                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+                        0 : 1;
+                _set_module_autoidle(oh, idlemode, &v);
+                _write_sysconfig(v, oh);
+        }
 }
 
 /**
- * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG
+ * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * If module is marked as SWSUP_SIDLE, force the module into slave
@@ -682,7 +813,7 @@ static void _sysc_enable(struct omap_hwmod *oh)
  * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
  * configure it for smart-standby.  No return value.
  */
-static void _sysc_idle(struct omap_hwmod *oh)
+static void _idle_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
@@ -709,13 +840,13 @@ static void _sysc_idle(struct omap_hwmod *oh)
 }
 
 /**
- * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG
+ * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
  * Force the module into slave idle and master suspend. No return
  * value.
  */
-static void _sysc_shutdown(struct omap_hwmod *oh)
+static void _shutdown_sysc(struct omap_hwmod *oh)
 {
         u32 v;
         u8 sf;
@@ -767,10 +898,10 @@ static struct omap_hwmod *_lookup(const char *name)
  * @data: not used; pass NULL
  *
  * Called by omap_hwmod_late_init() (after omap2_clk_init()).
- * Resolves all clock names embedded in the hwmod.  Must be called
- * with omap_hwmod_mutex held.  Returns -EINVAL if the omap_hwmod
- * has not yet been registered or if the clocks have already been
- * initialized, 0 on success, or a non-zero error on failure.
+ * Resolves all clock names embedded in the hwmod.  Returns -EINVAL if
+ * the omap_hwmod has not yet been registered or if the clocks have
+ * already been initialized, 0 on success, or a non-zero error on
+ * failure.
  */
 static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
@@ -834,56 +965,202 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 
 /**
+ * _lookup_hardreset - return the register bit shift for this hwmod/reset line
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line in the context of this hwmod
+ *
+ * Return the bit position of the reset line that match the
+ * input name. Return -ENOENT if not found.
+ */
+static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int i;
+
+        for (i = 0; i < oh->rst_lines_cnt; i++) {
+                const char *rst_line = oh->rst_lines[i].name;
+                if (!strcmp(rst_line, name)) {
+                        u8 shift = oh->rst_lines[i].rst_shift;
+                        pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n",
+                                 oh->name, rst_line, shift);
+
+                        return shift;
+                }
+        }
+
+        return -ENOENT;
+}
+
+/**
+ * _assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+                                                  shift);
+        else if (cpu_is_omap44xx())
+                return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                  shift);
+        else
+                return -EINVAL;
+}
+
+/**
+ * _deassert_hardreset - deassert the HW reset line of submodules contained
+ * in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.
+ */
+static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+        int r;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+                                                 shift);
+        else if (cpu_is_omap44xx())
+                r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
+                                                 shift);
+        else
+                return -EINVAL;
+
+        if (r == -EBUSY)
+                pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
+
+        return r;
+}
+
+/**
+ * _read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the state of the reset line.
+ */
+static int _read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        u8 shift;
+
+        if (!oh)
+                return -EINVAL;
+
+        shift = _lookup_hardreset(oh, name);
+        if (IS_ERR_VALUE(shift))
+                return shift;
+
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+                                                       shift);
+        } else if (cpu_is_omap44xx()) {
+                return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
+                                                       shift);
+        } else {
+                return -EINVAL;
+        }
+}
+
+/**
  * _reset - reset an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- * enabled for this to work.  Must be called with omap_hwmod_mutex
- * held.  Returns -EINVAL if the hwmod cannot be reset this way or if
- * the hwmod is in the wrong state, -ETIMEDOUT if the module did not
- * reset in time, or 0 upon success.
+ * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
+ * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * the module did not reset in time, or 0 upon success.
+ *
+ * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
+ * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead
+ * use the SYSCONFIG softreset bit to provide the status.
+ *
+ * Note that some IP like McBSP does have a reset control but no reset status.
  */
 static int _reset(struct omap_hwmod *oh)
 {
-        u32 r, v;
+        u32 v;
         int c = 0;
+        int ret = 0;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) ||
-            (oh->class->sysc->sysc_flags & SYSS_MISSING))
+            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
                 return -EINVAL;
 
         /* clocks must be on for this operation */
         if (oh->_state != _HWMOD_STATE_ENABLED) {
-                WARN(1, "omap_hwmod: %s: reset can only be entered from "
-                     "enabled state\n", oh->name);
+                pr_warning("omap_hwmod: %s: reset can only be entered from "
+                           "enabled state\n", oh->name);
                 return -EINVAL;
         }
 
+        /* For some modules, all optionnal clocks need to be enabled as well */
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _enable_optional_clocks(oh);
+
         pr_debug("omap_hwmod: %s: resetting\n", oh->name);
 
         v = oh->_sysc_cache;
-        r = _set_softreset(oh, &v);
-        if (r)
-                return r;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto dis_opt_clks;
         _write_sysconfig(v, oh);
 
-        omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) &
-                           SYSS_RESETDONE_MASK),
-                          MAX_MODULE_RESET_WAIT, c);
-
-        if (c == MAX_MODULE_RESET_WAIT)
-                WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
-                     oh->name, MAX_MODULE_RESET_WAIT);
+        if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
+                omap_test_timeout((omap_hwmod_read(oh,
+                                                    oh->class->sysc->syss_offs)
+                                   & SYSS_RESETDONE_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+        else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
+                omap_test_timeout(!(omap_hwmod_read(oh,
+                                                     oh->class->sysc->sysc_offs)
+                                   & SYSC_TYPE2_SOFTRESET_MASK),
+                                  MAX_MODULE_SOFTRESET_WAIT, c);
+
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
+                           oh->name, MAX_MODULE_SOFTRESET_WAIT);
         else
-                pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c);
+                pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
 
         /*
          * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
          * _wait_target_ready() or _reset()
          */
 
-        return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0;
+        ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
+
+dis_opt_clks:
+        if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
+                _disable_optional_clocks(oh);
+
+        return ret;
 }
 
 /**
@@ -891,9 +1168,11 @@ static int _reset(struct omap_hwmod *oh)
  * @oh: struct omap_hwmod *
  *
  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
- * register target.  Must be called with omap_hwmod_mutex held.
- * Returns -EINVAL if the hwmod is in the wrong state or passes along
- * the return value of _wait_target_ready().
+ * register target.  (This function has a full name --
+ * _omap_hwmod_enable() rather than simply _enable() -- because it is
+ * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
+ * the hwmod is in the wrong state or passes along the return value of
+ * _wait_target_ready().
  */
 int _omap_hwmod_enable(struct omap_hwmod *oh)
 {
@@ -909,6 +1188,15 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: enabling\n", oh->name);
 
+        /*
+         * If an IP contains only one HW reset line, then de-assert it in order
+         * to allow to enable the clocks. Otherwise the PRCM will return
+         * Intransition status, and the init will failed.
+         */
+        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+                _deassert_hardreset(oh, oh->rst_lines[0].name);
+
         /* XXX mux balls */
 
         _add_initiator_dep(oh, mpu_oh);
@@ -922,7 +1210,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
                 if (oh->class->sysc) {
                         if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
                                 _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         } else {
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
@@ -933,12 +1221,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 }
 
 /**
- * _idle - idle an omap_hwmod
+ * _omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Idles an omap_hwmod @oh.  This should be called once the hwmod has
- * no further work.  Returns -EINVAL if the hwmod is in the wrong
- * state or returns 0.
+ * no further work.  (This function has a full name --
+ * _omap_hwmod_idle() rather than simply _idle() -- because it is
+ * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
+ * the hwmod is in the wrong state or returns 0.
  */
 int _omap_hwmod_idle(struct omap_hwmod *oh)
 {
@@ -951,7 +1241,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: idling\n", oh->name);
 
         if (oh->class->sysc)
-                _sysc_idle(oh);
+                _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
         _disable_clocks(oh);
 
@@ -981,10 +1271,21 @@ static int _shutdown(struct omap_hwmod *oh)
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
 
         if (oh->class->sysc)
-                _sysc_shutdown(oh);
-        _del_initiator_dep(oh, mpu_oh);
-        /* XXX what about the other system initiators here? DMA, tesla, d2d */
-        _disable_clocks(oh);
+                _shutdown_sysc(oh);
+
+        /*
+         * If an IP contains only one HW reset line, then assert it
+         * before disabling the clocks and shutting down the IP.
+         */
+        if (oh->rst_lines_cnt == 1)
+                _assert_hardreset(oh, oh->rst_lines[0].name);
+
+        /* clocks and deps are already disabled in idle */
+        if (oh->_state == _HWMOD_STATE_ENABLED) {
+                _del_initiator_dep(oh, mpu_oh);
+                /* XXX what about the other system initiators here? dma, dsp */
+                _disable_clocks(oh);
+        }
         /* XXX Should this code also force-disable the optional clocks? */
 
         /* XXX mux any associated balls to safe mode */
@@ -1000,11 +1301,10 @@ static int _shutdown(struct omap_hwmod *oh)
  * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Must be called with omap_hwmod_mutex held.
- * @skip_setup_idle is intended to be used on a system that will not
- * call omap_hwmod_enable() to enable devices (e.g., a system without
- * PM runtime).  Returns -EINVAL if the hwmod is in the wrong state or
- * returns 0.
+ * OCP_SYSCONFIG register.  @skip_setup_idle is intended to be used on
+ * a system that will not call omap_hwmod_enable() to enable devices
+ * (e.g., a system without PM runtime).  Returns -EINVAL if the hwmod
+ * is in the wrong state or returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
@@ -1034,8 +1334,19 @@ static int _setup(struct omap_hwmod *oh, void *data)
                 }
         }
 
+        mutex_init(&oh->_mutex);
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
+        /*
+         * In the case of hwmod with hardreset that should not be
+         * de-assert at boot time, we have to keep the module
+         * initialized, because we cannot enable it properly with the
+         * reset asserted. Exit without warning because that behavior is
+         * expected.
+         */
+        if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+                return 0;
+
         r = _omap_hwmod_enable(oh);
         if (r) {
                 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
@@ -1044,16 +1355,16 @@ static int _setup(struct omap_hwmod *oh, void *data)
         }
 
         if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+                _reset(oh);
+
                 /*
-                 * XXX Do the OCP_SYSCONFIG bits need to be
-                 * reprogrammed after a reset?  If not, then this can
-                 * be removed.  If they do, then probably the
-                 * _omap_hwmod_enable() function should be split to avoid the
-                 * rewrite of the OCP_SYSCONFIG register.
+                 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
+                 * The _omap_hwmod_enable() function should be split to
+                 * avoid the rewrite of the OCP_SYSCONFIG register.
                  */
                 if (oh->class->sysc) {
                         _update_sysc_cache(oh);
-                        _sysc_enable(oh);
+                        _enable_sysc(oh);
                 }
         }
 
@@ -1067,14 +1378,20 @@ static int _setup(struct omap_hwmod *oh, void *data)
 
 /* Public functions */
 
-u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs)
+u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
 {
-        return __raw_readl(oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                return __raw_readw(oh->_mpu_rt_va + reg_offs);
+        else
+                return __raw_readl(oh->_mpu_rt_va + reg_offs);
 }
 
-void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs)
+void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
-        __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+        if (oh->flags & HWMOD_16BIT_REG)
+                __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+        else
+                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
 }
 
 /**
@@ -1309,7 +1626,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
  * omap_hwmod_enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Enable an omap_hwomd @oh.  Intended to be called by omap_device_enable().
+ * Enable an omap_hwmod @oh.  Intended to be called by omap_device_enable().
  * Returns -EINVAL on error or passes along the return value from _enable().
  */
 int omap_hwmod_enable(struct omap_hwmod *oh)
@@ -1319,9 +1636,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return r;
 }
@@ -1331,7 +1648,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
  * omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Idle an omap_hwomd @oh.  Intended to be called by omap_device_idle().
+ * Idle an omap_hwmod @oh.  Intended to be called by omap_device_idle().
  * Returns -EINVAL on error or passes along the return value from _idle().
  */
 int omap_hwmod_idle(struct omap_hwmod *oh)
@@ -1339,9 +1656,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _omap_hwmod_idle(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1350,7 +1667,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
  * omap_hwmod_shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
- * Shutdown an omap_hwomd @oh.  Intended to be called by
+ * Shutdown an omap_hwmod @oh.  Intended to be called by
  * omap_device_shutdown().  Returns -EINVAL on error or passes along
  * the return value from _shutdown().
  */
@@ -1359,9 +1676,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _shutdown(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1374,9 +1691,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
  */
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _enable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1389,9 +1706,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _disable_clocks(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1421,7 +1738,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
          * Forces posted writes to complete on the OCP thread handling
          * register writes
          */
-        omap_hwmod_readl(oh, oh->class->sysc->sysc_offs);
+        omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
 }
 
 /**
@@ -1430,20 +1747,18 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
  *
  * Under some conditions, a driver may wish to reset the entire device.
  * Called from omap_device code.  Returns -EINVAL on error or passes along
- * the return value from _reset()/_enable().
+ * the return value from _reset().
  */
 int omap_hwmod_reset(struct omap_hwmod *oh)
 {
         int r;
 
-        if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED))
+        if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         r = _reset(oh);
-        if (!r)
-                r = _omap_hwmod_enable(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return r;
 }
@@ -1468,7 +1783,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
         int ret, i;
 
-        ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt;
+        ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
 
         for (i = 0; i < oh->slaves_cnt; i++)
                 ret += oh->slaves[i]->addr_cnt;
@@ -1501,10 +1816,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 r++;
         }
 
-        for (i = 0; i < oh->sdma_chs_cnt; i++) {
-                (res + r)->name = (oh->sdma_chs + i)->name;
-                (res + r)->start = (oh->sdma_chs + i)->dma_ch;
-                (res + r)->end = (oh->sdma_chs + i)->dma_ch;
+        for (i = 0; i < oh->sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
                 (res + r)->flags = IORESOURCE_DMA;
                 r++;
         }
@@ -1644,9 +1959,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _enable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
@@ -1669,14 +1984,92 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
+        mutex_lock(&oh->_mutex);
         _disable_wakeup(oh);
-        mutex_unlock(&omap_hwmod_mutex);
+        mutex_unlock(&oh->_mutex);
 
         return 0;
 }
 
 /**
+ * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to lookup and assert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _assert_hardreset().
+ */
+int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _assert_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
+ * contained in the hwmod module.
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and deassert
+ *
+ * Some IP like dsp, ipu or iva contain processor that require
+ * an HW reset line to be assert / deassert in order to enable fully
+ * the IP.  Returns -EINVAL if @oh is null or if the operation is not
+ * yet supported on this OMAP; otherwise, passes along the return value
+ * from _deassert_hardreset().
+ */
+int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _deassert_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_read_hardreset - read the HW reset line state of submodules
+ * contained in the hwmod module
+ * @oh: struct omap_hwmod *
+ * @name: name of the reset line to look up and read
+ *
+ * Return the current state of the hwmod @oh's reset line named @name:
+ * returns -EINVAL upon parameter error or if this operation
+ * is unsupported on the current OMAP; otherwise, passes along the return
+ * value from _read_hardreset().
+ */
+int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
+{
+        int ret;
+
+        if (!oh)
+                return -EINVAL;
+
+        mutex_lock(&oh->_mutex);
+        ret = _read_hardreset(oh, name);
+        mutex_unlock(&oh->_mutex);
+
+        return ret;
+}
+
+
+/**
  * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
  * @classname: struct omap_hwmod_class name to search for
  * @fn: callback function pointer to call for each hwmod in class @classname
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e8bc04..adf6e3632a2b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,10 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2420 hardware module integration data
@@ -33,6 +35,7 @@ static struct omap_hwmod omap2420_mpu_hwmod;
 static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
+static struct omap_hwmod omap2420_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -71,6 +74,9 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
+static struct omap_hwmod omap2420_uart1_hwmod;
+static struct omap_hwmod omap2420_uart2_hwmod;
+static struct omap_hwmod omap2420_uart3_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2420_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2420_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2420_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
         &omap2420_l3_main__l4_core,
@@ -87,6 +147,9 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
         &omap2420_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
 };
 
 /* L4 CORE */
@@ -165,12 +228,206 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48022000,
+                .pa_end         = 0x4802207f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2420_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap2420_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
+        &omap2420_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2420_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2420_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2420_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2420_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2420_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2420_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
         &omap2420_l4_wkup_hwmod,
         &omap2420_mpu_hwmod,
         &omap2420_iva_hwmod,
+        &omap2420_wd_timer2_hwmod,
+        &omap2420_uart1_hwmod,
+        &omap2420_uart2_hwmod,
+        &omap2420_uart3_hwmod,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628ed287..12d939e456cf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,10 +15,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
+#include "cm-regbits-24xx.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -33,6 +35,7 @@ static struct omap_hwmod omap2430_mpu_hwmod;
 static struct omap_hwmod omap2430_iva_hwmod;
 static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
+static struct omap_hwmod omap2430_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -71,6 +74,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_uart1_hwmod;
+static struct omap_hwmod omap2430_uart2_hwmod;
+static struct omap_hwmod omap2430_uart3_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -79,6 +85,60 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART1_BASE,
+                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2430_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART2_BASE,
+                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2430_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP2_UART3_BASE,
+                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2430_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -104,6 +164,9 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
 /* Slave interfaces on the L4_WKUP interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
 };
 
 /* Master interfaces on the L4_WKUP interconnect */
@@ -165,12 +228,206 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49016000,
+                .pa_end         = 0x4901607f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2430_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap2430_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
+        &omap2430_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap2430_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2430_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+        .slaves         = omap2430_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
+        &omap2_l4_core__uart1,
+};
+
+static struct omap_hwmod omap2430_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
+        &omap2_l4_core__uart2,
+};
+
+static struct omap_hwmod omap2430_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
+        &omap2_l4_core__uart3,
+};
+
+static struct omap_hwmod omap2430_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
         &omap2430_l4_core_hwmod,
         &omap2430_l4_wkup_hwmod,
         &omap2430_mpu_hwmod,
         &omap2430_iva_hwmod,
+        &omap2430_wd_timer2_hwmod,
+        &omap2430_uart1_hwmod,
+        &omap2430_uart2_hwmod,
+        &omap2430_uart3_hwmod,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58ba5e3..cb97ecf0a3f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,10 +17,12 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/serial.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-34xx.h"
+#include "cm-regbits-34xx.h"
 
 /*
  * OMAP3xxx hardware module integration data
@@ -36,6 +38,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -82,6 +85,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
+static struct omap_hwmod omap3xxx_uart1_hwmod;
+static struct omap_hwmod omap3xxx_uart2_hwmod;
+static struct omap_hwmod omap3xxx_uart3_hwmod;
+static struct omap_hwmod omap3xxx_uart4_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
@@ -90,6 +97,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap3xxx_uart4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
@@ -98,6 +177,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
         &omap3xxx_l4_core__l4_wkup,
+        &omap3_l4_core__uart1,
+        &omap3_l4_core__uart2,
 };
 
 /* L4 CORE */
@@ -119,6 +200,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 
 /* Master interfaces on the L4_PER interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
+        &omap3_l4_per__uart3,
+        &omap3_l4_per__uart4,
 };
 
 /* L4 PER */
@@ -197,6 +280,235 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48314000,
+                .pa_end         = 0x4831407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_wd_timer2_hwmod,
+        .clk            = "wdt2_ick",
+        .addr           = omap3xxx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap3xxx_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
+        &omap3xxx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap3xxx_wd_timer_hwmod_class,
+        .main_clk       = "wdt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_WDT2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART common */
+
+static struct omap_hwmod_class_sysconfig uart_sysc = {
+        .rev_offs       = 0x50,
+        .sysc_offs      = 0x54,
+        .syss_offs      = 0x58,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class uart_class = {
+        .name = "uart",
+        .sysc = &uart_sysc,
+};
+
+/* UART1 */
+
+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
+        { .irq = INT_24XX_UART1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
+        &omap3_l4_core__uart1,
+};
+
+static struct omap_hwmod omap3xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = uart1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
+        .sdma_reqs      = uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART2 */
+
+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
+        { .irq = INT_24XX_UART2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
+        &omap3_l4_core__uart2,
+};
+
+static struct omap_hwmod omap3xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = uart2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
+        .sdma_reqs      = uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART3 */
+
+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
+        { .irq = INT_24XX_UART3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
+        &omap3_l4_per__uart3,
+};
+
+static struct omap_hwmod omap3xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = uart3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
+        .sdma_reqs      = uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* UART4 */
+
+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
+        { .irq = INT_36XX_UART4_IRQ, },
+};
+
+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+        &omap3_l4_per__uart4,
+};
+
+static struct omap_hwmod omap3xxx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = uart4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
+        .sdma_reqs      = uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = OMAP3430_PER_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3630_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
+        .class          = &uart_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
@@ -204,6 +516,11 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l4_wkup_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+        &omap3xxx_wd_timer2_hwmod,
+        &omap3xxx_uart1_hwmod,
+        &omap3xxx_uart2_hwmod,
+        &omap3xxx_uart3_hwmod,
+        &omap3xxx_uart4_hwmod,
         NULL,
 };
 
@@ -211,5 +528,3 @@ int __init omap3xxx_hwmod_init(void)
 {
         return omap_hwmod_init(omap3xxx_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
new file mode 100644
index 000000000000..7274db4de487
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -0,0 +1,850 @@
+/*
+ * Hardware modules present on the OMAP44xx chips
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/cpu.h>
+
+#include "omap_hwmod_common_data.h"
+
+#include "cm.h"
+#include "prm-regbits-44xx.h"
+
+/* Base offset for all OMAP4 interrupts external to MPUSS */
+#define OMAP44XX_IRQ_GIC_START  32
+
+/* Base offset for all OMAP4 dma requests */
+#define OMAP44XX_DMA_REQ_START  1
+
+/* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_dmm_hwmod;
+static struct omap_hwmod omap44xx_emif_fw_hwmod;
+static struct omap_hwmod omap44xx_l3_instr_hwmod;
+static struct omap_hwmod omap44xx_l3_main_1_hwmod;
+static struct omap_hwmod omap44xx_l3_main_2_hwmod;
+static struct omap_hwmod omap44xx_l3_main_3_hwmod;
+static struct omap_hwmod omap44xx_l4_abe_hwmod;
+static struct omap_hwmod omap44xx_l4_cfg_hwmod;
+static struct omap_hwmod omap44xx_l4_per_hwmod;
+static struct omap_hwmod omap44xx_l4_wkup_hwmod;
+static struct omap_hwmod omap44xx_mpu_hwmod;
+static struct omap_hwmod omap44xx_mpu_private_hwmod;
+
+/*
+ * Interconnects omap_hwmod structures
+ * hwmods that compose the global OMAP interconnect
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
+        .name = "dmm",
+};
+
+/* dmm interface data */
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dmm slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
+        &omap44xx_l3_main_1__dmm,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod omap44xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap44xx_dmm_hwmod_class,
+        .slaves         = omap44xx_dmm_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
+        .mpu_irqs       = omap44xx_dmm_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'emif_fw' class
+ * instance(s): emif_fw
+ */
+static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
+        .name = "emif_fw",
+};
+
+/* emif_fw interface data */
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+        .master         = &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* emif_fw slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
+        &omap44xx_dmm__emif_fw,
+        &omap44xx_l4_cfg__emif_fw,
+};
+
+static struct omap_hwmod omap44xx_emif_fw_hwmod = {
+        .name           = "emif_fw",
+        .class          = &omap44xx_emif_fw_hwmod_class,
+        .slaves         = omap44xx_emif_fw_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
+        .name = "l3",
+};
+
+/* l3_instr interface data */
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+        .master         = &omap44xx_l3_main_3_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_instr slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
+        &omap44xx_l3_main_3__l3_instr,
+};
+
+static struct omap_hwmod omap44xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_instr_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+        &omap44xx_l3_main_2__l3_main_1,
+        &omap44xx_l4_cfg__l3_main_1,
+        &omap44xx_mpu__l3_main_1,
+};
+
+static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_2 interface data */
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+        &omap44xx_l3_main_1__l3_main_2,
+        &omap44xx_l4_cfg__l3_main_2,
+};
+
+static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l3_main_3 interface data */
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
+        &omap44xx_l3_main_1__l3_main_3,
+        &omap44xx_l3_main_2__l3_main_3,
+        &omap44xx_l4_cfg__l3_main_3,
+};
+
+static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap44xx_l3_hwmod_class,
+        .slaves         = omap44xx_l3_main_3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
+        .name = "l4",
+};
+
+/* l4_abe interface data */
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+        &omap44xx_l3_main_1__l4_abe,
+        &omap44xx_mpu__l4_abe,
+};
+
+static struct omap_hwmod omap44xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_abe_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_cfg interface data */
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_cfg_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
+        &omap44xx_l3_main_1__l4_cfg,
+};
+
+static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_cfg_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_per interface data */
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l4_per_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
+        &omap44xx_l3_main_2__l4_per,
+};
+
+static struct omap_hwmod omap44xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_per_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_wkup interface data */
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l4_wkup_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
+        &omap44xx_l4_cfg__l4_wkup,
+};
+
+static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap44xx_l4_hwmod_class,
+        .slaves         = omap44xx_l4_wkup_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
+        .name = "mpu_bus",
+};
+
+/* mpu_private interface data */
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_mpu_private_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu_private slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
+        &omap44xx_mpu__mpu_private,
+};
+
+static struct omap_hwmod omap44xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap44xx_mpu_bus_hwmod_class,
+        .slaves         = omap44xx_mpu_private_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
+        .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
+        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* mpu master ports */
+static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
+        &omap44xx_mpu__l3_main_1,
+        &omap44xx_mpu__l4_abe,
+        &omap44xx_mpu__dmm,
+};
+
+static struct omap_hwmod omap44xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap44xx_mpu_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
+                },
+        },
+        .masters        = omap44xx_mpu_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+        .name = "wd_timer",
+        .sysc = &omap44xx_wd_timer_sysc,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap44xx_wd_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
+        .name = "uart",
+        .sysc = &omap44xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap44xx_uart1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
+        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+        {
+                .pa_start       = 0x4806a000,
+                .pa_end         = 0x4806a0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
+        &omap44xx_l4_per__uart1,
+};
+
+static struct omap_hwmod omap44xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
+        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
+        .main_clk       = "uart1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart2 */
+static struct omap_hwmod omap44xx_uart2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
+        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+        {
+                .pa_start       = 0x4806c000,
+                .pa_end         = 0x4806c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_wd_timer2_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wd_timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
+        &omap44xx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
+        .main_clk       = "wd_timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* wd_timer3 */
+static struct omap_hwmod omap44xx_wd_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
+        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
+        &omap44xx_l4_per__uart2,
+};
+
+static struct omap_hwmod omap44xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
+        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
+        .main_clk       = "uart2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart3 */
+static struct omap_hwmod omap44xx_uart3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
+        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+        {
+                .pa_start       = 0x48020000,
+                .pa_end         = 0x480200ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49030000,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
+        &omap44xx_l4_per__uart3,
+};
+
+static struct omap_hwmod omap44xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap44xx_uart_hwmod_class,
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+        .mpu_irqs       = omap44xx_uart3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
+        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
+        .main_clk       = "uart3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* uart4 */
+static struct omap_hwmod omap44xx_uart4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
+        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+        {
+                .pa_start       = 0x4806e000,
+                .pa_end         = 0x4806e0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* wd_timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
+};
+
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* uart4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
+        &omap44xx_l4_per__uart4,
+};
+
+static struct omap_hwmod omap44xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap44xx_uart_hwmod_class,
+        .mpu_irqs       = omap44xx_uart4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
+        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
+        .main_clk       = "uart4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+        /* dmm class */
+        &omap44xx_dmm_hwmod,
+        /* emif_fw class */
+        &omap44xx_emif_fw_hwmod,
+        /* l3 class */
+        &omap44xx_l3_instr_hwmod,
+        &omap44xx_l3_main_1_hwmod,
+        &omap44xx_l3_main_2_hwmod,
+        &omap44xx_l3_main_3_hwmod,
+        /* l4 class */
+        &omap44xx_l4_abe_hwmod,
+        &omap44xx_l4_cfg_hwmod,
+        &omap44xx_l4_per_hwmod,
+        &omap44xx_l4_wkup_hwmod,
+        /* mpu_bus class */
+        &omap44xx_mpu_private_hwmod,
+
+        /* mpu class */
+        &omap44xx_mpu_hwmod,
+        /* wd_timer class */
+        &omap44xx_wd_timer2_hwmod,
+        &omap44xx_wd_timer3_hwmod,
+
+        /* uart class */
+        &omap44xx_uart1_hwmod,
+        &omap44xx_uart2_hwmod,
+        &omap44xx_uart3_hwmod,
+        &omap44xx_uart4_hwmod,
+        NULL,
+};
+
+int __init omap44xx_hwmod_init(void)
+{
+        return omap_hwmod_init(omap44xx_hwmods);
+}
+
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 723b44e252fd..5e81517a7af2 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -31,12 +31,17 @@
 #include <plat/board.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
+#include <plat/dmtimer.h>
 
 #include "prm.h"
 #include "cm.h"
 #include "pm.h"
 
 int omap2_pm_debug;
+u32 enable_off_mode;
+u32 sleep_while_idle;
+u32 wakeup_timer_seconds;
+u32 wakeup_timer_milliseconds;
 
 #define DUMP_PRM_MOD_REG(mod, reg)    \
         regs[reg_count].name = #mod "." #reg; \
@@ -162,7 +167,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
 
 static void pm_dbg_regset_store(u32 *ptr);
 
-struct dentry *pm_dbg_dir;
+static struct dentry *pm_dbg_dir;
 
 static int pm_dbg_init_done;
 
@@ -349,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
         pwrdm->timer = t;
 }
 
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+
+        if (!seconds && !milliseconds)
+                return;
+
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
+
 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
 {
         struct seq_file *s = (struct seq_file *)user;
@@ -494,8 +516,10 @@ int pm_dbg_regset_init(int reg_set)
 
 static int pwrdm_suspend_get(void *data, u64 *val)
 {
-        int ret;
-        ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
+        int ret = -EINVAL;
+
+        if (cpu_is_omap34xx())
+                ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
         *val = ret;
 
         if (ret >= 0)
@@ -505,7 +529,10 @@ static int pwrdm_suspend_get(void *data, u64 *val)
 
 static int pwrdm_suspend_set(void *data, u64 val)
 {
-        return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
+        if (cpu_is_omap34xx())
+                return omap3_pm_set_suspend_state(
+                        (struct powerdomain *)data, (int)val);
+        return -EINVAL;
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
@@ -553,8 +580,10 @@ static int option_set(void *data, u64 val)
 
         *option = val;
 
-        if (option == &enable_off_mode)
-                omap3_pm_off_mode_enable(val);
+        if (option == &enable_off_mode) {
+                if (cpu_is_omap34xx())
+                        omap3_pm_off_mode_enable(val);
+        }
 
         return 0;
 }
@@ -609,6 +638,9 @@ static int __init pm_dbg_init(void)
                                    &sleep_while_idle, &pm_dbg_option_fops);
         (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
                                    &wakeup_timer_seconds, &pm_dbg_option_fops);
+        (void) debugfs_create_file("wakeup_timer_milliseconds",
+                        S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
+                        &pm_dbg_option_fops);
         pm_dbg_init_done = 1;
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 68f9f2e95891..59ca03b0e691 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -18,11 +18,15 @@
 #include <plat/omap_device.h>
 #include <plat/common.h>
 
+#include <plat/powerdomain.h>
+#include <plat/clockdomain.h>
+
 static struct omap_device_pm_latency *pm_lats;
 
 static struct device *mpu_dev;
-static struct device *dsp_dev;
+static struct device *iva_dev;
 static struct device *l3_dev;
+static struct device *dsp_dev;
 
 struct device *omap2_get_mpuss_device(void)
 {
@@ -30,10 +34,10 @@ struct device *omap2_get_mpuss_device(void)
         return mpu_dev;
 }
 
-struct device *omap2_get_dsp_device(void)
+struct device *omap2_get_iva_device(void)
 {
-        WARN_ON_ONCE(!dsp_dev);
-        return dsp_dev;
+        WARN_ON_ONCE(!iva_dev);
+        return iva_dev;
 }
 
 struct device *omap2_get_l3_device(void)
@@ -42,6 +46,13 @@ struct device *omap2_get_l3_device(void)
         return l3_dev;
 }
 
+struct device *omap4_get_dsp_device(void)
+{
+        WARN_ON_ONCE(!dsp_dev);
+        return dsp_dev;
+}
+EXPORT_SYMBOL(omap4_get_dsp_device);
+
 /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
 static int _init_omap_device(char *name, struct device **new_dev)
 {
@@ -69,8 +80,60 @@ static int _init_omap_device(char *name, struct device **new_dev)
 static void omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu", &mpu_dev);
-        _init_omap_device("iva", &dsp_dev);
-        _init_omap_device("l3_main", &l3_dev);
+        _init_omap_device("iva", &iva_dev);
+        if (cpu_is_omap44xx()) {
+                _init_omap_device("l3_main_1", &l3_dev);
+                _init_omap_device("dsp", &dsp_dev);
+        } else {
+                _init_omap_device("l3_main", &l3_dev);
+        }
+}
+
+/*
+ * This sets pwrdm state (other than mpu & core. Currently only ON &
+ * RET are supported. Function is assuming that clkdm doesn't have
+ * hw_sup mode enabled.
+ */
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+{
+        u32 cur_state;
+        int sleep_switch = 0;
+        int ret = 0;
+
+        if (pwrdm == NULL || IS_ERR(pwrdm))
+                return -EINVAL;
+
+        while (!(pwrdm->pwrsts & (1 << state))) {
+                if (state == PWRDM_POWER_OFF)
+                        return ret;
+                state--;
+        }
+
+        cur_state = pwrdm_read_next_pwrst(pwrdm);
+        if (cur_state == state)
+                return ret;
+
+        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
+                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+                sleep_switch = 1;
+                pwrdm_wait_transition(pwrdm);
+        }
+
+        ret = pwrdm_set_next_pwrst(pwrdm, state);
+        if (ret) {
+                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
+                       pwrdm->name);
+                goto err;
+        }
+
+        if (sleep_switch) {
+                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+                pwrdm_wait_transition(pwrdm);
+                pwrdm_state_switch(pwrdm);
+        }
+
+err:
+        return ret;
 }
 
 static int __init omap2_common_pm_init(void)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece23fc8..0d75bfd1fdbe 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -13,14 +13,11 @@
 
 #include <plat/powerdomain.h>
 
-extern u32 enable_off_mode;
-extern u32 sleep_while_idle;
-
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
-extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
+extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 
 struct cpuidle_params {
@@ -48,10 +45,16 @@ extern struct omap_dm_timer *gptimer_wakeup;
 
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
+extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
 extern int omap2_pm_debug;
+extern u32 enable_off_mode;
+extern u32 sleep_while_idle;
 #else
 #define omap2_pm_dump(mode, resume, us)         do {} while (0);
+#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
 #define omap2_pm_debug                          0
+#define enable_off_mode 0
+#define sleep_while_idle 0
 #endif
 
 #if defined(CONFIG_CPU_IDLE)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 6aeedeacdad8..a40457d81927 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -38,7 +38,6 @@
 #include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/control.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
@@ -48,6 +47,7 @@
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "pm.h"
+#include "control.h"
 
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
@@ -245,6 +245,8 @@ static int omap2_can_sleep(void)
 {
         if (omap2_fclks_active())
                 return 0;
+        if (!omap_uart_can_sleep())
+                return 0;
         if (osc_ck->usecount > 1)
                 return 0;
         if (omap_dma_running())
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7b03426c72a3..75c0cd13ad8e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -32,13 +32,11 @@
 #include <plat/sram.h>
 #include <plat/clockdomain.h>
 #include <plat/powerdomain.h>
-#include <plat/control.h>
 #include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
-#include <plat/dmtimer.h>
 
 #include <asm/tlbflush.h>
 
@@ -49,16 +47,12 @@
 #include "prm.h"
 #include "pm.h"
 #include "sdrc.h"
+#include "control.h"
 
 /* Scratchpad offsets */
-#define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
-#define OMAP343X_TABLE_VALUE_OFFSET        0x30
-#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
-
-u32 enable_off_mode;
-u32 sleep_while_idle;
-u32 wakeup_timer_seconds;
-u32 wakeup_timer_milliseconds;
+#define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
+#define OMAP343X_TABLE_VALUE_OFFSET        0xc0
+#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
 struct power_state {
         struct powerdomain *pwrdm;
@@ -316,7 +310,7 @@ static void restore_control_register(u32 val)
 /* Function to restore the table entry that was modified for enabling MMU */
 static void restore_table_entry(void)
 {
-        u32 *scratchpad_address;
+        void __iomem *scratchpad_address;
         u32 previous_value, control_reg_value;
         u32 *address;
 
@@ -351,7 +345,6 @@ void omap_sram_idle(void)
         int core_next_state = PWRDM_POWER_ON;
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
-        int per_state_modified = 0;
 
         if (!_omap_sram_idle)
                 return;
@@ -385,9 +378,9 @@ void omap_sram_idle(void)
         /* Enable IO-PAD and IO-CHAIN wakeups */
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-        if (omap3_has_io_wakeup() && \
-                        (per_next_state < PWRDM_POWER_ON ||
-                        core_next_state < PWRDM_POWER_ON)) {
+        if (omap3_has_io_wakeup() &&
+            (per_next_state < PWRDM_POWER_ON ||
+             core_next_state < PWRDM_POWER_ON)) {
                 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
@@ -395,20 +388,12 @@ void omap_sram_idle(void)
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
                 omap_uart_prepare_idle(2);
+                omap_uart_prepare_idle(3);
                 omap2_gpio_prepare_for_idle(per_next_state);
-                if (per_next_state == PWRDM_POWER_OFF) {
-                        if (core_next_state == PWRDM_POWER_ON) {
-                                per_next_state = PWRDM_POWER_RET;
-                                pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
-                                per_state_modified = 1;
-                        } else
+                if (per_next_state == PWRDM_POWER_OFF)
                                 omap3_per_save_context();
-                }
         }
 
-        if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
-                omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
-
         /* CORE */
         if (core_next_state < PWRDM_POWER_ON) {
                 omap_uart_prepare_idle(0);
@@ -475,8 +460,7 @@ void omap_sram_idle(void)
                 if (per_prev_state == PWRDM_POWER_OFF)
                         omap3_per_restore_context();
                 omap_uart_resume_idle(2);
-                if (per_state_modified)
-                        pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
+                omap_uart_resume_idle(3);
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -501,51 +485,6 @@ int omap3_can_sleep(void)
         return 1;
 }
 
-/* This sets pwrdm state (other than mpu & core. Currently only ON &
- * RET are supported. Function is assuming that clkdm doesn't have
- * hw_sup mode enabled. */
-int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
-{
-        u32 cur_state;
-        int sleep_switch = 0;
-        int ret = 0;
-
-        if (pwrdm == NULL || IS_ERR(pwrdm))
-                return -EINVAL;
-
-        while (!(pwrdm->pwrsts & (1 << state))) {
-                if (state == PWRDM_POWER_OFF)
-                        return ret;
-                state--;
-        }
-
-        cur_state = pwrdm_read_next_pwrst(pwrdm);
-        if (cur_state == state)
-                return ret;
-
-        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                sleep_switch = 1;
-                pwrdm_wait_transition(pwrdm);
-        }
-
-        ret = pwrdm_set_next_pwrst(pwrdm, state);
-        if (ret) {
-                printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
-                       pwrdm->name);
-                goto err;
-        }
-
-        if (sleep_switch) {
-                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
-                pwrdm_wait_transition(pwrdm);
-                pwrdm_state_switch(pwrdm);
-        }
-
-err:
-        return ret;
-}
-
 static void omap3_pm_idle(void)
 {
         local_irq_disable();
@@ -567,23 +506,6 @@ out:
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state;
 
-static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-
-        if (!seconds && !milliseconds)
-                return;
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
-
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -604,7 +526,7 @@ static int omap3_pm_suspend(void)
                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
         /* Set ones wanted by suspend */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
+                if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
                         goto restore;
                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
                         goto restore;
@@ -625,7 +547,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -756,6 +678,14 @@ static void __init omap3_d2d_idle(void)
 
 static void __init prcm_setup_regs(void)
 {
+        u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_AUTO_UART4_MASK : 0;
+        u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_EN_UART4_MASK : 0;
+        u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
+                                        OMAP3630_GRPSEL_UART4_MASK : 0;
+
+
         /* XXX Reset all wkdeps. This should be done when initializing
          * powerdomains */
         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -842,6 +772,7 @@ static void __init prcm_setup_regs(void)
                 CM_AUTOIDLE);
 
         cm_write_mod_reg(
+                omap3630_auto_uart4_mask |
                 OMAP3430_AUTO_GPIO6_MASK |
                 OMAP3430_AUTO_GPIO5_MASK |
                 OMAP3430_AUTO_GPIO4_MASK |
@@ -918,14 +849,16 @@ static void __init prcm_setup_regs(void)
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
+        prm_write_mod_reg(omap3630_en_uart4_mask |
+                          OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
                           OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
+        prm_write_mod_reg(omap3630_grpsel_uart4_mask |
+                          OMAP3430_GRPSEL_GPIO2_MASK |
                           OMAP3430_GRPSEL_GPIO3_MASK |
                           OMAP3430_GRPSEL_GPIO4_MASK |
                           OMAP3430_GRPSEL_GPIO5_MASK |
@@ -974,7 +907,7 @@ void omap3_pm_off_mode_enable(int enable)
 
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 pwrst->next_state = state;
-                set_pwrdm_state(pwrst->pwrdm, state);
+                omap_set_pwrdm_state(pwrst->pwrdm, state);
         }
 }
 
@@ -1019,7 +952,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
         if (pwrdm_has_hdwr_sar(pwrdm))
                 pwrdm_enable_hdwr_sar(pwrdm);
 
-        return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 }
 
 /*
@@ -1029,9 +962,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        clkdm_clear_all_wkdeps(clkdm);
-        clkdm_clear_all_sleepdeps(clkdm);
-
         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
                 omap2_clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
new file mode 100644
index 000000000000..784989f8f2f5
--- /dev/null
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -0,0 +1,85 @@
+/*
+ * Runtime PM support code for OMAP
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int omap_pm_runtime_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int r, ret = 0;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+
+        if (!ret && dev->parent == &omap_device_parent) {
+                r = omap_device_idle(pdev);
+                WARN_ON(r);
+        }
+
+        return ret;
+};
+
+int omap_pm_runtime_resume(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int r;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        if (dev->parent == &omap_device_parent) {
+                r = omap_device_enable(pdev);
+                WARN_ON(r);
+        }
+
+        return pm_generic_runtime_resume(dev);
+};
+#else
+#define omap_pm_runtime_suspend NULL
+#define omap_pm_runtime_resume NULL
+#endif /* CONFIG_PM_RUNTIME */
+
+static int __init omap_pm_runtime_init(void)
+{
+        const struct dev_pm_ops *pm;
+        struct dev_pm_ops *omap_pm;
+
+        pm = platform_bus_get_pm_ops();
+        if (!pm) {
+                pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
+                        __func__);
+                return -ENODEV;
+        }
+
+        omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
+        if (!omap_pm) {
+                pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        omap_pm->runtime_suspend = omap_pm_runtime_suspend;
+        omap_pm->runtime_resume = omap_pm_runtime_resume;
+
+        platform_bus_set_pm_ops(omap_pm);
+
+        return 0;
+}
+core_initcall(omap_pm_runtime_init);
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c7219513472a..9c01b55d6102 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
         .prcm_offs        = OMAP4430_PRM_DSS_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 1,
         .pwrsts_mem_ret = {
                 [0] = PWRDM_POWER_OFF,  /* dss_mem */
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 995b7edbf18d..298a22a754e2 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -382,6 +382,9 @@
 #define OMAP3430_EN_MPU_SHIFT                           1
 
 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
+
+#define OMAP3630_EN_UART4_MASK                          (1 << 18)
+#define OMAP3630_EN_UART4_SHIFT                         18
 #define OMAP3430_EN_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_EN_GPIO6_SHIFT                         17
 #define OMAP3430_EN_GPIO5_MASK                          (1 << 16)
@@ -422,6 +425,8 @@
 #define OMAP3430_EN_MCBSP2_SHIFT                        0
 
 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
+#define OMAP3630_ST_UART4_SHIFT                         18
+#define OMAP3630_ST_UART4_MASK                          (1 << 18)
 #define OMAP3430_ST_GPIO6_SHIFT                         17
 #define OMAP3430_ST_GPIO6_MASK                          (1 << 17)
 #define OMAP3430_ST_GPIO5_SHIFT                         16
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c20137497c92..a51846e3a6fa 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -26,13 +26,14 @@
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
-#include <plat/control.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
+#include "prm-regbits-44xx.h"
+#include "control.h"
 
 static void __iomem *prm_base;
 static void __iomem *cm_base;
@@ -118,7 +119,7 @@ struct omap3_prcm_regs {
         u32 wkup_pm_wken;
 };
 
-struct omap3_prcm_regs prcm_context;
+static struct omap3_prcm_regs prcm_context;
 
 u32 omap_prcm_get_reset_sources(void)
 {
@@ -161,8 +162,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
                 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
                                                  OMAP2_RM_RSTCTRL);
         if (cpu_is_omap44xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                                 OMAP4_RM_RSTCTRL);
+                prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
+                                     prcm_offs, OMAP4_RM_RSTCTRL);
 }
 
 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
@@ -215,6 +216,30 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
         return v;
 }
 
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= ~mask;
+        v |= bits;
+        __raw_writel(v, reg);
+
+        return v;
+}
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 7fd6023edf96..9e63cb743a97 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -122,6 +122,7 @@
 #define OMAP3430_MEMRETSTATE_MASK                       (1 << 8)
 
 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
+#define OMAP3630_GRPSEL_UART4_MASK                      (1 << 18)
 #define OMAP3430_GRPSEL_GPIO6_MASK                      (1 << 17)
 #define OMAP3430_GRPSEL_GPIO5_MASK                      (1 << 16)
 #define OMAP3430_GRPSEL_GPIO4_MASK                      (1 << 15)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 597be4a2b9ff..25b19b610177 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -1,8 +1,8 @@
 /*
  * OMAP44xx Power Management register bits
  *
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
  * Rajendra Nayak (rnayak@ti.com)
@@ -30,587 +30,611 @@
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                1
-#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 (1 << 1)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              2
-#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               (1 << 2)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  31
-#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
+#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   (1 << 31)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   (1 << 7)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  7
-#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
+#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   (1 << 7)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   2
-#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   1
-#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    (1 << 1)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_AESSMEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_AESSMEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_AESSMEM_STATEST_SHIFT                                  4
-#define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_AESSMEM_STATEST_MASK                                   (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_AIPOFF_SHIFT                                           8
-#define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
+#define OMAP4430_AIPOFF_MASK                                            (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             0
-#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              (0x3 << 0)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              4
-#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               (0x3 << 4)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              2
-#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               (0x3 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_RA_ERR_SHIFT                                      25
+#define OMAP4430_BYPS_RA_ERR_MASK                                       (1 << 25)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_SA_ERR_SHIFT                                      24
+#define OMAP4430_BYPS_SA_ERR_MASK                                       (1 << 24)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT                                 26
+#define OMAP4430_BYPS_TIMEOUT_ERR_MASK                                  (1 << 26)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_C2C_RST_SHIFT                                          10
+#define OMAP4430_C2C_RST_MASK                                           (1 << 10)
 
 /* Used by PM_CAM_PWRSTCTRL */
 #define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_CAM_PWRSTST */
 #define OMAP4430_CAM_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_CAM_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_CLKREQCTRL */
 #define OMAP4430_CLKREQ_COND_SHIFT                                      0
-#define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
+#define OMAP4430_CLKREQ_COND_MASK                                       (0x7 << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_CMD */
 #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   4
-#define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_CMD_VDD_CORE_L_MASK                                    (1 << 4)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    12
-#define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
+#define OMAP4430_CMD_VDD_IVA_L_MASK                                     (1 << 12)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    17
-#define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
+#define OMAP4430_CMD_VDD_MPU_L_MASK                                     (1 << 17)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              18
-#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               (0x3 << 18)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             9
-#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              (1 << 9)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              6
-#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
+#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          16
-#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           (0x3 << 16)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         8
-#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          (1 << 8)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          4
-#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_CUSTOM_SHIFT                                           6
+#define OMAP4430_CUSTOM_MASK                                            (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_DATA_SHIFT                                             16
-#define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_DATA_MASK                                              (0xff << 16)
 
 /* Used by PRM_DEVICE_OFF_CTRL */
 #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                0
-#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 (1 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_DFILTEREN_SHIFT                                        6
-#define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
+#define OMAP4430_DFILTEREN_MASK                                         (1 << 6)
 
-/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT                               0
+#define OMAP4430_DISABLE_RTA_EXPORT_MASK                                (1 << 0)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 (1 << 4)
 
-/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                4
-#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                (1 << 0)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               0
-#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             6
-#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                2
-#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                1
-#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 (1 << 1)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                3
-#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              (1 << 7)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             7
-#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
-
-/* Used by PRM_IRQENABLE_MPU */
-#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
-
-/* Used by PRM_IRQSTATUS_MPU */
-#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                5
-#define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              (1 << 7)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_DSS_PWRSTCTRL */
 #define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_PWRSTST */
 #define OMAP4430_DSS_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_DSS_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             20
-#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              (0x3 << 20)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            10
-#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             (1 << 10)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             8
-#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              (0x3 << 8)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          22
-#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           (0x3 << 22)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         11
-#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          (1 << 11)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          10
-#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           (0x3 << 10)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_EMULATION_RST_SHIFT                                    0
-#define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_EMULATION_RST_MASK                                     (1 << 0)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST1ST_SHIFT                                 3
-#define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_EMULATION_RST1ST_MASK                                  (1 << 3)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_EMULATION_RST2ST_SHIFT                                 4
-#define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_EMULATION_RST2ST_MASK                                  (1 << 4)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            3
-#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             (1 << 3)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            4
-#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             (1 << 4)
 
 /* Used by PM_EMU_PWRSTCTRL */
 #define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 16
-#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_EMU_PWRSTST */
 #define OMAP4430_EMU_BANK_STATEST_SHIFT                                 4
-#define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
-
-/*
- * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
- * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
- */
-#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                0
-#define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_EMU_BANK_STATEST_MASK                                  (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC1_SHIFT                                          3
-#define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
+#define OMAP4430_ENFUNC1_EXPORT_SHIFT                                   3
+#define OMAP4430_ENFUNC1_EXPORT_MASK                                    (1 << 3)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
-#define OMAP4430_ENFUNC3_SHIFT                                          5
-#define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
+#define OMAP4430_ENFUNC3_EXPORT_SHIFT                                   5
+#define OMAP4430_ENFUNC3_EXPORT_MASK                                    (1 << 5)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC4_SHIFT                                          6
-#define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
+#define OMAP4430_ENFUNC4_MASK                                           (1 << 6)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
  * PRM_LDO_SRAM_MPU_SETUP
  */
 #define OMAP4430_ENFUNC5_SHIFT                                          7
-#define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
+#define OMAP4430_ENFUNC5_MASK                                           (1 << 7)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERRORGAIN_SHIFT                                        16
-#define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
+#define OMAP4430_ERRORGAIN_MASK                                         (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_ERROROFFSET_SHIFT                                      24
-#define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
+#define OMAP4430_ERROROFFSET_MASK                                       (0xff << 24)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                5
-#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 (1 << 5)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_FORCEUPDATE_SHIFT                                      1
-#define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_FORCEUPDATE_MASK                                       (1 << 1)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  8
-#define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
+#define OMAP4430_FORCEUPDATEWAIT_MASK                                   (0xffffff << 8)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
 #define OMAP4430_FORCEWKUP_EN_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_EN_MASK                                      (1 << 10)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
 #define OMAP4430_FORCEWKUP_ST_SHIFT                                     10
-#define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
+#define OMAP4430_FORCEWKUP_ST_MASK                                      (1 << 10)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_FUNC_SHIFT                                             16
+#define OMAP4430_FUNC_MASK                                              (0xfff << 16)
 
 /* Used by PM_GFX_PWRSTCTRL */
 #define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_GFX_PWRSTST */
 #define OMAP4430_GFX_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_GFX_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  0
-#define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_GLOBAL_COLD_RST_MASK                                   (1 << 0)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               1
-#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_GLOBAL_WUEN_SHIFT                                      16
-#define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
+#define OMAP4430_GLOBAL_WUEN_MASK                                       (1 << 16)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMCODE_SHIFT                                          0
-#define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
+#define OMAP4430_HSMCODE_MASK                                           (0x7 << 0)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_HSMODEEN_SHIFT                                         3
-#define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
+#define OMAP4430_HSMODEEN_MASK                                          (1 << 3)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLH_SHIFT                                           16
-#define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_HSSCLH_MASK                                            (0xff << 16)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_HSSCLL_SHIFT                                           24
-#define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_HSSCLL_MASK                                            (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  16
-#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   (0x3 << 16)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 8
-#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  (1 << 8)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_HWA_MEM_STATEST_SHIFT                                  4
-#define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+#define OMAP4430_HWA_MEM_STATEST_MASK                                   (0x3 << 4)
 
 /* Used by RM_MPU_RSTST */
 #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               1
-#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                (1 << 1)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                5
-#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 (1 << 5)
 
 /* Used by RM_DUCATI_RSTST */
 #define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                6
-#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 (1 << 6)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           5
-#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            (1 << 5)
 
 /* Used by RM_IVAHD_RSTST */
 #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           6
-#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            (1 << 6)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_ICEPICK_RST_SHIFT                                      9
-#define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
+#define OMAP4430_ICEPICK_RST_MASK                                       (1 << 9)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVDD_SHIFT                                          2
-#define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
+#define OMAP4430_INITVDD_MASK                                           (1 << 2)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_INITVOLTAGE_SHIFT                                      8
-#define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
+#define OMAP4430_INITVOLTAGE_MASK                                       (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_INTRANSITION_SHIFT                                     20
-#define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
+#define OMAP4430_INTRANSITION_MASK                                      (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_IO_EN_SHIFT                                            9
-#define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_EN_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_IO_ON_STATUS_SHIFT                                     5
-#define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
+#define OMAP4430_IO_ON_STATUS_MASK                                      (1 << 5)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_IO_ST_SHIFT                                            9
-#define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
+#define OMAP4430_IO_ST_MASK                                             (1 << 9)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  0
-#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   (1 << 0)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOCLK_STATUS_SHIFT                                    1
-#define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
+#define OMAP4430_ISOCLK_STATUS_MASK                                     (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_ISOOVR_EXTEND_SHIFT                                    4
-#define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
+#define OMAP4430_ISOOVR_EXTEND_MASK                                     (1 << 4)
 
 /* Used by PRM_IO_COUNT */
 #define OMAP4430_ISO_2_ON_TIME_SHIFT                                    0
-#define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
+#define OMAP4430_ISO_2_ON_TIME_MASK                                     (0xff << 0)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             16
-#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              (0x3 << 16)
 
 /* Used by PM_L3INIT_PWRSTCTRL */
 #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            8
-#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             (1 << 8)
 
 /* Used by PM_L3INIT_PWRSTST */
 #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             4
-#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
+#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              (0x3 << 4)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
+ */
+#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT                            24
+#define OMAP4430_LASTPOWERSTATEENTERED_MASK                             (0x3 << 24)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL,
- * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
- * PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOGICRETSTATE_SHIFT                                    2
-#define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
+#define OMAP4430_LOGICRETSTATE_MASK                                     (1 << 2)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_LOGICSTATEST_SHIFT                                     2
-#define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
+#define OMAP4430_LOGICSTATEST_MASK                                      (1 << 2)
 
 /*
- * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT,
- * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
- * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
- * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
- * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
- * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
- * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
- * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
- * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
- * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
- * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
- * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
- * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
- * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
- * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
  * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
  * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
  * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
- * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT,
- * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT,
- * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT,
- * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT,
- * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT,
- * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT,
- * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT,
- * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
- * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
- * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT,
- * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
- * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
- * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
- * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT,
- * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
- * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
+ * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
+ * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
+ * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
+ * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
+ * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
+ * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
+ * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
+ * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
+ * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
+ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
+ * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
+ * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
+ * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
+ * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
+ * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
+ * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
+ * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
+ * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  0
-#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   (1 << 0)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
- * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
+ * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
+ * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
  * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
  * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
- * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT,
- * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
- * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT,
- * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT,
- * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT,
- * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT,
- * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT,
- * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT,
- * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
- * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
- * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
- * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
+ * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
+ * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
  */
 #define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  1
-#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
+#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   (1 << 1)
 
 /* Used by RM_ABE_AESS_CONTEXT */
 #define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   (1 << 8)
 
 /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
 #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           8
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            (1 << 8)
 
 /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       9
-#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        (1 << 9)
 
 /* Used by RM_L3_2_OCMC_RAM_CONTEXT */
 #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              8
-#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               (1 << 8)
 
 /*
  * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
  * RM_SDMA_SDMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          8
-#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           (1 << 8)
 
 /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
 #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             9
-#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              (1 << 9)
 
 /* Used by RM_DUCATI_DUCATI_CONTEXT */
 #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          8
-#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           (1 << 8)
 
 /* Used by RM_EMU_DEBUGSS_CONTEXT */
 #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 8
-#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  (1 << 8)
 
 /* Used by RM_GFX_GFX_CONTEXT */
 #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
@@ -620,19 +644,19 @@
  * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
  */
 #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             8
-#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   8
-#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    (1 << 8)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   9
-#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    (1 << 9)
 
 /* Used by RM_MPU_MPU_CONTEXT */
 #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  10
-#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   (1 << 10)
 
 /*
  * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
@@ -640,14 +664,14 @@
  * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
  */
 #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         8
-#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          (1 << 8)
 
 /*
  * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
  * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
  */
 #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                8
-#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 (1 << 8)
 
 /*
  * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
@@ -655,245 +679,237 @@
  * RM_L4SEC_CRYPTODMA_CONTEXT
  */
 #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            8
-#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             (1 << 8)
 
 /* Used by RM_IVAHD_SL2_CONTEXT */
 #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  8
-#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  (1 << 8)
 
 /* Used by RM_IVAHD_IVAHD_CONTEXT */
 #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  (1 << 9)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               10
-#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                (1 << 10)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 8
-#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  (1 << 8)
 
 /* Used by RM_TESLA_TESLA_CONTEXT */
 #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 9
-#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  (1 << 9)
 
 /* Used by RM_WKUP_SARRAM_CONTEXT */
 #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                8
-#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 (1 << 8)
 
 /*
- * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
- * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
- * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
+ * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              4
-#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
-
-/* Used by PM_CORE_PWRSTCTRL */
-#define OMAP4430_MEMORYCHANGE_SHIFT                                     3
-#define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               (1 << 4)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_READY_SHIFT                                      1
-#define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
+#define OMAP4430_MODEM_READY_MASK                                       (1 << 1)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               9
-#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                (1 << 9)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   16
-#define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
+#define OMAP4430_MODEM_SLEEP_ST_MASK                                    (1 << 16)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   8
-#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    (1 << 8)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   16
-#define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
+#define OMAP4430_MPU_L1_ONSTATE_MASK                                    (0x3 << 16)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  8
-#define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
+#define OMAP4430_MPU_L1_RETSTATE_MASK                                   (1 << 8)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L1_STATEST_SHIFT                                   4
-#define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
+#define OMAP4430_MPU_L1_STATEST_MASK                                    (0x3 << 4)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   18
-#define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
+#define OMAP4430_MPU_L2_ONSTATE_MASK                                    (0x3 << 18)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  9
-#define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
+#define OMAP4430_MPU_L2_RETSTATE_MASK                                   (1 << 9)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_L2_STATEST_SHIFT                                   6
-#define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
+#define OMAP4430_MPU_L2_STATEST_MASK                                    (0x3 << 6)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  20
-#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
+#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   (0x3 << 20)
 
 /* Used by PM_MPU_PWRSTCTRL */
 #define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 10
-#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
+#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  (1 << 10)
 
 /* Used by PM_MPU_PWRSTST */
 #define OMAP4430_MPU_RAM_STATEST_SHIFT                                  8
-#define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_MPU_RAM_STATEST_MASK                                   (0x3 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            2
-#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             (1 << 2)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_MPU_WDT_RST_SHIFT                                      3
-#define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
+#define OMAP4430_MPU_WDT_RST_MASK                                       (1 << 3)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         18
-#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          (0x3 << 18)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        9
-#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         (1 << 9)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         6
-#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          (0x3 << 6)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            24
-#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             (0x3 << 24)
 
 /* Used by PM_CORE_PWRSTCTRL */
 #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           12
-#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            (1 << 12)
 
 /* Used by PM_CORE_PWRSTST */
 #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            12
-#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
+#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             (0x3 << 12)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_OFF_SHIFT                                              0
-#define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
-
-/* Used by PRM_LDO_BANDGAP_CTRL */
-#define OMAP4430_OFF_ENABLE_SHIFT                                       0
-#define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_OFF_MASK                                               (0xff << 0)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ON_SHIFT                                               24
-#define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
+#define OMAP4430_ON_MASK                                                (0xff << 24)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_ONLP_SHIFT                                             16
-#define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
+#define OMAP4430_ONLP_MASK                                              (0xff << 16)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_CHANGE_SHIFT                                       2
-#define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
+#define OMAP4430_OPP_CHANGE_MASK                                        (1 << 2)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_OPP_SEL_SHIFT                                          0
-#define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
+#define OMAP4430_OPP_SEL_MASK                                           (0x3 << 0)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 0
-#define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
+#define OMAP4430_PCHARGECNT_VALUE_MASK                                  (0x3f << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PCHARGE_TIME_SHIFT                                     0
-#define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
+#define OMAP4430_PCHARGE_TIME_MASK                                      (0xff << 0)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                20
-#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
+#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 (0x3 << 20)
 
 /* Used by PM_ABE_PWRSTCTRL */
 #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               10
-#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                (1 << 10)
 
 /* Used by PM_ABE_PWRSTST */
 #define OMAP4430_PERIPHMEM_STATEST_SHIFT                                8
-#define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
+#define OMAP4430_PERIPHMEM_STATEST_MASK                                 (0x3 << 8)
 
 /* Used by PRM_PHASE1_CNDP */
 #define OMAP4430_PHASE1_CNDP_SHIFT                                      0
-#define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
+#define OMAP4430_PHASE1_CNDP_MASK                                       (0xffffffff << 0)
 
 /* Used by PRM_PHASE2A_CNDP */
 #define OMAP4430_PHASE2A_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2A_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PHASE2B_CNDP */
 #define OMAP4430_PHASE2B_CNDP_SHIFT                                     0
-#define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
+#define OMAP4430_PHASE2B_CNDP_MASK                                      (0xffffffff << 0)
 
 /* Used by PRM_PSCON_COUNT */
 #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            8
-#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             (0xff << 8)
 
 /*
- * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL,
- * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL,
- * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
- * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
  */
 #define OMAP4430_POWERSTATE_SHIFT                                       0
-#define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
+#define OMAP4430_POWERSTATE_MASK                                        (0x3 << 0)
 
 /*
- * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
- * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
- * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
+ * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
  */
 #define OMAP4430_POWERSTATEST_SHIFT                                     0
-#define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
+#define OMAP4430_POWERSTATEST_MASK                                      (0x3 << 0)
 
 /* Used by PRM_PWRREQCTRL */
 #define OMAP4430_PWRREQ_COND_SHIFT                                      0
-#define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
+#define OMAP4430_PWRREQ_COND_MASK                                       (0x3 << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 3
-#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
+#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  (1 << 3)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  11
-#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
+#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   (1 << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  20
-#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
+#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   (1 << 20)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   2
-#define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
+#define OMAP4430_RAC_VDD_CORE_L_MASK                                    (1 << 2)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    10
-#define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
+#define OMAP4430_RAC_VDD_IVA_L_MASK                                     (1 << 10)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    19
-#define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
+#define OMAP4430_RAC_VDD_MPU_L_MASK                                     (1 << 19)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -901,7 +917,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  16
-#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
+#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   (0x3f << 16)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -909,7 +925,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                24
-#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
+#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 (0x3 << 24)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -917,7 +933,7 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_COUNT_SHIFT                                    0
-#define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
+#define OMAP4430_RAMP_UP_COUNT_MASK                                     (0x3f << 0)
 
 /*
  * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -925,1281 +941,1381 @@
  * PRM_VOLTSETUP_MPU_RET_SLEEP
  */
 #define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  8
-#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
+#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   (0x3 << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   1
-#define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
+#define OMAP4430_RAV_VDD_CORE_L_MASK                                    (1 << 1)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    9
-#define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
+#define OMAP4430_RAV_VDD_IVA_L_MASK                                     (1 << 9)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    18
-#define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
+#define OMAP4430_RAV_VDD_MPU_L_MASK                                     (1 << 18)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_REGADDR_SHIFT                                          8
-#define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
+#define OMAP4430_REGADDR_MASK                                           (0xff << 8)
 
 /*
  * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
  * PRM_VC_VAL_CMD_VDD_MPU_L
  */
 #define OMAP4430_RET_SHIFT                                              8
-#define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
+#define OMAP4430_RET_MASK                                               (0xff << 8)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            16
-#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
+#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             (0x3 << 16)
 
 /* Used by PM_L4PER_PWRSTCTRL */
 #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           8
-#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            (1 << 8)
 
 /* Used by PM_L4PER_PWRSTST */
 #define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            4
-#define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
+#define OMAP4430_RETAINED_BANK_STATEST_MASK                             (0x3 << 4)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_RETMODE_ENABLE_SHIFT                                   0
-#define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
+#define OMAP4430_RETMODE_ENABLE_MASK                                    (1 << 0)
 
-/* Used by REVISION_PRM */
-#define OMAP4430_REV_SHIFT                                              0
-#define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
-
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST1_SHIFT                                             0
-#define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
+#define OMAP4430_RST1_MASK                                              (1 << 0)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST1ST_SHIFT                                           0
-#define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
+#define OMAP4430_RST1ST_MASK                                            (1 << 0)
 
-/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
 #define OMAP4430_RST2_SHIFT                                             1
-#define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
+#define OMAP4430_RST2_MASK                                              (1 << 1)
 
-/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
 #define OMAP4430_RST2ST_SHIFT                                           1
-#define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
+#define OMAP4430_RST2ST_MASK                                            (1 << 1)
 
 /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
 #define OMAP4430_RST3_SHIFT                                             2
-#define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
+#define OMAP4430_RST3_MASK                                              (1 << 2)
 
 /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
 #define OMAP4430_RST3ST_SHIFT                                           2
-#define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
+#define OMAP4430_RST3ST_MASK                                            (1 << 2)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME1_SHIFT                                         0
-#define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
+#define OMAP4430_RSTTIME1_MASK                                          (0x3ff << 0)
 
 /* Used by PRM_RSTTIME */
 #define OMAP4430_RSTTIME2_SHIFT                                         10
-#define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
+#define OMAP4430_RSTTIME2_MASK                                          (0x1f << 10)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               1
-#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                (1 << 1)
 
 /* Used by PRM_RSTCTRL */
 #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               0
-#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                (1 << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_R_RTL_SHIFT                                            11
+#define OMAP4430_R_RTL_MASK                                             (0x1f << 11)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_CORE_L_SHIFT                                    0
-#define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
+#define OMAP4430_SA_VDD_CORE_L_MASK                                     (1 << 0)
 
 /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                0
-#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 (0x7f << 0)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_IVA_L_SHIFT                                     8
-#define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
+#define OMAP4430_SA_VDD_IVA_L_MASK                                      (1 << 8)
 
 /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      8
-#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 8)
 
 /* Used by PRM_VC_CFG_CHANNEL */
 #define OMAP4430_SA_VDD_MPU_L_SHIFT                                     16
-#define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
+#define OMAP4430_SA_VDD_MPU_L_MASK                                      (1 << 16)
 
 /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      16
-#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       (0x7f << 16)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_SCHEME_SHIFT                                           30
+#define OMAP4430_SCHEME_MASK                                            (0x3 << 30)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLH_SHIFT                                             0
-#define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
+#define OMAP4430_SCLH_MASK                                              (0xff << 0)
 
 /* Used by PRM_VC_CFG_I2C_CLK */
 #define OMAP4430_SCLL_SHIFT                                             8
-#define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
+#define OMAP4430_SCLL_MASK                                              (0xff << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_SECURE_WDT_RST_SHIFT                                   4
-#define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
+#define OMAP4430_SECURE_WDT_RST_MASK                                    (1 << 4)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  18
-#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
+#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   (0x3 << 18)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 9
-#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  (1 << 9)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_SL2_MEM_STATEST_SHIFT                                  6
-#define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
+#define OMAP4430_SL2_MEM_STATEST_MASK                                   (0x3 << 6)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_SLAVEADDR_SHIFT                                        0
-#define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
+#define OMAP4430_SLAVEADDR_MASK                                         (0x7f << 0)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    3
-#define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
+#define OMAP4430_SLEEP_RBB_SEL_MASK                                     (1 << 3)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_SLPCNT_VALUE_SHIFT                                     16
-#define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
+#define OMAP4430_SLPCNT_VALUE_MASK                                      (0xff << 16)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   (0xffff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  8
-#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
+#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   (0xffff << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT                                 1
+#define OMAP4430_SMPS_RA_ERR_CORE_MASK                                  (1 << 1)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT                                  9
+#define OMAP4430_SMPS_RA_ERR_IVA_MASK                                   (1 << 9)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT                                  17
+#define OMAP4430_SMPS_RA_ERR_MPU_MASK                                   (1 << 17)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT                                 0
+#define OMAP4430_SMPS_SA_ERR_CORE_MASK                                  (1 << 0)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT                                  8
+#define OMAP4430_SMPS_SA_ERR_IVA_MASK                                   (1 << 8)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT                                  16
+#define OMAP4430_SMPS_SA_ERR_MPU_MASK                                   (1 << 16)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT                            2
+#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK                             (1 << 2)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT                             10
+#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK                              (1 << 10)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT                             18
+#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK                              (1 << 18)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2EN_SHIFT                                            0
-#define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
+#define OMAP4430_SR2EN_MASK                                             (1 << 0)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_IN_TRANSITION_SHIFT                                6
-#define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
+#define OMAP4430_SR2_IN_TRANSITION_MASK                                 (1 << 6)
 
 /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
 #define OMAP4430_SR2_STATUS_SHIFT                                       3
-#define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
+#define OMAP4430_SR2_STATUS_MASK                                        (0x3 << 3)
 
 /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
 #define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  8
-#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   (0xff << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAMLDO_STATUS_SHIFT                                   8
-#define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
+#define OMAP4430_SRAMLDO_STATUS_MASK                                    (1 << 8)
 
 /*
  * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
  * PRM_LDO_SRAM_MPU_CTRL
  */
 #define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               9
-#define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
+#define OMAP4430_SRAM_IN_TRANSITION_MASK                                (1 << 9)
 
 /* Used by PRM_VC_CFG_I2C_MODE */
 #define OMAP4430_SRMODEEN_SHIFT                                         4
-#define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
+#define OMAP4430_SRMODEEN_MASK                                          (1 << 4)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_COUNT_SHIFT                                     0
-#define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
+#define OMAP4430_STABLE_COUNT_MASK                                      (0x3f << 0)
 
 /* Used by PRM_VOLTSETUP_WARMRESET */
 #define OMAP4430_STABLE_PRESCAL_SHIFT                                   8
-#define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
+#define OMAP4430_STABLE_PRESCAL_MASK                                    (0x3 << 8)
+
+/* Used by PRM_LDO_BANDGAP_SETUP */
+#define OMAP4430_STARTUP_COUNT_SHIFT                                    0
+#define OMAP4430_STARTUP_COUNT_MASK                                     (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP4430_STARTUP_COUNT_24_31_SHIFT                              24
+#define OMAP4430_STARTUP_COUNT_24_31_MASK                               (0xff << 24)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 20
-#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  (0x3 << 20)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                10
-#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 (1 << 10)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 8
-#define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
+#define OMAP4430_TCM1_MEM_STATEST_MASK                                  (0x3 << 8)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 22
-#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  (0x3 << 22)
 
 /* Used by PM_IVAHD_PWRSTCTRL */
 #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                11
-#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 (1 << 11)
 
 /* Used by PM_IVAHD_PWRSTST */
 #define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 10
-#define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
+#define OMAP4430_TCM2_MEM_STATEST_MASK                                  (0x3 << 10)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                2
-#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
+#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 (1 << 2)
 
 /* Used by RM_TESLA_RSTST */
 #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          3
-#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           (1 << 3)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               20
-#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                (0x3 << 20)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              10
-#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               (1 << 10)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               8
-#define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
+#define OMAP4430_TESLA_EDMA_STATEST_MASK                                (0x3 << 8)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 16
-#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
+#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  (0x3 << 16)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                8
-#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
+#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 (1 << 8)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L1_STATEST_SHIFT                                 4
-#define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
+#define OMAP4430_TESLA_L1_STATEST_MASK                                  (0x3 << 4)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 18
-#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
+#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  (0x3 << 18)
 
 /* Used by PM_TESLA_PWRSTCTRL */
 #define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                9
-#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
+#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 (1 << 9)
 
 /* Used by PM_TESLA_PWRSTST */
 #define OMAP4430_TESLA_L2_STATEST_SHIFT                                 6
-#define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
+#define OMAP4430_TESLA_L2_STATEST_MASK                                  (0x3 << 6)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_TIMEOUT_SHIFT                                          0
-#define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
+#define OMAP4430_TIMEOUT_MASK                                           (0xffff << 0)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_TIMEOUTEN_SHIFT                                        3
-#define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
+#define OMAP4430_TIMEOUTEN_MASK                                         (1 << 3)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_TRANSITION_EN_SHIFT                                    8
-#define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_EN_MASK                                     (1 << 8)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_TRANSITION_ST_SHIFT                                    8
-#define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
+#define OMAP4430_TRANSITION_ST_MASK                                     (1 << 8)
 
 /* Used by PRM_VC_VAL_BYPASS */
 #define OMAP4430_VALID_SHIFT                                            24
-#define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
+#define OMAP4430_VALID_MASK                                             (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_EN_MASK                                   (1 << 14)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  14
-#define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
+#define OMAP4430_VC_BYPASSACK_ST_MASK                                   (1 << 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_CORE_VPACK_EN_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_EN_MASK                                  (1 << 22)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_CORE_VPACK_ST_SHIFT                                 22
+#define OMAP4430_VC_CORE_VPACK_ST_MASK                                  (1 << 22)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  30
-#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
+#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   (1 << 30)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  6
-#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
+#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   (1 << 6)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_RAERR_EN_SHIFT                                      12
-#define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_EN_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_RAERR_ST_SHIFT                                      12
-#define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
+#define OMAP4430_VC_RAERR_ST_MASK                                       (1 << 12)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_SAERR_EN_SHIFT                                      11
-#define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_EN_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_SAERR_ST_SHIFT                                      11
-#define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
+#define OMAP4430_VC_SAERR_ST_MASK                                       (1 << 11)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VC_TOERR_EN_SHIFT                                      13
-#define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_EN_MASK                                       (1 << 13)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VC_TOERR_ST_SHIFT                                      13
-#define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
+#define OMAP4430_VC_TOERR_ST_MASK                                       (1 << 13)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMAX_SHIFT                                           24
-#define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
+#define OMAP4430_VDDMAX_MASK                                            (0xff << 24)
 
 /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
 #define OMAP4430_VDDMIN_SHIFT                                           16
-#define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
+#define OMAP4430_VDDMIN_MASK                                            (0xff << 16)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             12
-#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              (1 << 12)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            8
-#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             (1 << 8)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              14
-#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               (1 << 14)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 9
-#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
+#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  (1 << 9)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             7
-#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              (1 << 7)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              13
-#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               (1 << 13)
 
 /* Used by PRM_VOLTCTRL */
 #define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 8
-#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  (1 << 8)
 
 /* Used by PRM_RSTST */
 #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             6
-#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              (1 << 6)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT                                 4
+#define OMAP4430_VFSM_RA_ERR_CORE_MASK                                  (1 << 4)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT                                  12
+#define OMAP4430_VFSM_RA_ERR_IVA_MASK                                   (1 << 12)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT                                  20
+#define OMAP4430_VFSM_RA_ERR_MPU_MASK                                   (1 << 20)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT                                 3
+#define OMAP4430_VFSM_SA_ERR_CORE_MASK                                  (1 << 3)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT                                  11
+#define OMAP4430_VFSM_SA_ERR_IVA_MASK                                   (1 << 11)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT                                  19
+#define OMAP4430_VFSM_SA_ERR_MPU_MASK                                   (1 << 19)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT                            5
+#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK                             (1 << 5)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT                             13
+#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK                              (1 << 13)
+
+/* Used by PRM_VC_ERRST */
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT                             21
+#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK                              (1 << 21)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 0
-#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  (0xff << 0)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  8
-#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   (0xff << 8)
 
 /* Used by PRM_VC_VAL_SMPS_RA_VOL */
 #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  16
-#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   (0xff << 16)
 
 /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
 #define OMAP4430_VPENABLE_SHIFT                                         0
-#define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPENABLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
 #define OMAP4430_VPINIDLE_SHIFT                                         0
-#define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
+#define OMAP4430_VPINIDLE_MASK                                          (1 << 0)
 
 /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
 #define OMAP4430_VPVOLTAGE_SHIFT                                        0
-#define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
+#define OMAP4430_VPVOLTAGE_MASK                                         (0xff << 0)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                (1 << 20)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               20
-#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                (1 << 20)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                18
-#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 (1 << 18)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                17
-#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 (1 << 17)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              (1 << 19)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             19
-#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              (1 << 19)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          (1 << 16)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         16
-#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          (1 << 16)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              (1 << 21)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             21
-#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              (1 << 21)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                28
-#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 (1 << 28)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 26
-#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  (1 << 26)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 25
-#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  (1 << 25)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               (1 << 27)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              27
-#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               (1 << 27)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           (1 << 24)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          24
-#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           (1 << 24)
 
 /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               (1 << 29)
 
 /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
 #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              29
-#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               (1 << 29)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                4
-#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 (1 << 4)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 2
-#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  (1 << 2)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 1
-#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  (1 << 1)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               (1 << 3)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              3
-#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               (1 << 3)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           (1 << 0)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          0
-#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           (1 << 0)
 
 /* Used by PRM_IRQENABLE_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               (1 << 5)
 
 /* Used by PRM_IRQSTATUS_MPU_2 */
 #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              5
-#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               (1 << 5)
 
 /* Used by PRM_SRAM_COUNT */
 #define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  8
-#define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
+#define OMAP4430_VSETUPCNT_VALUE_MASK                                   (0xff << 8)
 
 /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
 #define OMAP4430_VSTEPMAX_SHIFT                                         0
-#define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMAX_MASK                                          (0xff << 0)
 
 /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
 #define OMAP4430_VSTEPMIN_SHIFT                                         0
-#define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
+#define OMAP4430_VSTEPMIN_MASK                                          (0xff << 0)
 
 /* Used by PRM_MODEM_IF_CTRL */
 #define OMAP4430_WAKE_MODEM_SHIFT                                       0
-#define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
+#define OMAP4430_WAKE_MODEM_MASK                                        (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           6
-#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            (1 << 6)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_DMIC_WKDEP */
 #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           2
-#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            (1 << 2)
 
 /* Used by PM_L4PER_DMTIMER10_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         1
-#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER11_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            0
-#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER2_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER3_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER4_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_DMTIMER9_WKDEP */
 #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              (1 << 0)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              5
-#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               (1 << 5)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 4
-#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  (1 << 4)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                7
-#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 (1 << 7)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               6
-#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              9
-#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               (1 << 9)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 8
-#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  (1 << 8)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                11
-#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 (1 << 11)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               10
-#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                (1 << 10)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_WKUP_GPIO1_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        1
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         (1 << 1)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO2_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO3_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO4_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO5_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_GPIO6_WKDEP */
 #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             19
-#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              (1 << 19)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           13
-#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            (1 << 13)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              12
-#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               (1 << 12)
 
 /* Used by PM_DSS_DSS_WKDEP */
 #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            14
-#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             (1 << 14)
 
 /* Used by PM_L4PER_HECC1_WKDEP */
 #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_HECC2_WKDEP */
 #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C1_WKDEP */
 #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C2_WKDEP */
 #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C3_WKDEP */
 #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L4PER_I2C4_WKDEP */
 #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            7
-#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             (1 << 7)
 
 /* Used by PM_L4PER_I2C5_WKDEP */
 #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              (1 << 0)
 
 /* Used by PM_WKUP_KEYBOARD_WKDEP */
 #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_ABE_MCASP_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          7
-#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           (1 << 7)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         6
-#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          (1 << 6)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           0
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            (1 << 0)
 
 /* Used by PM_L4PER_MCASP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         2
-#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          (1 << 2)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP1_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP2_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_ABE_MCBSP3_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCBSP4_WKDEP */
 #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI1_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI2_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI3_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MCSPI4_WKDEP */
 #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC1_WKDEP */
 #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_L3INIT_MMC2_WKDEP */
 #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_MMC6_WKDEP */
 #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD3_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD4_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L4PER_MMCSD5_WKDEP */
 #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              3
-#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               (1 << 3)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                (1 << 0)
 
 /* Used by PM_L3INIT_PCIESS_WKDEP */
 #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             7
-#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              (1 << 7)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            6
-#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             (1 << 6)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ABE_PDM_WKDEP */
 #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            2
-#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             (1 << 2)
 
 /* Used by PM_WKUP_RTC_WKDEP */
 #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  0
-#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_SATA_WKDEP */
 #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               2
-#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                (1 << 2)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_ABE_SLIMBUS_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        7
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         (1 << 7)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       6
-#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        (1 << 6)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         0
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          (1 << 0)
 
 /* Used by PM_L4PER_SLIMBUS2_WKDEP */
 #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       2
-#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        (1 << 2)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_ALWON_SR_CORE_WKDEP */
 #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               (1 << 0)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            1
-#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             (1 << 1)
 
 /* Used by PM_ALWON_SR_IVA_WKDEP */
 #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ALWON_SR_MPU_WKDEP */
 #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                (1 << 0)
 
 /* Used by PM_WKUP_TIMER12_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_TIMER1_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER5_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER6_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER7_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               0
-#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                (1 << 0)
 
 /* Used by PM_ABE_TIMER8_WKDEP */
 #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             2
-#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              (1 << 2)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART1_WKDEP */
 #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART2_WKDEP */
 #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             1
-#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              (1 << 1)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L4PER_UART3_WKDEP */
 #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              2
-#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               (1 << 2)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                0
-#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 (1 << 0)
 
 /* Used by PM_L4PER_UART4_WKDEP */
 #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               3
-#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                (1 << 3)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_UNIPRO1_WKDEP */
 #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          1
-#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       1
-#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        (1 << 1)
 
 /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          0
-#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           (1 << 0)
 
 /* Used by PM_L3INIT_USB_HOST_WKDEP */
 #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             0
-#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              (1 << 0)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_OTG_WKDEP */
 #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               (1 << 0)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           1
-#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            (1 << 1)
 
 /* Used by PM_L3INIT_USB_TLL_WKDEP */
 #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              0
-#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_WKUP_USIM_WKDEP */
 #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                3
-#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 (1 << 3)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               (1 << 1)
 
 /* Used by PM_WKUP_WDT2_WKDEP */
 #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_ABE_WDT3_WKDEP */
 #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 0
-#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  (1 << 0)
 
 /* Used by PM_L3INIT_HSI_WKDEP */
 #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         8
-#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          (1 << 8)
 
 /* Used by PM_L3INIT_XHPI_WKDEP */
 #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              1
-#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               (1 << 1)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_CTRL_SHIFT                                       8
-#define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
+#define OMAP4430_WUCLK_CTRL_MASK                                        (1 << 8)
 
 /* Used by PRM_IO_PMCTRL */
 #define OMAP4430_WUCLK_STATUS_SHIFT                                     9
-#define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
+#define OMAP4430_WUCLK_STATUS_MASK                                      (1 << 9)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_X_MAJOR_SHIFT                                          8
+#define OMAP4430_X_MAJOR_MASK                                           (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_Y_MINOR_SHIFT                                          0
+#define OMAP4430_Y_MINOR_MASK                                           (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 588873b9303a..7be040b2fdab 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -5,7 +5,7 @@
  * OMAP2/3 Power/Reset Management (PRM) register definitions
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2010 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -246,6 +246,15 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
         return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
 
+/* These omap2_ PRM functions apply to both OMAP2 and 3 */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
+
+int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
+int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+
 #endif
 
 /*
@@ -398,4 +407,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 
 
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
new file mode 100644
index 000000000000..421771eee450
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -0,0 +1,110 @@
+/*
+ * OMAP2/3 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+
+/**
+ * omap2_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL if called while running on a non-OMAP2/3 chip.
+ */
+int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
+                                       (1 << shift));
+}
+
+/**
+ * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+        u32 mask;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        mask = 1 << shift;
+        prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
+
+        return 0;
+}
+
+/**
+ * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @prm_mod: PRM submodule base (e.g. CORE_MOD)
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
+{
+        u32 mask;
+        int c;
+
+        if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
+                return -EINVAL;
+
+        mask = 1 << shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
+        /* de-assert the reset control line */
+        prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
+        /* wait the status to be set */
+        omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
+                                                  mask),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
new file mode 100644
index 000000000000..a1ff918d9bed
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -0,0 +1,116 @@
+/*
+ * OMAP4 PRM module functions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ * Benoît Cousson
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <plat/common.h>
+#include <plat/cpu.h>
+#include <plat/prcm.h>
+
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET                4
+
+/**
+ * omap4_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
+{
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
+}
+
+/**
+ * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        mask = 1 << shift;
+        omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
+
+        return 0;
+}
+
+/**
+ * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
+{
+        u32 mask;
+        void __iomem *rstst_reg;
+        int c;
+
+        if (!cpu_is_omap44xx() || !rstctrl_reg)
+                return -EINVAL;
+
+        rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
+
+        mask = 1 << shift;
+
+        /* Check the current status to avoid de-asserting the line twice */
+        if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
+        /* de-assert the reset control line */
+        omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
+        /* wait the status to be set */
+        omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index fe8ef26431e5..59839dbabd84 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -44,14 +44,12 @@
 #define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET                0x0038
 #define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
-#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_PRM_PROFILING_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET              0x0000
 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET             0x0004
-#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
 #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET                  0x0008
 #define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
 #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET              0x000c
@@ -686,8 +684,8 @@
 #define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET               0x00dc
 #define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
-#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET               0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET              0x00e0
+#define OMAP4430_PRM_LDO_BANDGAP_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET                0x00e4
 #define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET                    0x00e8
@@ -698,6 +696,8 @@
 #define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
 #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
 #define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+#define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
+#define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
 
 /*
  * PRCM_MPU
@@ -715,6 +715,8 @@
 /* PRCM_MPU.DEVICE_PRM register offsets */
 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
 #define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
 
 /* PRCM_MPU.CPU0 register offsets */
 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 566e991ede81..becf0e38ef7e 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,20 +19,31 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/serial_8250.h>
+#include <linux/pm_runtime.h>
+
+#ifdef CONFIG_SERIAL_OMAP
+#include <plat/omap-serial.h>
+#endif
 
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/clock.h>
-#include <plat/control.h>
+#include <plat/dma.h>
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 
 #include "prm.h"
 #include "pm.h"
+#include "cm.h"
 #include "prm-regbits-34xx.h"
+#include "control.h"
 
 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
@@ -48,6 +59,8 @@
  */
 #define DEFAULT_TIMEOUT 0
 
+#define MAX_UART_HWMOD_NAME_LEN         16
+
 struct omap_uart_state {
         int num;
         int can_sleep;
@@ -58,14 +71,21 @@ struct omap_uart_state {
         void __iomem *wk_en;
         u32 wk_mask;
         u32 padconf;
+        u32 dma_enabled;
 
         struct clk *ick;
         struct clk *fck;
         int clocked;
 
-        struct plat_serial8250_port *p;
+        int irq;
+        int regshift;
+        int irqflags;
+        void __iomem *membase;
+        resource_size_t mapbase;
+
         struct list_head node;
-        struct platform_device pdev;
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
 
         u32 errata;
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
@@ -83,75 +103,47 @@ struct omap_uart_state {
 };
 
 static LIST_HEAD(uart_list);
+static u8 num_uarts;
 
-static struct plat_serial8250_port serial_platform_data0[] = {
-        {
-                .irq            = 72,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+/*
+ * Since these idle/enable hooks are used in the idle path itself
+ * which has interrupts disabled, use the non-locking versions of
+ * the hwmod enable/disable functions.
+ */
+static int uart_idle_hwmod(struct omap_device *od)
+{
+        _omap_hwmod_idle(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data1[] = {
-        {
-                .irq            = 73,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+        return 0;
+}
 
-static struct plat_serial8250_port serial_platform_data2[] = {
-        {
-                .irq            = 74,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
-};
+static int uart_enable_hwmod(struct omap_device *od)
+{
+        _omap_hwmod_enable(od->hwmods[0]);
 
-static struct plat_serial8250_port serial_platform_data3[] = {
+        return 0;
+}
+
+static struct omap_device_pm_latency omap_uart_latency[] = {
         {
-                .irq            = 70,
-                .flags          = UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = OMAP24XX_BASE_BAUD * 16,
-        }, {
-                .flags          = 0
-        }
+                .deactivate_func = uart_idle_hwmod,
+                .activate_func   = uart_enable_hwmod,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
 };
 
-void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
-{
-        serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
-        serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
-        serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
-        serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
-}
-
 static inline unsigned int __serial_read_reg(struct uart_port *up,
-                                           int offset)
+                                             int offset)
 {
         offset <<= up->regshift;
         return (unsigned int)__raw_readb(up->membase + offset);
 }
 
-static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
+static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
                                            int offset)
 {
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
+        offset <<= uart->regshift;
+        return (unsigned int)__raw_readb(uart->membase + offset);
 }
 
 static inline void __serial_write_reg(struct uart_port *up, int offset,
@@ -161,11 +153,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset,
         __raw_writeb(value, up->membase + offset);
 }
 
-static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
+static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
                                     int value)
 {
-        offset <<= p->regshift;
-        __raw_writeb(value, p->membase + offset);
+        offset <<= uart->regshift;
+        __raw_writeb(value, uart->membase + offset);
 }
 
 /*
@@ -173,14 +165,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
  * properly. Note that the TX watermark initialization may not be needed
  * once the 8250.c watermark handling code is merged.
  */
+
 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
-
-        serial_write_reg(p, UART_OMAP_MDR1, 0x07);
-        serial_write_reg(p, UART_OMAP_SCR, 0x08);
-        serial_write_reg(p, UART_OMAP_MDR1, 0x00);
-        serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
+        serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
+        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
+        serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
 }
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -197,24 +187,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
                 u8 fcr_val)
 {
-        struct plat_serial8250_port *p = uart->p;
         u8 timeout = 255;
 
-        serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
+        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
         udelay(2);
-        serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
+        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
                         UART_FCR_CLEAR_RCVR);
         /*
          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
          * TX_FIFO_E bit is 1.
          */
-        while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) &
+        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
                                 (UART_LSR_THRE | UART_LSR_DR))) {
                 timeout--;
                 if (!timeout) {
                         /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
-                                serial_read_reg(p, UART_LSR));
+                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
+                        serial_read_reg(uart, UART_LSR));
                         break;
                 }
                 udelay(1);
@@ -224,23 +213,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 static void omap_uart_save_context(struct omap_uart_state *uart)
 {
         u16 lcr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
 
-        lcr = serial_read_reg(p, UART_LCR);
-        serial_write_reg(p, UART_LCR, 0xBF);
-        uart->dll = serial_read_reg(p, UART_DLL);
-        uart->dlh = serial_read_reg(p, UART_DLM);
-        serial_write_reg(p, UART_LCR, lcr);
-        uart->ier = serial_read_reg(p, UART_IER);
-        uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(p, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(p, UART_OMAP_WER);
-        serial_write_reg(p, UART_LCR, 0x80);
-        uart->mcr = serial_read_reg(p, UART_MCR);
-        serial_write_reg(p, UART_LCR, lcr);
+        lcr = serial_read_reg(uart, UART_LCR);
+        serial_write_reg(uart, UART_LCR, 0xBF);
+        uart->dll = serial_read_reg(uart, UART_DLL);
+        uart->dlh = serial_read_reg(uart, UART_DLM);
+        serial_write_reg(uart, UART_LCR, lcr);
+        uart->ier = serial_read_reg(uart, UART_IER);
+        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
+        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
+        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
+        serial_write_reg(uart, UART_LCR, 0x80);
+        uart->mcr = serial_read_reg(uart, UART_MCR);
+        serial_write_reg(uart, UART_LCR, lcr);
 
         uart->context_valid = 1;
 }
@@ -248,7 +236,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
 static void omap_uart_restore_context(struct omap_uart_state *uart)
 {
         u16 efr = 0;
-        struct plat_serial8250_port *p = uart->p;
 
         if (!enable_off_mode)
                 return;
@@ -261,29 +248,30 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
                 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x7);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        efr = serial_read_reg(p, UART_EFR);
-        serial_write_reg(p, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, 0x0);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_DLL, uart->dll);
-        serial_write_reg(p, UART_DLM, uart->dlh);
-        serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(p, UART_IER, uart->ier);
-        serial_write_reg(p, UART_LCR, 0x80);
-        serial_write_reg(p, UART_MCR, uart->mcr);
-        serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
-        serial_write_reg(p, UART_EFR, efr);
-        serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(p, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(p, UART_OMAP_WER, uart->wer);
-        serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
+                serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        efr = serial_read_reg(uart, UART_EFR);
+        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, 0x0);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_DLL, uart->dll);
+        serial_write_reg(uart, UART_DLM, uart->dlh);
+        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
+        serial_write_reg(uart, UART_IER, uart->ier);
+        serial_write_reg(uart, UART_LCR, 0x80);
+        serial_write_reg(uart, UART_MCR, uart->mcr);
+        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_EFR, efr);
+        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
+        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
+        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
+        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
                 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
         else
-                serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
+                /* UART 16x mode */
+                serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
 }
 #else
 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -295,8 +283,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
         if (uart->clocked)
                 return;
 
-        clk_enable(uart->ick);
-        clk_enable(uart->fck);
+        omap_device_enable(uart->pdev);
         uart->clocked = 1;
         omap_uart_restore_context(uart);
 }
@@ -310,8 +297,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 
         omap_uart_save_context(uart);
         uart->clocked = 0;
-        clk_disable(uart->ick);
-        clk_disable(uart->fck);
+        omap_device_idle(uart->pdev);
 }
 
 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
@@ -349,18 +335,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 }
 
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                          int enable)
+                                               int enable)
 {
-        struct plat_serial8250_port *p = uart->p;
-        u16 sysc;
+        u8 idlemode;
 
-        sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
-        if (enable)
-                sysc |= 0x2 << 3;
-        else
-                sysc |= 0x1 << 3;
+        if (enable) {
+                /**
+                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
+                 * in Smartidle Mode When Configured for DMA Operations.
+                 */
+                if (uart->dma_enabled)
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = HWMOD_IDLEMODE_SMART;
+        } else {
+                idlemode = HWMOD_IDLEMODE_NO;
+        }
 
-        serial_write_reg(p, UART_OMAP_SYSC, sysc);
+        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 }
 
 static void omap_uart_block_sleep(struct omap_uart_state *uart)
@@ -377,7 +369,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
-        if (device_may_wakeup(&uart->pdev.dev))
+        if (device_may_wakeup(&uart->pdev->dev))
                 omap_uart_enable_wakeup(uart);
         else
                 omap_uart_disable_wakeup(uart);
@@ -472,6 +464,7 @@ int omap_uart_can_sleep(void)
  * UART will not idle or sleep for its timeout period.
  *
  **/
+/* static int first_interrupt; */
 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 {
         struct omap_uart_state *uart = dev_id;
@@ -483,7 +476,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
@@ -495,7 +487,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
         omap_uart_smart_idle_enable(uart, 0);
 
         if (cpu_is_omap34xx()) {
-                u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
+                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
                 u32 wk_mask = 0;
                 u32 padconf = 0;
 
@@ -514,19 +506,17 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP3430_ST_UART3_MASK;
                         padconf = 0x19e;
                         break;
+                case 3:
+                        wk_mask = OMAP3630_ST_UART4_MASK;
+                        padconf = 0x0d2;
+                        break;
                 }
                 uart->wk_mask = wk_mask;
                 uart->padconf = padconf;
         } else if (cpu_is_omap24xx()) {
                 u32 wk_mask = 0;
+                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
-                }
                 switch (uart->num) {
                 case 0:
                         wk_mask = OMAP24XX_ST_UART1_MASK;
@@ -535,10 +525,19 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                         wk_mask = OMAP24XX_ST_UART2_MASK;
                         break;
                 case 2:
+                        wk_en = OMAP24XX_PM_WKEN2;
+                        wk_st = OMAP24XX_PM_WKST2;
                         wk_mask = OMAP24XX_ST_UART3_MASK;
                         break;
                 }
                 uart->wk_mask = wk_mask;
+                if (cpu_is_omap2430()) {
+                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
+                } else if (cpu_is_omap2420()) {
+                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
+                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
+                }
         } else {
                 uart->wk_en = NULL;
                 uart->wk_st = NULL;
@@ -546,9 +545,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        p->irqflags |= IRQF_SHARED;
-        ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
-                          "serial idle", (void *)uart);
+        uart->irqflags |= IRQF_SHARED;
+        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
+                                   IRQF_SHARED, "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
@@ -558,11 +557,17 @@ void omap_uart_enable_irqs(int enable)
         struct omap_uart_state *uart;
 
         list_for_each_entry(uart, &uart_list, node) {
-                if (enable)
-                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
-                                IRQF_SHARED, "serial idle", (void *)uart);
-                else
-                        free_irq(uart->p->irq, (void *)uart);
+                if (enable) {
+                        pm_runtime_put_sync(&uart->pdev->dev);
+                        ret = request_threaded_irq(uart->irq, NULL,
+                                                   omap_uart_interrupt,
+                                                   IRQF_SHARED,
+                                                   "serial idle",
+                                                   (void *)uart);
+                } else {
+                        pm_runtime_get_noresume(&uart->pdev->dev);
+                        free_irq(uart->irq, (void *)uart);
+                }
         }
 }
 
@@ -570,10 +575,9 @@ static ssize_t sleep_timeout_show(struct device *dev,
                                   struct device_attribute *attr,
                                   char *buf)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 
         return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
@@ -582,10 +586,9 @@ static ssize_t sleep_timeout_store(struct device *dev,
                                    struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct platform_device *pdev = container_of(dev,
-                                        struct platform_device, dev);
-        struct omap_uart_state *uart = container_of(pdev,
-                                        struct omap_uart_state, pdev);
+        struct platform_device *pdev = to_platform_device(dev);
+        struct omap_device *odev = to_omap_device(pdev);
+        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
@@ -608,48 +611,15 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static void omap_uart_block_sleep(struct omap_uart_state *uart)
+{
+        /* Needed to enable UART clocks when built without CONFIG_PM */
+        omap_uart_enable_clocks(uart);
+}
 #define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct omap_uart_state omap_uart[] = {
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data0,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM1,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data1,
-                        },
-                },
-        }, {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = PLAT8250_DEV_PLATFORM2,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data2,
-                        },
-                },
-        },
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        {
-                .pdev = {
-                        .name                   = "serial8250",
-                        .id                     = 3,
-                        .dev                    = {
-                                .platform_data  = serial_platform_data3,
-                        },
-                },
-        },
-#endif
-};
-
+#ifndef CONFIG_SERIAL_OMAP
 /*
  * Override the default 8250 read handler: mem_serial_in()
  * Empty RX fifo read causes an abort on omap3630 and omap4
@@ -682,71 +652,44 @@ static void serial_out_override(struct uart_port *up, int offset, int value)
         }
         __serial_write_reg(up, offset, value);
 }
+#endif
+
 void __init omap_serial_early_init(void)
 {
-        int i, nr_ports;
-        char name[16];
+        int i = 0;
 
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        do {
+                char oh_name[MAX_UART_HWMOD_NAME_LEN];
+                struct omap_hwmod *oh;
+                struct omap_uart_state *uart;
 
-        /*
-         * Make sure the serial ports are muxed on at this point.
-         * You have to mux them off in device drivers later on
-         * if not needed.
-         */
+                snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
+                         "uart%d", i + 1);
+                oh = omap_hwmod_lookup(oh_name);
+                if (!oh)
+                        break;
 
-        for (i = 0; i < nr_ports; i++) {
-                struct omap_uart_state *uart = &omap_uart[i];
-                struct platform_device *pdev = &uart->pdev;
-                struct device *dev = &pdev->dev;
-                struct plat_serial8250_port *p = dev->platform_data;
+                uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
+                if (WARN_ON(!uart))
+                        return;
+
+                uart->oh = oh;
+                uart->num = i++;
+                list_add_tail(&uart->node, &uart_list);
+                num_uarts++;
 
-                /* Don't map zero-based physical address */
-                if (p->mapbase == 0) {
-                        dev_warn(dev, "no physical address for uart#%d,"
-                                 " so skipping early_init...\n", i);
-                        continue;
-                }
                 /*
-                 * Module 4KB + L4 interconnect 4KB
-                 * Static mapping, never released
+                 * NOTE: omap_hwmod_init() has not yet been called,
+                 *       so no hwmod functions will work yet.
                  */
-                p->membase = ioremap(p->mapbase, SZ_8K);
-                if (!p->membase) {
-                        dev_err(dev, "ioremap failed for uart%i\n", i + 1);
-                        continue;
-                }
-
-                sprintf(name, "uart%d_ick", i + 1);
-                uart->ick = clk_get(NULL, name);
-                if (IS_ERR(uart->ick)) {
-                        dev_err(dev, "Could not get uart%d_ick\n", i + 1);
-                        uart->ick = NULL;
-                }
 
-                sprintf(name, "uart%d_fck", i+1);
-                uart->fck = clk_get(NULL, name);
-                if (IS_ERR(uart->fck)) {
-                        dev_err(dev, "Could not get uart%d_fck\n", i + 1);
-                        uart->fck = NULL;
-                }
-
-                /* FIXME: Remove this once the clkdev is ready */
-                if (!cpu_is_omap44xx()) {
-                        if (!uart->ick || !uart->fck)
-                                continue;
-                }
-
-                uart->num = i;
-                p->private_data = uart;
-                uart->p = p;
-
-                if (cpu_is_omap44xx())
-                        p->irq += 32;
-        }
+                /*
+                 * During UART early init, device need to be probed
+                 * to determine SoC specific init before omap_device
+                 * is ready.  Therefore, don't allow idle here
+                 */
+                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+        } while (1);
 }
 
 /**
@@ -763,53 +706,135 @@ void __init omap_serial_early_init(void)
 void __init omap_serial_init_port(int port)
 {
         struct omap_uart_state *uart;
-        struct platform_device *pdev;
-        struct device *dev;
-
-        BUG_ON(port < 0);
-        BUG_ON(port >= ARRAY_SIZE(omap_uart));
-
-        uart = &omap_uart[port];
-        pdev = &uart->pdev;
-        dev = &pdev->dev;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        void *pdata = NULL;
+        u32 pdata_size = 0;
+        char *name;
+#ifndef CONFIG_SERIAL_OMAP
+        struct plat_serial8250_port ports[2] = {
+                {},
+                {.flags = 0},
+        };
+        struct plat_serial8250_port *p = &ports[0];
+#else
+        struct omap_uart_port_info omap_up;
+#endif
 
-        /* Don't proceed if there's no clocks available */
-        if (unlikely(!uart->ick || !uart->fck)) {
-                WARN(1, "%s: can't init uart%d, no clocks available\n",
-                     kobject_name(&dev->kobj), port);
+        if (WARN_ON(port < 0))
+                return;
+        if (WARN_ON(port >= num_uarts))
                 return;
-        }
-
-        omap_uart_enable_clocks(uart);
-
-        omap_uart_reset(uart);
-        omap_uart_idle_init(uart);
 
-        list_add_tail(&uart->node, &uart_list);
+        list_for_each_entry(uart, &uart_list, node)
+                if (port == uart->num)
+                        break;
 
-        if (WARN_ON(platform_device_register(pdev)))
-                return;
+        oh = uart->oh;
+        uart->dma_enabled = 0;
+#ifndef CONFIG_SERIAL_OMAP
+        name = "serial8250";
 
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
-                device_init_wakeup(dev, true);
-                DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
-        }
+        /*
+         * !! 8250 driver does not use standard IORESOURCE* It
+         * has it's own custom pdata that can be taken from
+         * the hwmod resource data.  But, this needs to be
+         * done after the build.
+         *
+         * ?? does it have to be done before the register ??
+         * YES, because platform_device_data_add() copies
+         * pdata, it does not use a pointer.
+         */
+        p->flags = UPF_BOOT_AUTOCONF;
+        p->iotype = UPIO_MEM;
+        p->regshift = 2;
+        p->uartclk = OMAP24XX_BASE_BAUD * 16;
+        p->irq = oh->mpu_irqs[0].irq;
+        p->mapbase = oh->slaves[0]->addr->pa_start;
+        p->membase = omap_hwmod_get_mpu_rt_va(oh);
+        p->irqflags = IRQF_SHARED;
+        p->private_data = uart;
 
         /*
          * omap44xx: Never read empty UART fifo
          * omap3xxx: Never read empty UART fifo on UARTs
          * with IP rev >=0x52
          */
+        uart->regshift = p->regshift;
+        uart->membase = p->membase;
         if (cpu_is_omap44xx())
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 
         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                uart->p->serial_in = serial_in_override;
-                uart->p->serial_out = serial_out_override;
+                p->serial_in = serial_in_override;
+                p->serial_out = serial_out_override;
+        }
+
+        pdata = &ports[0];
+        pdata_size = 2 * sizeof(struct plat_serial8250_port);
+#else
+
+        name = DRIVER_NAME;
+
+        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
+        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
+        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
+        omap_up.irqflags = IRQF_SHARED;
+        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+
+        pdata = &omap_up;
+        pdata_size = sizeof(struct omap_uart_port_info);
+#endif
+
+        if (WARN_ON(!oh))
+                return;
+
+        od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
+                               omap_uart_latency,
+                               ARRAY_SIZE(omap_uart_latency), false);
+        WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
+             name, oh->name);
+
+        uart->irq = oh->mpu_irqs[0].irq;
+        uart->regshift = 2;
+        uart->mapbase = oh->slaves[0]->addr->pa_start;
+        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
+        uart->pdev = &od->pdev;
+
+        oh->dev_attr = uart;
+
+        /*
+         * Because of early UART probing, UART did not get idled
+         * on init.  Now that omap_device is ready, ensure full idle
+         * before doing omap_device_enable().
+         */
+        omap_hwmod_idle(uart->oh);
+
+        omap_device_enable(uart->pdev);
+        omap_uart_idle_init(uart);
+        omap_uart_reset(uart);
+        omap_hwmod_enable_wakeup(uart->oh);
+        omap_device_idle(uart->pdev);
+
+        /*
+         * Need to block sleep long enough for interrupt driven
+         * driver to start.  Console driver is in polling mode
+         * so device needs to be kept enabled while polling driver
+         * is in use.
+         */
+        if (uart->timeout)
+                uart->timeout = (30 * HZ);
+        omap_uart_block_sleep(uart);
+        uart->timeout = DEFAULT_TIMEOUT;
+
+        if ((cpu_is_omap34xx() && uart->padconf) ||
+            (uart->wk_en && uart->wk_mask)) {
+                device_init_wakeup(&od->pdev.dev, true);
+                DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
         }
 
         /* Enable the MDR1 errata for OMAP3 */
@@ -826,13 +851,8 @@ void __init omap_serial_init_port(int port)
  */
 void __init omap_serial_init(void)
 {
-        int i, nr_ports;
-
-        if (!(cpu_is_omap3630() || cpu_is_omap4430()))
-                nr_ports = 3;
-        else
-                nr_ports = ARRAY_SIZE(omap_uart);
+        struct omap_uart_state *uart;
 
-        for (i = 0; i < nr_ports; i++)
-                omap_serial_init_port(i);
+        list_for_each_entry(uart, &uart_list, node)
+                omap_serial_init_port(uart->num);
 }
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index ba53191ae4c5..2fb205a7f285 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -27,11 +27,11 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
-#include <plat/control.h>
 
 #include "cm.h"
 #include "prm.h"
 #include "sdrc.h"
+#include "control.h"
 
 #define SDRC_SCRATCHPAD_SEM_V   0xfa00291c
 
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2a57ab..3637274af5be 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
         ldr     r4, [sp, #80]
         str     r4, omap_sdrc_mr_1_val
 skip_cs1_params:
+        mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
+        bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
+        mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
         dsb                             @ flush buffered writes to interconnect
-
+        isb                             @ prevent speculative exec past here
         cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
@@ -148,6 +151,7 @@ skip_cs1_params:
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
 return_to_sdram:
+        mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8491f2..e13c29eecf2b 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -40,6 +40,8 @@
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 
+#include "timer-gp.h"
+
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
 
@@ -228,8 +230,10 @@ static void __init omap2_gp_clocksource_init(void)
 static void __init omap2_gp_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-        BUG_ON(!twd_base);
+        if (cpu_is_omap44xx()) {
+                twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+                BUG_ON(!twd_base);
+        }
 #endif
         omap_dm_timer_init();
 
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
new file mode 100644
index 000000000000..5c1072c6783b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer-gp.h
@@ -0,0 +1,16 @@
+/*
+ * OMAP2/3 GPTIMER support.headers
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
+
+extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
+
+#endif
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index a216d88b04b5..1481078763b8 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -29,18 +29,18 @@
 
 #include <asm/irq.h>
 
-#include <plat/control.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
+#include "control.h"
+#include "mux.h"
+
 #define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
 #define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
 #define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
 #define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
 #define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
 
-#include "mux.h"
-
 #if defined(CONFIG_ARCH_OMAP2)
 
 #ifdef  CONFIG_USB_GADGET_OMAP