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authorKevin Hilman <khilman@ti.com>2011-03-29 18:57:16 -0400
committerKevin Hilman <khilman@ti.com>2011-09-15 15:08:57 -0400
commit24d3194a2c9bc4d2315117915d4d22c395c07fd5 (patch)
treed7a5848a3b67f8288fc974bb0b0eab6dacb7ea97 /arch/arm/mach-omap2/vc.c
parent08d1c9a3e2dc7a285db7c689c42963d0f5271c1f (diff)
OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from the PMIC configuration. Currently, the VC channel to PMIC mapping is a simple one-to-one mapping. Whenever a VC channel parameter is configured (i2c slave addres, PMIC register address, on/ret/off command), the corresponding bits are enabled in the VC channel configuration register. If necessary, the programmability of channel configuration settings could be extended to board/PMIC files, however, because this patch changes the channel configuration to be programmed based on existing values from the PMIC settings, it may not be required. Also note that starting with OMAP4, where there are more than 2 channels, one channel is identified as the "default" channel. When any of the bits in the channel config for the other channels are zero, it means to use the default channel. The OMAP4 TRM (at least through NDA version Q) is wrong in describing which is the default channel. The default channel on OMAP4 is MPU, not CORE as decribed in the TRM. Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/vc.c')
-rw-r--r--arch/arm/mach-omap2/vc.c70
1 files changed, 58 insertions, 12 deletions
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 72c9cb64a42b..1791f79112bf 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -19,6 +19,52 @@
19#include "prm-regbits-44xx.h" 19#include "prm-regbits-44xx.h"
20#include "prm44xx.h" 20#include "prm44xx.h"
21 21
22/*
23 * Channel configuration bits, common for OMAP3 & 4
24 * OMAP3 register: PRM_VC_CH_CONF
25 * OMAP4 register: PRM_VC_CFG_CHANNEL
26 */
27#define CFG_CHANNEL_SA BIT(0)
28#define CFG_CHANNEL_RAV BIT(1)
29#define CFG_CHANNEL_RAC BIT(2)
30#define CFG_CHANNEL_RACEN BIT(3)
31#define CFG_CHANNEL_CMD BIT(4)
32#define CFG_CHANNEL_MASK 0x3f
33
34/**
35 * omap_vc_config_channel - configure VC channel to PMIC mappings
36 * @voltdm: pointer to voltagdomain defining the desired VC channel
37 *
38 * Configures the VC channel to PMIC mappings for the following
39 * PMIC settings
40 * - i2c slave address (SA)
41 * - voltage configuration address (RAV)
42 * - command configuration address (RAC) and enable bit (RACEN)
43 * - command values for ON, ONLP, RET and OFF (CMD)
44 *
45 * This function currently only allows flexible configuration of the
46 * non-default channel. Starting with OMAP4, there are more than 2
47 * channels, with one defined as the default (on OMAP4, it's MPU.)
48 * Only the non-default channel can be configured.
49 */
50static int omap_vc_config_channel(struct voltagedomain *voltdm)
51{
52 struct omap_vc_channel *vc = voltdm->vc;
53
54 /*
55 * For default channel, the only configurable bit is RACEN.
56 * All others must stay at zero (see function comment above.)
57 */
58 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
59 vc->cfg_channel &= CFG_CHANNEL_RACEN;
60
61 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
62 vc->cfg_channel << vc->cfg_channel_sa_shift,
63 vc->common->cfg_channel_reg);
64
65 return 0;
66}
67
22/* Voltage scale and accessory APIs */ 68/* Voltage scale and accessory APIs */
23int omap_vc_pre_scale(struct voltagedomain *voltdm, 69int omap_vc_pre_scale(struct voltagedomain *voltdm,
24 unsigned long target_volt, 70 unsigned long target_volt,
@@ -166,8 +212,6 @@ static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
166 * Generic VC parameters init 212 * Generic VC parameters init
167 * XXX This data should be abstracted out 213 * XXX This data should be abstracted out
168 */ 214 */
169 voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
170 OMAP3_PRM_VC_CH_CONF_OFFSET);
171 voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, 215 voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
172 OMAP3_PRM_VC_I2C_CFG_OFFSET); 216 OMAP3_PRM_VC_I2C_CFG_OFFSET);
173 217
@@ -186,15 +230,6 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
186 if (is_initialized) 230 if (is_initialized)
187 return; 231 return;
188 232
189 /*
190 * Generic VC parameters init
191 * XXX This data should be abstracted out
192 */
193 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
194 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
195 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
196 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
197
198 /* XXX These are magic numbers and do not belong! */ 233 /* XXX These are magic numbers and do not belong! */
199 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); 234 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
200 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); 235 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
@@ -222,6 +257,8 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
222 return; 257 return;
223 } 258 }
224 259
260 vc->cfg_channel = 0;
261
225 /* get PMIC/board specific settings */ 262 /* get PMIC/board specific settings */
226 vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr; 263 vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
227 vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr; 264 vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
@@ -232,6 +269,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
232 voltdm->rmw(vc->smps_sa_mask, 269 voltdm->rmw(vc->smps_sa_mask,
233 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), 270 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
234 vc->common->smps_sa_reg); 271 vc->common->smps_sa_reg);
272 vc->cfg_channel |= CFG_CHANNEL_SA;
235 273
236 /* 274 /*
237 * Configure the PMIC register addresses. 275 * Configure the PMIC register addresses.
@@ -239,10 +277,14 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
239 voltdm->rmw(vc->smps_volra_mask, 277 voltdm->rmw(vc->smps_volra_mask,
240 vc->volt_reg_addr << __ffs(vc->smps_volra_mask), 278 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
241 vc->common->smps_volra_reg); 279 vc->common->smps_volra_reg);
242 if (vc->cmd_reg_addr) 280 vc->cfg_channel |= CFG_CHANNEL_RAV;
281
282 if (vc->cmd_reg_addr) {
243 voltdm->rmw(vc->smps_cmdra_mask, 283 voltdm->rmw(vc->smps_cmdra_mask,
244 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), 284 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
245 vc->common->smps_cmdra_reg); 285 vc->common->smps_cmdra_reg);
286 vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
287 }
246 288
247 /* Set up the on, inactive, retention and off voltage */ 289 /* Set up the on, inactive, retention and off voltage */
248 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); 290 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
@@ -254,6 +296,10 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
254 (ret_vsel << vc->common->cmd_ret_shift) | 296 (ret_vsel << vc->common->cmd_ret_shift) |
255 (off_vsel << vc->common->cmd_off_shift)); 297 (off_vsel << vc->common->cmd_off_shift));
256 voltdm->write(val, vc->cmdval_reg); 298 voltdm->write(val, vc->cmdval_reg);
299 vc->cfg_channel |= CFG_CHANNEL_CMD;
300
301 /* Channel configuration */
302 omap_vc_config_channel(voltdm);
257 303
258 /* Configure the setup times */ 304 /* Configure the setup times */
259 voltdm->rmw(voltdm->vfsm->voltsetup_mask, 305 voltdm->rmw(voltdm->vfsm->voltsetup_mask,