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authorDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
committerDan Williams <dan.j.williams@intel.com>2009-09-08 20:55:21 -0400
commitbbb20089a3275a19e475dbc21320c3742e3ca423 (patch)
tree216fdc1cbef450ca688135c5b8969169482d9a48 /arch/arm/mach-omap2/timer-gp.c
parent3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff)
parent657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff)
Merge branch 'dmaengine' into async-tx-next
Conflicts: crypto/async_tx/async_xor.c drivers/dma/ioat/dma_v2.h drivers/dma/ioat/pci.c drivers/md/raid5.c
Diffstat (limited to 'arch/arm/mach-omap2/timer-gp.c')
-rw-r--r--arch/arm/mach-omap2/timer-gp.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index f36aba12090e..97eeeebcb066 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -17,9 +17,10 @@
17 * 17 *
18 * Some parts based off of TI's 24xx code: 18 * Some parts based off of TI's 24xx code:
19 * 19 *
20 * Copyright (C) 2004 Texas Instruments, Inc. 20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 * 21 *
22 * Roughly modelled after the OMAP1 MPU timer code. 22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
23 * 24 *
24 * This file is subject to the terms and conditions of the GNU General Public 25 * This file is subject to the terms and conditions of the GNU General Public
25 * License. See the file "COPYING" in the main directory of this archive 26 * License. See the file "COPYING" in the main directory of this archive
@@ -37,6 +38,7 @@
37 38
38#include <asm/mach/time.h> 39#include <asm/mach/time.h>
39#include <mach/dmtimer.h> 40#include <mach/dmtimer.h>
41#include <asm/localtimer.h>
40 42
41/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ 43/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
42#define MAX_GPTIMER_ID 12 44#define MAX_GPTIMER_ID 12
@@ -82,7 +84,8 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
82 case CLOCK_EVT_MODE_PERIODIC: 84 case CLOCK_EVT_MODE_PERIODIC:
83 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; 85 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
84 period -= 1; 86 period -= 1;
85 87 if (cpu_is_omap44xx())
88 period = 0xff; /* FIXME: */
86 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); 89 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
87 break; 90 break;
88 case CLOCK_EVT_MODE_ONESHOT: 91 case CLOCK_EVT_MODE_ONESHOT:
@@ -145,6 +148,9 @@ static void __init omap2_gp_clockevent_init(void)
145 "timer-gp: omap_dm_timer_set_source() failed\n"); 148 "timer-gp: omap_dm_timer_set_source() failed\n");
146 149
147 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); 150 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
151 if (cpu_is_omap44xx())
152 /* Assuming 32kHz clk is driving GPT1 */
153 tick_rate = 32768; /* FIXME: */
148 154
149 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", 155 pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
150 gptimer_id, tick_rate); 156 gptimer_id, tick_rate);
@@ -224,6 +230,9 @@ static void __init omap2_gp_clocksource_init(void)
224 230
225static void __init omap2_gp_timer_init(void) 231static void __init omap2_gp_timer_init(void)
226{ 232{
233#ifdef CONFIG_LOCAL_TIMERS
234 twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
235#endif
227 omap_dm_timer_init(); 236 omap_dm_timer_init();
228 237
229 omap2_gp_clockevent_init(); 238 omap2_gp_clockevent_init();