OMAP3 SRAM: renumber registers to make space for argument passing

Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
author: Paul Walmsley <paul@pwsan.com> 2009-05-12 19:27:10 -0400
committer: paul <paul@twilight.(none)> 2009-05-12 19:27:10 -0400
commit: b2abb271a5705bc80478e79d95fc9f3babc2605c (patch)
tree: 1c3272b5b66d9589a974a19d76a527c33e0f5677 /arch/arm/mach-omap2/sram34xx.S
parent: 98cfe5abf24c6d2f06b70fa8a8a111681bed3ed9 (diff)
1 files changed, 57 insertions, 57 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 9a454151c422..35131e5bc7d1 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -63,50 +63,50 @@ ENTRY(omap3_sram_configure_core_dpll)
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 unlock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x4
+        orr     r12, r12, #0x4
-        str     r5, [r4]                @ (no OCP barrier needed)
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 lock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        bic     r5, r5, #0x4
+        bic     r12, r12, #0x4
-        str     r5, [r4]                @ (no OCP barrier needed)
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 sdram_in_selfrefresh:
-        ldr     r4, omap3_sdrc_power    @ read the SDRC_POWER register
+        ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        ldr     r12, [r11]              @ read the contents of SDRC_POWER
-        mov     r9, r5                  @ keep a copy of SDRC_POWER bits
+        mov     r9, r12                 @ keep a copy of SDRC_POWER bits
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        orr     r12, r12, #0x40         @ enable self refresh on idle req
-        bic     r5, r5, #0x4            @ clear PWDENA
+        bic     r12, r12, #0x4          @ clear PWDENA
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        str     r12, [r11]              @ write back to SDRC_POWER register
-        ldr     r5, [r4]                @ posted-write barrier for SDRC
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
-        ldr     r4, omap3_cm_iclken1_core       @ read the CM_ICLKEN1_CORE reg
+        ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        bic     r5, r5, #0x2            @ disable iclk bit for SDRC
+        bic     r12, r12, #0x2          @ disable iclk bit for SDRC
-        str     r5, [r4]
+        str     r12, [r11]
 wait_sdrc_idle:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2            @ check for SDRC idle
+        and     r12, r12, #0x2          @ check for SDRC idle
-        cmp     r5, #2
+        cmp     r12, #2
        bne     wait_sdrc_idle
        bx      lr
 configure_core_dpll:
-        ldr     r4, omap3_cm_clksel1_pll
+        ldr     r11, omap3_cm_clksel1_pll
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        ldr     r6, core_m2_mask_val    @ modify m2 for core dpll
+        ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
-        and     r5, r5, r6
+        and     r12, r12, r10
-        orr     r5, r5, r3, lsl #0x1B   @ r3 contains the M2 val
+        orr     r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
-        str     r5, [r4]
+        str     r12, [r11]
-        ldr     r5, [r4]                @ posted-write barrier for CM
+        ldr     r12, [r11]              @ posted-write barrier for CM
-        mov     r5, #0x800              @ wait for the clock to stabilise
+        mov     r12, #0x800             @ wait for the clock to stabilise
        cmp     r3, #2
        bne     wait_clk_stable
        bx      lr
 wait_clk_stable:
-        subs    r5, r5, #1
+        subs    r12, r12, #1
        bne     wait_clk_stable
        nop
        nop
@@ -120,42 +120,42 @@ wait_clk_stable:
        nop
        bx      lr
 enable_sdrc:
-        ldr     r4, omap3_cm_iclken1_core
+        ldr     r11, omap3_cm_iclken1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x2            @ enable iclk bit for SDRC
+        orr     r12, r12, #0x2          @ enable iclk bit for SDRC
-        str     r5, [r4]
+        str     r12, [r11]
 wait_sdrc_idle1:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2
+        and     r12, r12, #0x2
-        cmp     r5, #0
+        cmp     r12, #0
        bne     wait_sdrc_idle1
 restore_sdrc_power_val:
-        ldr     r4, omap3_sdrc_power
+        ldr     r11, omap3_sdrc_power
-        str     r9, [r4]                @ restore SDRC_POWER, no barrier needed
+        str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
        bx      lr
 wait_dll_lock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x4
+        cmp     r12, #0x4
        bne     wait_dll_lock
        bx      lr
 wait_dll_unlock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x0
+        cmp     r12, #0x0
        bne     wait_dll_unlock
        bx      lr
 configure_sdrc:
-        ldr     r4, omap3_sdrc_rfr_ctrl
+        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r4]
+        str     r0, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrla
+        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r4]
+        str     r1, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrlb
+        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r4]
+        str     r2, [r11]
-        ldr     r2, [r4]                @ posted-write barrier for SDRC
+        ldr     r2, [r11]               @ posted-write barrier for SDRC
        bx      lr
 omap3_sdrc_power:
author	Paul Walmsley <paul@pwsan.com>	2009-05-12 19:27:10 -0400
committer	paul <paul@twilight.(none)>	2009-05-12 19:27:10 -0400
commit	b2abb271a5705bc80478e79d95fc9f3babc2605c (patch)
tree	1c3272b5b66d9589a974a19d76a527c33e0f5677 /arch/arm/mach-omap2/sram34xx.S
parent	98cfe5abf24c6d2f06b70fa8a8a111681bed3ed9 (diff)

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 9a454151c422..35131e5bc7d1 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S
@@ -63,50 +63,50 @@ ENTRY(omap3_sram_configure_core_dpll)
63	mov r0, #0 @ return value	63	mov r0, #0 @ return value
64	ldmfd sp!, {r1-r12, pc} @ restore regs and return	64	ldmfd sp!, {r1-r12, pc} @ restore regs and return
65	unlock_dll:	65	unlock_dll:
66	ldr r4, omap3_sdrc_dlla_ctrl	66	ldr r11, omap3_sdrc_dlla_ctrl
67	ldr r5, [r4]	67	ldr r12, [r11]
68	orr r5, r5, #0x4	68	orr r12, r12, #0x4
69	str r5, [r4] @ (no OCP barrier needed)	69	str r12, [r11] @ (no OCP barrier needed)
70	bx lr	70	bx lr
71	lock_dll:	71	lock_dll:
72	ldr r4, omap3_sdrc_dlla_ctrl	72	ldr r11, omap3_sdrc_dlla_ctrl
73	ldr r5, [r4]	73	ldr r12, [r11]
74	bic r5, r5, #0x4	74	bic r12, r12, #0x4
75	str r5, [r4] @ (no OCP barrier needed)	75	str r12, [r11] @ (no OCP barrier needed)
76	bx lr	76	bx lr
77	sdram_in_selfrefresh:	77	sdram_in_selfrefresh:
78	ldr r4, omap3_sdrc_power @ read the SDRC_POWER register	78	ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
79	ldr r5, [r4] @ read the contents of SDRC_POWER	79	ldr r12, [r11] @ read the contents of SDRC_POWER
80	mov r9, r5 @ keep a copy of SDRC_POWER bits	80	mov r9, r12 @ keep a copy of SDRC_POWER bits
81	orr r5, r5, #0x40 @ enable self refresh on idle req	81	orr r12, r12, #0x40 @ enable self refresh on idle req
82	bic r5, r5, #0x4 @ clear PWDENA	82	bic r12, r12, #0x4 @ clear PWDENA
83	str r5, [r4] @ write back to SDRC_POWER register	83	str r12, [r11] @ write back to SDRC_POWER register
84	ldr r5, [r4] @ posted-write barrier for SDRC	84	ldr r12, [r11] @ posted-write barrier for SDRC
85	ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg	85	ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
86	ldr r5, [r4]	86	ldr r12, [r11]
87	bic r5, r5, #0x2 @ disable iclk bit for SDRC	87	bic r12, r12, #0x2 @ disable iclk bit for SDRC
88	str r5, [r4]	88	str r12, [r11]
89	wait_sdrc_idle:	89	wait_sdrc_idle:
90	ldr r4, omap3_cm_idlest1_core	90	ldr r11, omap3_cm_idlest1_core
91	ldr r5, [r4]	91	ldr r12, [r11]
92	and r5, r5, #0x2 @ check for SDRC idle	92	and r12, r12, #0x2 @ check for SDRC idle
93	cmp r5, #2	93	cmp r12, #2
94	bne wait_sdrc_idle	94	bne wait_sdrc_idle
95	bx lr	95	bx lr
96	configure_core_dpll:	96	configure_core_dpll:
97	ldr r4, omap3_cm_clksel1_pll	97	ldr r11, omap3_cm_clksel1_pll
98	ldr r5, [r4]	98	ldr r12, [r11]
99	ldr r6, core_m2_mask_val @ modify m2 for core dpll	99	ldr r10, core_m2_mask_val @ modify m2 for core dpll
100	and r5, r5, r6	100	and r12, r12, r10
101	orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val	101	orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
102	str r5, [r4]	102	str r12, [r11]
103	ldr r5, [r4] @ posted-write barrier for CM	103	ldr r12, [r11] @ posted-write barrier for CM
104	mov r5, #0x800 @ wait for the clock to stabilise	104	mov r12, #0x800 @ wait for the clock to stabilise
105	cmp r3, #2	105	cmp r3, #2
106	bne wait_clk_stable	106	bne wait_clk_stable
107	bx lr	107	bx lr
108	wait_clk_stable:	108	wait_clk_stable:
109	subs r5, r5, #1	109	subs r12, r12, #1
110	bne wait_clk_stable	110	bne wait_clk_stable
111	nop	111	nop
112	nop	112	nop
@@ -120,42 +120,42 @@ wait_clk_stable:
120	nop	120	nop
121	bx lr	121	bx lr
122	enable_sdrc:	122	enable_sdrc:
123	ldr r4, omap3_cm_iclken1_core	123	ldr r11, omap3_cm_iclken1_core
124	ldr r5, [r4]	124	ldr r12, [r11]
125	orr r5, r5, #0x2 @ enable iclk bit for SDRC	125	orr r12, r12, #0x2 @ enable iclk bit for SDRC
126	str r5, [r4]	126	str r12, [r11]
127	wait_sdrc_idle1:	127	wait_sdrc_idle1:
128	ldr r4, omap3_cm_idlest1_core	128	ldr r11, omap3_cm_idlest1_core
129	ldr r5, [r4]	129	ldr r12, [r11]
130	and r5, r5, #0x2	130	and r12, r12, #0x2
131	cmp r5, #0	131	cmp r12, #0
132	bne wait_sdrc_idle1	132	bne wait_sdrc_idle1
133	restore_sdrc_power_val:	133	restore_sdrc_power_val:
134	ldr r4, omap3_sdrc_power	134	ldr r11, omap3_sdrc_power
135	str r9, [r4] @ restore SDRC_POWER, no barrier needed	135	str r9, [r11] @ restore SDRC_POWER, no barrier needed
136	bx lr	136	bx lr
137	wait_dll_lock:	137	wait_dll_lock:
138	ldr r4, omap3_sdrc_dlla_status	138	ldr r11, omap3_sdrc_dlla_status
139	ldr r5, [r4]	139	ldr r12, [r11]
140	and r5, r5, #0x4	140	and r12, r12, #0x4
141	cmp r5, #0x4	141	cmp r12, #0x4
142	bne wait_dll_lock	142	bne wait_dll_lock
143	bx lr	143	bx lr
144	wait_dll_unlock:	144	wait_dll_unlock:
145	ldr r4, omap3_sdrc_dlla_status	145	ldr r11, omap3_sdrc_dlla_status
146	ldr r5, [r4]	146	ldr r12, [r11]
147	and r5, r5, #0x4	147	and r12, r12, #0x4
148	cmp r5, #0x0	148	cmp r12, #0x0
149	bne wait_dll_unlock	149	bne wait_dll_unlock
150	bx lr	150	bx lr
151	configure_sdrc:	151	configure_sdrc:
152	ldr r4, omap3_sdrc_rfr_ctrl	152	ldr r11, omap3_sdrc_rfr_ctrl
153	str r0, [r4]	153	str r0, [r11]
154	ldr r4, omap3_sdrc_actim_ctrla	154	ldr r11, omap3_sdrc_actim_ctrla
155	str r1, [r4]	155	str r1, [r11]
156	ldr r4, omap3_sdrc_actim_ctrlb	156	ldr r11, omap3_sdrc_actim_ctrlb
157	str r2, [r4]	157	str r2, [r11]
158	ldr r2, [r4] @ posted-write barrier for SDRC	158	ldr r2, [r11] @ posted-write barrier for SDRC
159	bx lr	159	bx lr
160		160
161	omap3_sdrc_power:	161	omap3_sdrc_power: