Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits) MAINTAINERS: EB110ATX is not ebsa110 MAINTAINERS: update Eric Miao's email address and status fb: add support of LCD display controller on pxa168/910 (base layer) [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines [ARM] 5544/1: Trust PrimeCell resource sizes [ARM] pxa/sharpsl_pm: cleanup of gpio-related code. [ARM] pxa/sharpsl_pm: drop set_irq_type calls [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific [ARM] sa1100: remove unused collie_pm.c [ARM] pxa: fix the conflicting non-static declarations of global_gpios[] [ARM] 5550/1: Add default configure file for w90p910 platform [ARM] 5549/1: Add clock api for w90p910 platform. [ARM] 5548/1: Add gpio api for w90p910 platform [ARM] 5551/1: Add multi-function pin api for w90p910 platform. [ARM] Make ARM_VIC_NR depend on ARM_VIC [ARM] 5546/1: ARM PL022 SSP/SPI driver v3 ARM: OMAP4: SMP: Update defconfig for OMAP4430 ARM: OMAP4: SMP: Enable SMP support for OMAP4430 ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2009-06-14 16:42:43 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2009-06-14 16:42:43 -0400
commit: 2cf4d4514d5b43c1f3b64bd0ec8b9853bde8f1dc (patch)
tree: e35a625496acc6ac852846d40b8851186b9d1ac4 /arch/arm/mach-omap2/sram34xx.S
parent: 44b7532b8b464f606053562400719c9c21276037 (diff)
parent: ce53895a5d24e0ee19fb92f56c17323fb4c9ab27 (diff)
1 files changed, 67 insertions, 62 deletions
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 2c7146136342..c080c82521e1 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -40,69 +40,74 @@
 /*
 * Change frequency of core dpll
 * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
+ * r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
+ *      SDRC rates < 83MHz
 */
 ENTRY(omap3_sram_configure_core_dpll)
        stmfd   sp!, {r1-r12, lr}       @ store regs to stack
+        ldr     r4, [sp, #52]           @ pull extra args off the stack
+        dsb                             @ flush buffered writes to interconnect
        cmp     r3, #0x2
        blne    configure_sdrc
-        cmp     r3, #0x2
+        cmp     r4, #0x1
+        bleq    unlock_dll
        blne    lock_dll
-        cmp     r3, #0x1
-        blne    unlock_dll
        bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
        bl      configure_core_dpll
        bl      enable_sdrc
-        cmp     r3, #0x1
+        cmp     r4, #0x1
-        blne    wait_dll_unlock
+        bleq    wait_dll_unlock
-        cmp     r3, #0x2
        blne    wait_dll_lock
        cmp     r3, #0x1
        blne    configure_sdrc
+        isb                             @ prevent speculative exec past here
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 unlock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x4
+        orr     r12, r12, #0x4
-        str     r5, [r4]
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 lock_dll:
-        ldr     r4, omap3_sdrc_dlla_ctrl
+        ldr     r11, omap3_sdrc_dlla_ctrl
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        bic     r5, r5, #0x4
+        bic     r12, r12, #0x4
-        str     r5, [r4]
+        str     r12, [r11]              @ (no OCP barrier needed)
        bx      lr
 sdram_in_selfrefresh:
-        mov     r5, #0x0                @ Move 0 to R5
+        ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
-        mcr     p15, 0, r5, c7, c10, 5  @ memory barrier
+        ldr     r12, [r11]              @ read the contents of SDRC_POWER
-        ldr     r4, omap3_sdrc_power    @ read the SDRC_POWER register
+        mov     r9, r12                 @ keep a copy of SDRC_POWER bits
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r12, r12, #0x40         @ enable self refresh on idle req
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        bic     r12, r12, #0x4          @ clear PWDENA
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        str     r12, [r11]              @ write back to SDRC_POWER register
-        ldr     r4, omap3_cm_iclken1_core       @ read the CM_ICLKEN1_CORE reg
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
-        ldr     r5, [r4]
+        ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
-        bic     r5, r5, #0x2            @ disable iclk bit for SRDC
+        ldr     r12, [r11]
-        str     r5, [r4]
+        bic     r12, r12, #0x2          @ disable iclk bit for SDRC
+        str     r12, [r11]
 wait_sdrc_idle:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2            @ check for SDRC idle
+        and     r12, r12, #0x2          @ check for SDRC idle
-        cmp     r5, #2
+        cmp     r12, #2
        bne     wait_sdrc_idle
        bx      lr
 configure_core_dpll:
-        ldr     r4, omap3_cm_clksel1_pll
+        ldr     r11, omap3_cm_clksel1_pll
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        ldr     r6, core_m2_mask_val    @ modify m2 for core dpll
+        ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
-        and     r5, r5, r6
+        and     r12, r12, r10
-        orr     r5, r5, r3, lsl #0x1B   @ r3 contains the M2 val
+        orr     r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
-        str     r5, [r4]
+        str     r12, [r11]
-        mov     r5, #0x800              @ wait for the clock to stabilise
+        ldr     r12, [r11]              @ posted-write barrier for CM
+        mov     r12, #0x800             @ wait for the clock to stabilise
        cmp     r3, #2
        bne     wait_clk_stable
        bx      lr
 wait_clk_stable:
-        subs    r5, r5, #1
+        subs    r12, r12, #1
        bne     wait_clk_stable
        nop
        nop
@@ -116,42 +121,42 @@ wait_clk_stable:
        nop
        bx      lr
 enable_sdrc:
-        ldr     r4, omap3_cm_iclken1_core
+        ldr     r11, omap3_cm_iclken1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        orr     r5, r5, #0x2            @ enable iclk bit for SDRC
+        orr     r12, r12, #0x2          @ enable iclk bit for SDRC
-        str     r5, [r4]
+        str     r12, [r11]
 wait_sdrc_idle1:
-        ldr     r4, omap3_cm_idlest1_core
+        ldr     r11, omap3_cm_idlest1_core
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x2
+        and     r12, r12, #0x2
-        cmp     r5, #0
+        cmp     r12, #0
        bne     wait_sdrc_idle1
-        ldr     r4, omap3_sdrc_power
+restore_sdrc_power_val:
-        ldr     r5, [r4]
+        ldr     r11, omap3_sdrc_power
-        bic     r5, r5, #0x40
+        str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
-        str     r5, [r4]
        bx      lr
 wait_dll_lock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x4
+        cmp     r12, #0x4
        bne     wait_dll_lock
        bx      lr
 wait_dll_unlock:
-        ldr     r4, omap3_sdrc_dlla_status
+        ldr     r11, omap3_sdrc_dlla_status
-        ldr     r5, [r4]
+        ldr     r12, [r11]
-        and     r5, r5, #0x4
+        and     r12, r12, #0x4
-        cmp     r5, #0x0
+        cmp     r12, #0x0
        bne     wait_dll_unlock
        bx      lr
 configure_sdrc:
-        ldr     r4, omap3_sdrc_rfr_ctrl
+        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r4]
+        str     r0, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrla
+        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r4]
+        str     r1, [r11]
-        ldr     r4, omap3_sdrc_actim_ctrlb
+        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r4]
+        str     r2, [r11]
+        ldr     r2, [r11]               @ posted-write barrier for SDRC
        bx      lr
 omap3_sdrc_power:
author	Linus Torvalds <torvalds@linux-foundation.org>	2009-06-14 16:42:43 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2009-06-14 16:42:43 -0400
commit	2cf4d4514d5b43c1f3b64bd0ec8b9853bde8f1dc (patch)
tree	e35a625496acc6ac852846d40b8851186b9d1ac4 /arch/arm/mach-omap2/sram34xx.S
parent	44b7532b8b464f606053562400719c9c21276037 (diff)
parent	ce53895a5d24e0ee19fb92f56c17323fb4c9ab27 (diff)

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 2c7146136342..c080c82521e1 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S
@@ -40,69 +40,74 @@
40	/*	40	/*
41	* Change frequency of core dpll	41	* Change frequency of core dpll
42	* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2	42	* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
		43	* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
		44	* SDRC rates < 83MHz
43	*/	45	*/
44	ENTRY(omap3_sram_configure_core_dpll)	46	ENTRY(omap3_sram_configure_core_dpll)
45	stmfd sp!, {r1-r12, lr} @ store regs to stack	47	stmfd sp!, {r1-r12, lr} @ store regs to stack
		48	ldr r4, [sp, #52] @ pull extra args off the stack
		49	dsb @ flush buffered writes to interconnect
46	cmp r3, #0x2	50	cmp r3, #0x2
47	blne configure_sdrc	51	blne configure_sdrc
48	cmp r3, #0x2	52	cmp r4, #0x1
		53	bleq unlock_dll
49	blne lock_dll	54	blne lock_dll
50	cmp r3, #0x1
51	blne unlock_dll
52	bl sdram_in_selfrefresh @ put the SDRAM in self refresh	55	bl sdram_in_selfrefresh @ put the SDRAM in self refresh
53	bl configure_core_dpll	56	bl configure_core_dpll
54	bl enable_sdrc	57	bl enable_sdrc
55	cmp r3, #0x1	58	cmp r4, #0x1
56	blne wait_dll_unlock	59	bleq wait_dll_unlock
57	cmp r3, #0x2
58	blne wait_dll_lock	60	blne wait_dll_lock
59	cmp r3, #0x1	61	cmp r3, #0x1
60	blne configure_sdrc	62	blne configure_sdrc
		63	isb @ prevent speculative exec past here
61	mov r0, #0 @ return value	64	mov r0, #0 @ return value
62	ldmfd sp!, {r1-r12, pc} @ restore regs and return	65	ldmfd sp!, {r1-r12, pc} @ restore regs and return
63	unlock_dll:	66	unlock_dll:
64	ldr r4, omap3_sdrc_dlla_ctrl	67	ldr r11, omap3_sdrc_dlla_ctrl
65	ldr r5, [r4]	68	ldr r12, [r11]
66	orr r5, r5, #0x4	69	orr r12, r12, #0x4
67	str r5, [r4]	70	str r12, [r11] @ (no OCP barrier needed)
68	bx lr	71	bx lr
69	lock_dll:	72	lock_dll:
70	ldr r4, omap3_sdrc_dlla_ctrl	73	ldr r11, omap3_sdrc_dlla_ctrl
71	ldr r5, [r4]	74	ldr r12, [r11]
72	bic r5, r5, #0x4	75	bic r12, r12, #0x4
73	str r5, [r4]	76	str r12, [r11] @ (no OCP barrier needed)
74	bx lr	77	bx lr
75	sdram_in_selfrefresh:	78	sdram_in_selfrefresh:
76	mov r5, #0x0 @ Move 0 to R5	79	ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
77	mcr p15, 0, r5, c7, c10, 5 @ memory barrier	80	ldr r12, [r11] @ read the contents of SDRC_POWER
78	ldr r4, omap3_sdrc_power @ read the SDRC_POWER register	81	mov r9, r12 @ keep a copy of SDRC_POWER bits
79	ldr r5, [r4] @ read the contents of SDRC_POWER	82	orr r12, r12, #0x40 @ enable self refresh on idle req
80	orr r5, r5, #0x40 @ enable self refresh on idle req	83	bic r12, r12, #0x4 @ clear PWDENA
81	str r5, [r4] @ write back to SDRC_POWER register	84	str r12, [r11] @ write back to SDRC_POWER register
82	ldr r4, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg	85	ldr r12, [r11] @ posted-write barrier for SDRC
83	ldr r5, [r4]	86	ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
84	bic r5, r5, #0x2 @ disable iclk bit for SRDC	87	ldr r12, [r11]
85	str r5, [r4]	88	bic r12, r12, #0x2 @ disable iclk bit for SDRC
		89	str r12, [r11]
86	wait_sdrc_idle:	90	wait_sdrc_idle:
87	ldr r4, omap3_cm_idlest1_core	91	ldr r11, omap3_cm_idlest1_core
88	ldr r5, [r4]	92	ldr r12, [r11]
89	and r5, r5, #0x2 @ check for SDRC idle	93	and r12, r12, #0x2 @ check for SDRC idle
90	cmp r5, #2	94	cmp r12, #2
91	bne wait_sdrc_idle	95	bne wait_sdrc_idle
92	bx lr	96	bx lr
93	configure_core_dpll:	97	configure_core_dpll:
94	ldr r4, omap3_cm_clksel1_pll	98	ldr r11, omap3_cm_clksel1_pll
95	ldr r5, [r4]	99	ldr r12, [r11]
96	ldr r6, core_m2_mask_val @ modify m2 for core dpll	100	ldr r10, core_m2_mask_val @ modify m2 for core dpll
97	and r5, r5, r6	101	and r12, r12, r10
98	orr r5, r5, r3, lsl #0x1B @ r3 contains the M2 val	102	orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
99	str r5, [r4]	103	str r12, [r11]
100	mov r5, #0x800 @ wait for the clock to stabilise	104	ldr r12, [r11] @ posted-write barrier for CM
		105	mov r12, #0x800 @ wait for the clock to stabilise
101	cmp r3, #2	106	cmp r3, #2
102	bne wait_clk_stable	107	bne wait_clk_stable
103	bx lr	108	bx lr
104	wait_clk_stable:	109	wait_clk_stable:
105	subs r5, r5, #1	110	subs r12, r12, #1
106	bne wait_clk_stable	111	bne wait_clk_stable
107	nop	112	nop
108	nop	113	nop
@@ -116,42 +121,42 @@ wait_clk_stable:
116	nop	121	nop
117	bx lr	122	bx lr
118	enable_sdrc:	123	enable_sdrc:
119	ldr r4, omap3_cm_iclken1_core	124	ldr r11, omap3_cm_iclken1_core
120	ldr r5, [r4]	125	ldr r12, [r11]
121	orr r5, r5, #0x2 @ enable iclk bit for SDRC	126	orr r12, r12, #0x2 @ enable iclk bit for SDRC
122	str r5, [r4]	127	str r12, [r11]
123	wait_sdrc_idle1:	128	wait_sdrc_idle1:
124	ldr r4, omap3_cm_idlest1_core	129	ldr r11, omap3_cm_idlest1_core
125	ldr r5, [r4]	130	ldr r12, [r11]
126	and r5, r5, #0x2	131	and r12, r12, #0x2
127	cmp r5, #0	132	cmp r12, #0
128	bne wait_sdrc_idle1	133	bne wait_sdrc_idle1
129	ldr r4, omap3_sdrc_power	134	restore_sdrc_power_val:
130	ldr r5, [r4]	135	ldr r11, omap3_sdrc_power
131	bic r5, r5, #0x40	136	str r9, [r11] @ restore SDRC_POWER, no barrier needed
132	str r5, [r4]
133	bx lr	137	bx lr
134	wait_dll_lock:	138	wait_dll_lock:
135	ldr r4, omap3_sdrc_dlla_status	139	ldr r11, omap3_sdrc_dlla_status
136	ldr r5, [r4]	140	ldr r12, [r11]
137	and r5, r5, #0x4	141	and r12, r12, #0x4
138	cmp r5, #0x4	142	cmp r12, #0x4
139	bne wait_dll_lock	143	bne wait_dll_lock
140	bx lr	144	bx lr
141	wait_dll_unlock:	145	wait_dll_unlock:
142	ldr r4, omap3_sdrc_dlla_status	146	ldr r11, omap3_sdrc_dlla_status
143	ldr r5, [r4]	147	ldr r12, [r11]
144	and r5, r5, #0x4	148	and r12, r12, #0x4
145	cmp r5, #0x0	149	cmp r12, #0x0
146	bne wait_dll_unlock	150	bne wait_dll_unlock
147	bx lr	151	bx lr
148	configure_sdrc:	152	configure_sdrc:
149	ldr r4, omap3_sdrc_rfr_ctrl	153	ldr r11, omap3_sdrc_rfr_ctrl
150	str r0, [r4]	154	str r0, [r11]
151	ldr r4, omap3_sdrc_actim_ctrla	155	ldr r11, omap3_sdrc_actim_ctrla
152	str r1, [r4]	156	str r1, [r11]
153	ldr r4, omap3_sdrc_actim_ctrlb	157	ldr r11, omap3_sdrc_actim_ctrlb
154	str r2, [r4]	158	str r2, [r11]
		159	ldr r2, [r11] @ posted-write barrier for SDRC
155	bx lr	160	bx lr
156		161
157	omap3_sdrc_power:	162	omap3_sdrc_power: