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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-01-23 08:30:34 -0500
committerKevin Hilman <khilman@ti.com>2011-03-10 15:23:12 -0500
commit4444d712fd5b31f2348b57eaa2bbdc5e68c4e1b6 (patch)
tree049e428aaddc72e916c8850b19474006dd360a51 /arch/arm/mach-omap2/sleep34xx.S
parentb1ace38094c4926255343a81faba8fb4faf59a45 (diff)
OMAP3: PM: Use ARMv7 supported instructions instead of legacy CP15 ones
On ARMv7 dsb, dmb instructions are supported and can be used directly instead of their cp15 equivalnet. Also remove the opcodes for smc and use the available instruction directly in OMAP3 low power asm code Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/sleep34xx.S')
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S21
1 files changed, 10 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 0c1b33511fed..1c17ee81cb12 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -144,8 +144,8 @@ ENTRY(save_secure_ram_context)
144 mov r1, #0 @ set task id for ROM code in r1 144 mov r1, #0 @ set task id for ROM code in r1
145 mov r2, #4 @ set some flags in r2, r6 145 mov r2, #4 @ set some flags in r2, r6
146 mov r6, #0xff 146 mov r6, #0xff
147 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 147 dsb @ data write barrier
148 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 148 dmb @ data memory barrier
149 smc #1 @ call SMI monitor (smi #1) 149 smc #1 @ call SMI monitor (smi #1)
150 nop 150 nop
151 nop 151 nop
@@ -314,9 +314,8 @@ omap3_do_wfi:
314 str r5, [r4] @ write back to SDRC_POWER register 314 str r5, [r4] @ write back to SDRC_POWER register
315 315
316 /* Data memory barrier and Data sync barrier */ 316 /* Data memory barrier and Data sync barrier */
317 mov r1, #0 317 dsb
318 mcr p15, 0, r1, c7, c10, 4 318 dmb
319 mcr p15, 0, r1, c7, c10, 5
320 319
321/* 320/*
322 * =================================== 321 * ===================================
@@ -431,8 +430,8 @@ skipl2dis:
431 mov r2, #4 @ set some flags in r2, r6 430 mov r2, #4 @ set some flags in r2, r6
432 mov r6, #0xff 431 mov r6, #0xff
433 adr r3, l2_inv_api_params @ r3 points to dummy parameters 432 adr r3, l2_inv_api_params @ r3 points to dummy parameters
434 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 433 dsb @ data write barrier
435 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 434 dmb @ data memory barrier
436 smc #1 @ call SMI monitor (smi #1) 435 smc #1 @ call SMI monitor (smi #1)
437 /* Write to Aux control register to set some bits */ 436 /* Write to Aux control register to set some bits */
438 mov r0, #42 @ set service ID for PPA 437 mov r0, #42 @ set service ID for PPA
@@ -442,8 +441,8 @@ skipl2dis:
442 mov r6, #0xff 441 mov r6, #0xff
443 ldr r4, scratchpad_base 442 ldr r4, scratchpad_base
444 ldr r3, [r4, #0xBC] @ r3 points to parameters 443 ldr r3, [r4, #0xBC] @ r3 points to parameters
445 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 444 dsb @ data write barrier
446 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 445 dmb @ data memory barrier
447 smc #1 @ call SMI monitor (smi #1) 446 smc #1 @ call SMI monitor (smi #1)
448 447
449#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE 448#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
@@ -457,8 +456,8 @@ skipl2dis:
457 ldr r4, scratchpad_base 456 ldr r4, scratchpad_base
458 ldr r3, [r4, #0xBC] 457 ldr r3, [r4, #0xBC]
459 adds r3, r3, #8 @ r3 points to parameters 458 adds r3, r3, #8 @ r3 points to parameters
460 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 459 dsb @ data write barrier
461 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier 460 dmb @ data memory barrier
462 smc #1 @ call SMI monitor (smi #1) 461 smc #1 @ call SMI monitor (smi #1)
463#endif 462#endif
464 b logic_l1_restore 463 b logic_l1_restore