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authorNishanth Menon <nm@ti.com>2010-08-02 06:18:12 -0400
committerTony Lindgren <tony@atomide.com>2010-08-02 06:18:12 -0400
commit5a927b36f56c2a937e67f0947f233f723660f690 (patch)
tree5dba76203c4da869632c511b7175187497ff2242 /arch/arm/mach-omap2/serial.c
parentbfe6977ac7b96e5a6665546c0efd733cd290d0ca (diff)
omap2/3/4: serial: introduce errata handling
introduce silicon specific quirks as a errata handling mechanism as a start UART_ERRATA_FIFO_FULL_ABORT is used to handle the override for fifo full condition for rx and tx. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/serial.c')
-rw-r--r--arch/arm/mach-omap2/serial.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 584a2ed39ab4..009b63fc79f0 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -37,6 +37,8 @@
37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 37#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
38#define UART_OMAP_WER 0x17 /* Wake-up enable register */ 38#define UART_OMAP_WER 0x17 /* Wake-up enable register */
39 39
40#define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0)
41
40/* 42/*
41 * NOTE: By default the serial timeout is disabled as it causes lost characters 43 * NOTE: By default the serial timeout is disabled as it causes lost characters
42 * over the serial ports. This means that the UART clocks will stay on until 44 * over the serial ports. This means that the UART clocks will stay on until
@@ -64,6 +66,7 @@ struct omap_uart_state {
64 struct list_head node; 66 struct list_head node;
65 struct platform_device pdev; 67 struct platform_device pdev;
66 68
69 u32 errata;
67#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 70#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
68 int context_valid; 71 int context_valid;
69 72
@@ -756,11 +759,13 @@ void __init omap_serial_init_port(int port)
756 * omap3xxx: Never read empty UART fifo on UARTs 759 * omap3xxx: Never read empty UART fifo on UARTs
757 * with IP rev >=0x52 760 * with IP rev >=0x52
758 */ 761 */
759 if (cpu_is_omap44xx()) { 762 if (cpu_is_omap44xx())
760 uart->p->serial_in = serial_in_override; 763 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
761 uart->p->serial_out = serial_out_override; 764 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
762 } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) 765 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
763 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) { 766 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
767
768 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
764 uart->p->serial_in = serial_in_override; 769 uart->p->serial_in = serial_in_override;
765 uart->p->serial_out = serial_out_override; 770 uart->p->serial_out = serial_out_override;
766 } 771 }