diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-14 17:24:42 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-14 17:24:42 -0400 |
commit | b6825d2df55aa7d7341c715b577b73a6a03dc944 (patch) | |
tree | ae4f0f52f4c2ad4e501dd323318486ccdd7fcd93 /arch/arm/mach-omap2/serial.c | |
parent | 6defd90433729c2d795865165cb34d938d8ff07c (diff) | |
parent | aa59e19d05114f9fb7718d6bc8398255476fb4f5 (diff) |
Merge branch 'omap-all' into devel
Conflicts:
arch/arm/mach-omap2/gpmc.c
arch/arm/mach-omap2/irq.c
Diffstat (limited to 'arch/arm/mach-omap2/serial.c')
-rw-r--r-- | arch/arm/mach-omap2/serial.c | 116 |
1 files changed, 48 insertions, 68 deletions
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 7d9444adc5df..4dcf39c285b9 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * OMAP2 serial support. | 4 | * OMAP2 serial support. |
5 | * | 5 | * |
6 | * Copyright (C) 2005 Nokia Corporation | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
8 | * | 8 | * |
9 | * Based off of arch/arm/mach-omap/omap1/serial.c | 9 | * Based off of arch/arm/mach-omap/omap1/serial.c |
@@ -22,38 +22,34 @@ | |||
22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
23 | #include <mach/board.h> | 23 | #include <mach/board.h> |
24 | 24 | ||
25 | static struct clk * uart1_ick = NULL; | 25 | static struct clk *uart_ick[OMAP_MAX_NR_PORTS]; |
26 | static struct clk * uart1_fck = NULL; | 26 | static struct clk *uart_fck[OMAP_MAX_NR_PORTS]; |
27 | static struct clk * uart2_ick = NULL; | ||
28 | static struct clk * uart2_fck = NULL; | ||
29 | static struct clk * uart3_ick = NULL; | ||
30 | static struct clk * uart3_fck = NULL; | ||
31 | 27 | ||
32 | static struct plat_serial8250_port serial_platform_data[] = { | 28 | static struct plat_serial8250_port serial_platform_data[] = { |
33 | { | 29 | { |
34 | .membase = (char *)IO_ADDRESS(OMAP_UART1_BASE), | 30 | .membase = IO_ADDRESS(OMAP_UART1_BASE), |
35 | .mapbase = (unsigned long)OMAP_UART1_BASE, | 31 | .mapbase = OMAP_UART1_BASE, |
36 | .irq = 72, | 32 | .irq = 72, |
37 | .flags = UPF_BOOT_AUTOCONF, | 33 | .flags = UPF_BOOT_AUTOCONF, |
38 | .iotype = UPIO_MEM, | 34 | .iotype = UPIO_MEM, |
39 | .regshift = 2, | 35 | .regshift = 2, |
40 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 36 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
41 | }, { | 37 | }, { |
42 | .membase = (char *)IO_ADDRESS(OMAP_UART2_BASE), | 38 | .membase = IO_ADDRESS(OMAP_UART2_BASE), |
43 | .mapbase = (unsigned long)OMAP_UART2_BASE, | 39 | .mapbase = OMAP_UART2_BASE, |
44 | .irq = 73, | 40 | .irq = 73, |
45 | .flags = UPF_BOOT_AUTOCONF, | 41 | .flags = UPF_BOOT_AUTOCONF, |
46 | .iotype = UPIO_MEM, | 42 | .iotype = UPIO_MEM, |
47 | .regshift = 2, | 43 | .regshift = 2, |
48 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 44 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
49 | }, { | 45 | }, { |
50 | .membase = (char *)IO_ADDRESS(OMAP_UART3_BASE), | 46 | .membase = IO_ADDRESS(OMAP_UART3_BASE), |
51 | .mapbase = (unsigned long)OMAP_UART3_BASE, | 47 | .mapbase = OMAP_UART3_BASE, |
52 | .irq = 74, | 48 | .irq = 74, |
53 | .flags = UPF_BOOT_AUTOCONF, | 49 | .flags = UPF_BOOT_AUTOCONF, |
54 | .iotype = UPIO_MEM, | 50 | .iotype = UPIO_MEM, |
55 | .regshift = 2, | 51 | .regshift = 2, |
56 | .uartclk = OMAP16XX_BASE_BAUD * 16, | 52 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
57 | }, { | 53 | }, { |
58 | .flags = 0 | 54 | .flags = 0 |
59 | } | 55 | } |
@@ -70,7 +66,7 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, | |||
70 | int value) | 66 | int value) |
71 | { | 67 | { |
72 | offset <<= p->regshift; | 68 | offset <<= p->regshift; |
73 | __raw_writeb(value, (unsigned long)(p->membase + offset)); | 69 | __raw_writeb(value, p->membase + offset); |
74 | } | 70 | } |
75 | 71 | ||
76 | /* | 72 | /* |
@@ -86,10 +82,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p) | |||
86 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); | 82 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); |
87 | } | 83 | } |
88 | 84 | ||
89 | void __init omap_serial_init() | 85 | void omap_serial_enable_clocks(int enable) |
86 | { | ||
87 | int i; | ||
88 | for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { | ||
89 | if (uart_ick[i] && uart_fck[i]) { | ||
90 | if (enable) { | ||
91 | clk_enable(uart_ick[i]); | ||
92 | clk_enable(uart_fck[i]); | ||
93 | } else { | ||
94 | clk_disable(uart_ick[i]); | ||
95 | clk_disable(uart_fck[i]); | ||
96 | } | ||
97 | } | ||
98 | } | ||
99 | } | ||
100 | |||
101 | void __init omap_serial_init(void) | ||
90 | { | 102 | { |
91 | int i; | 103 | int i; |
92 | const struct omap_uart_config *info; | 104 | const struct omap_uart_config *info; |
105 | char name[16]; | ||
93 | 106 | ||
94 | /* | 107 | /* |
95 | * Make sure the serial ports are muxed on at this point. | 108 | * Make sure the serial ports are muxed on at this point. |
@@ -97,8 +110,7 @@ void __init omap_serial_init() | |||
97 | * if not needed. | 110 | * if not needed. |
98 | */ | 111 | */ |
99 | 112 | ||
100 | info = omap_get_config(OMAP_TAG_UART, | 113 | info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); |
101 | struct omap_uart_config); | ||
102 | 114 | ||
103 | if (info == NULL) | 115 | if (info == NULL) |
104 | return; | 116 | return; |
@@ -107,58 +119,26 @@ void __init omap_serial_init() | |||
107 | struct plat_serial8250_port *p = serial_platform_data + i; | 119 | struct plat_serial8250_port *p = serial_platform_data + i; |
108 | 120 | ||
109 | if (!(info->enabled_uarts & (1 << i))) { | 121 | if (!(info->enabled_uarts & (1 << i))) { |
110 | p->membase = 0; | 122 | p->membase = NULL; |
111 | p->mapbase = 0; | 123 | p->mapbase = 0; |
112 | continue; | 124 | continue; |
113 | } | 125 | } |
114 | 126 | ||
115 | switch (i) { | 127 | sprintf(name, "uart%d_ick", i+1); |
116 | case 0: | 128 | uart_ick[i] = clk_get(NULL, name); |
117 | uart1_ick = clk_get(NULL, "uart1_ick"); | 129 | if (IS_ERR(uart_ick[i])) { |
118 | if (IS_ERR(uart1_ick)) | 130 | printk(KERN_ERR "Could not get uart%d_ick\n", i+1); |
119 | printk("Could not get uart1_ick\n"); | 131 | uart_ick[i] = NULL; |
120 | else { | 132 | } else |
121 | clk_enable(uart1_ick); | 133 | clk_enable(uart_ick[i]); |
122 | } | 134 | |
123 | 135 | sprintf(name, "uart%d_fck", i+1); | |
124 | uart1_fck = clk_get(NULL, "uart1_fck"); | 136 | uart_fck[i] = clk_get(NULL, name); |
125 | if (IS_ERR(uart1_fck)) | 137 | if (IS_ERR(uart_fck[i])) { |
126 | printk("Could not get uart1_fck\n"); | 138 | printk(KERN_ERR "Could not get uart%d_fck\n", i+1); |
127 | else { | 139 | uart_fck[i] = NULL; |
128 | clk_enable(uart1_fck); | 140 | } else |
129 | } | 141 | clk_enable(uart_fck[i]); |
130 | break; | ||
131 | case 1: | ||
132 | uart2_ick = clk_get(NULL, "uart2_ick"); | ||
133 | if (IS_ERR(uart2_ick)) | ||
134 | printk("Could not get uart2_ick\n"); | ||
135 | else { | ||
136 | clk_enable(uart2_ick); | ||
137 | } | ||
138 | |||
139 | uart2_fck = clk_get(NULL, "uart2_fck"); | ||
140 | if (IS_ERR(uart2_fck)) | ||
141 | printk("Could not get uart2_fck\n"); | ||
142 | else { | ||
143 | clk_enable(uart2_fck); | ||
144 | } | ||
145 | break; | ||
146 | case 2: | ||
147 | uart3_ick = clk_get(NULL, "uart3_ick"); | ||
148 | if (IS_ERR(uart3_ick)) | ||
149 | printk("Could not get uart3_ick\n"); | ||
150 | else { | ||
151 | clk_enable(uart3_ick); | ||
152 | } | ||
153 | |||
154 | uart3_fck = clk_get(NULL, "uart3_fck"); | ||
155 | if (IS_ERR(uart3_fck)) | ||
156 | printk("Could not get uart3_fck\n"); | ||
157 | else { | ||
158 | clk_enable(uart3_fck); | ||
159 | } | ||
160 | break; | ||
161 | } | ||
162 | 142 | ||
163 | omap_serial_reset(p); | 143 | omap_serial_reset(p); |
164 | } | 144 | } |