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authorPaul Walmsley <paul@pwsan.com>2009-01-28 14:27:37 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 12:50:39 -0500
commitf2ab99778a1a04ddbae38f4de4ef40f2edb92080 (patch)
treecb2e52c92d22393c5d3784013f4cd9f8897c2bd4 /arch/arm/mach-omap2/sdrc2xxx.c
parent96609ef4009515f0667a52b7776c21418df19bd8 (diff)
[ARM] OMAP2 SDRC: separate common OMAP2/3 code from OMAP2xxx code
Separate SDRC code common to OMAP2/3 from mach-omap2/sdrc2xxx.c to mach-omap2/sdrc.c. Rename the OMAP2xxx-specific functions to use an 'omap2xxx' prefix rather than an 'omap2' prefix, and use "sdrc" in the function names rather than "memory." Mark several functions as static that should not be used outside the sdrc2xxx.c file. linux-omap source commit is bf1612b9d8d29379558500cd5de9ae0367c41fc4. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/sdrc2xxx.c')
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c67
1 files changed, 16 insertions, 51 deletions
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 3e38aa4ea458..3a47aba29031 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -3,11 +3,12 @@
3 * 3 *
4 * SDRAM timing related functions for OMAP2xxx 4 * SDRAM timing related functions for OMAP2xxx
5 * 5 *
6 * Copyright (C) 2005 Texas Instruments Inc. 6 * Copyright (C) 2005, 2008 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com> 7 * Copyright (C) 2005, 2008 Nokia Corporation
8 * 8 *
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com> 9 * Tony Lindgren <tony@atomide.com>
10 * Paul Walmsley
11 * Richard Woodruff <r-woodruff2@ti.com>
11 * 12 *
12 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
@@ -39,23 +40,20 @@
39#define M_LOCK 1 40#define M_LOCK 1
40 41
41 42
42void __iomem *omap2_sdrc_base;
43void __iomem *omap2_sms_base;
44
45static struct memory_timings mem_timings; 43static struct memory_timings mem_timings;
46static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; 44static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
47 45
48u32 omap2_memory_get_slow_dll_ctrl(void) 46static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
49{ 47{
50 return mem_timings.slow_dll_ctrl; 48 return mem_timings.slow_dll_ctrl;
51} 49}
52 50
53u32 omap2_memory_get_fast_dll_ctrl(void) 51static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
54{ 52{
55 return mem_timings.fast_dll_ctrl; 53 return mem_timings.fast_dll_ctrl;
56} 54}
57 55
58u32 omap2_memory_get_type(void) 56static u32 omap2xxx_sdrc_get_type(void)
59{ 57{
60 return mem_timings.m_type; 58 return mem_timings.m_type;
61} 59}
@@ -64,7 +62,7 @@ u32 omap2_memory_get_type(void)
64 * Check the DLL lock state, and return tue if running in unlock mode. 62 * Check the DLL lock state, and return tue if running in unlock mode.
65 * This is needed to compensate for the shifted DLL value in unlock mode. 63 * This is needed to compensate for the shifted DLL value in unlock mode.
66 */ 64 */
67u32 omap2_dll_force_needed(void) 65u32 omap2xxx_sdrc_dll_is_unlocked(void)
68{ 66{
69 /* dlla and dllb are a set */ 67 /* dlla and dllb are a set */
70 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); 68 u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
@@ -79,8 +77,10 @@ u32 omap2_dll_force_needed(void)
79 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. 77 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
80 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or 78 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
81 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) 79 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
80 *
81 * Used by the clock framework during CORE DPLL changes
82 */ 82 */
83u32 omap2_reprogram_sdrc(u32 level, u32 force) 83u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
84{ 84{
85 u32 dll_ctrl, m_type; 85 u32 dll_ctrl, m_type;
86 u32 prev = curr_perf_level; 86 u32 prev = curr_perf_level;
@@ -90,13 +90,13 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
90 return prev; 90 return prev;
91 91
92 if (level == CORE_CLK_SRC_DPLL) 92 if (level == CORE_CLK_SRC_DPLL)
93 dll_ctrl = omap2_memory_get_slow_dll_ctrl(); 93 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
94 else if (level == CORE_CLK_SRC_DPLL_X2) 94 else if (level == CORE_CLK_SRC_DPLL_X2)
95 dll_ctrl = omap2_memory_get_fast_dll_ctrl(); 95 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
96 else 96 else
97 return prev; 97 return prev;
98 98
99 m_type = omap2_memory_get_type(); 99 m_type = omap2xxx_sdrc_get_type();
100 100
101 local_irq_save(flags); 101 local_irq_save(flags);
102 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); 102 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
@@ -107,18 +107,8 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force)
107 return prev; 107 return prev;
108} 108}
109 109
110#if !defined(CONFIG_ARCH_OMAP2) 110/* Used by the clock framework during CORE DPLL changes */
111void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 111void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
112 u32 base_cs, u32 force_unlock)
113{
114}
115void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
116 u32 mem_type)
117{
118}
119#endif
120
121void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
122{ 112{
123 unsigned long dll_cnt; 113 unsigned long dll_cnt;
124 u32 fast_dll = 0; 114 u32 fast_dll = 0;
@@ -171,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
171 /* 90 degree phase for anything below 133Mhz + disable DLL filter */ 161 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
172 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 162 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
173} 163}
174
175void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
176{
177 omap2_sdrc_base = omap2_globals->sdrc;
178 omap2_sms_base = omap2_globals->sms;
179}
180
181/* turn on smart idle modes for SDRAM scheduler and controller */
182void __init omap2_init_memory(void)
183{
184 u32 l;
185
186 if (!cpu_is_omap2420())
187 return;
188
189 l = sms_read_reg(SMS_SYSCONFIG);
190 l &= ~(0x3 << 3);
191 l |= (0x2 << 3);
192 sms_write_reg(l, SMS_SYSCONFIG);
193
194 l = sdrc_read_reg(SDRC_SYSCONFIG);
195 l &= ~(0x3 << 3);
196 l |= (0x2 << 3);
197 sdrc_write_reg(l, SDRC_SYSCONFIG);
198}