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authorPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:15 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:05:15 -0500
commite4156ee52fe617c2c2d80b5db993ff4bf07d7c3c (patch)
tree5a2dca04df22b5eac3d5f1af4e39246ae32c5daf /arch/arm/mach-omap2/prm44xx.h
parentb170fbe1f9f1aa38773b1bcf064ab65951ce739d (diff)
OMAP4: CM instances: add clockdomain register offsets
In OMAP4 CM instances, some registers (CM_CLKSTCTRL, CM_STATICDEP, CM_DYNAMICDEP, and the module-specific registers underneath) are organized by clockdomain. Add the clockdomain offset macros to the appropriate PRCM module header files. This data was almost completely autogenerated from the TI hardware database; the autogeneration scripts have been updated. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: BenoƮt Cousson <b-cousson@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm44xx.h')
-rw-r--r--arch/arm/mach-omap2/prm44xx.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 95542aec6c90..67a0d3feb3f6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -56,6 +56,21 @@
56#define OMAP4430_PRM_DEVICE_INST 0x1b00 56#define OMAP4430_PRM_DEVICE_INST 0x1b00
57#define OMAP4430_PRM_INSTR_INST 0x1f00 57#define OMAP4430_PRM_INSTR_INST 0x1f00
58 58
59/* PRM clockdomain register offsets (from instance start) */
60#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
61#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
62#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
63#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
64#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
65#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
66#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
67#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
68#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
69#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
70#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
71#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
72#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
73#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
59 74
60/* OMAP4 specific register offsets */ 75/* OMAP4 specific register offsets */
61#define OMAP4_RM_RSTCTRL 0x0000 76#define OMAP4_RM_RSTCTRL 0x0000