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authorRajendra Nayak <rnayak@ti.com>2010-09-27 16:02:56 -0400
committerPaul Walmsley <paul@pwsan.com>2010-09-27 16:02:56 -0400
commitfdd4f409981e5581e03d4259f2b4923b3158f2cf (patch)
tree2aabfe525e1affe25b43f032ccc6c7fcde0d44ab /arch/arm/mach-omap2/prm44xx.h
parent568997cf375f3e3db28d6962cde66958b57dd6ac (diff)
OMAP4: PM: Define additional registers for ES2
4430 ES2 has a few new registers added and a few modified from ES1. This patch adds all the register changes in PRM and CM for OMAP4430 ES2. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: BenoƮt Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm44xx.h')
-rw-r--r--arch/arm/mach-omap2/prm44xx.h14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index fe8ef26431e5..59839dbabd84 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -44,14 +44,12 @@
44#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) 44#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
45#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 45#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
46#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) 46#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
47#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 47#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
48#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) 48#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
49 49
50/* PRM.CKGEN_PRM register offsets */ 50/* PRM.CKGEN_PRM register offsets */
51#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 51#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
52#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) 52#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
53#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004
54#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
55#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 53#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
56#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) 54#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
57#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 55#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
@@ -686,8 +684,8 @@
686#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) 684#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
687#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 685#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
688#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) 686#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
689#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 687#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
690#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) 688#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
691#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 689#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
692#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) 690#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
693#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 691#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
@@ -698,6 +696,8 @@
698#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) 696#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
699#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 697#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
700#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) 698#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
699#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
700#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
701 701
702/* 702/*
703 * PRCM_MPU 703 * PRCM_MPU
@@ -715,6 +715,8 @@
715/* PRCM_MPU.DEVICE_PRM register offsets */ 715/* PRCM_MPU.DEVICE_PRM register offsets */
716#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 716#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
717#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) 717#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
718#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
719#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
718 720
719/* PRCM_MPU.CPU0 register offsets */ 721/* PRCM_MPU.CPU0 register offsets */
720#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 722#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000