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authorKevin Hilman <khilman@ti.com>2011-03-28 13:52:04 -0400
committerKevin Hilman <khilman@ti.com>2011-09-15 15:02:04 -0400
commit58aaa599a97308c0f4a68ef07039157807fa8324 (patch)
tree584afba63279e12711f80989767a3287d6a7dd09 /arch/arm/mach-omap2/prm44xx.c
parente74e44054f8297d60fbd2ed1d412d84055afee8c (diff)
OMAP2+: add PRM VP functions for checking/clearing VP TX done status
Add SoC specific PRM VP helper functions for checking and clearing the VP transaction done status. Longer term, these events should be handled by the forthcoming PRCM interrupt handler. Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm44xx.c')
-rw-r--r--arch/arm/mach-omap2/prm44xx.c49
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 00165558fc4d..390e32c53b0e 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -21,6 +21,7 @@
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22#include <plat/prcm.h> 22#include <plat/prcm.h>
23 23
24#include "vp.h"
24#include "prm44xx.h" 25#include "prm44xx.h"
25#include "prm-regbits-44xx.h" 26#include "prm-regbits-44xx.h"
26 27
@@ -50,3 +51,51 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
50 51
51 return v; 52 return v;
52} 53}
54
55/* PRM VP */
56
57/*
58 * struct omap4_vp - OMAP4 VP register access description.
59 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
60 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
61 */
62struct omap4_vp {
63 u32 irqstatus_mpu;
64 u32 tranxdone_status;
65};
66
67static struct omap4_vp omap4_vp[] = {
68 [OMAP4_VP_VDD_MPU_ID] = {
69 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
70 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
71 },
72 [OMAP4_VP_VDD_IVA_ID] = {
73 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
74 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
75 },
76 [OMAP4_VP_VDD_CORE_ID] = {
77 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
78 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
79 },
80};
81
82u32 omap4_prm_vp_check_txdone(u8 vp_id)
83{
84 struct omap4_vp *vp = &omap4_vp[vp_id];
85 u32 irqstatus;
86
87 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
88 OMAP4430_PRM_OCP_SOCKET_INST,
89 vp->irqstatus_mpu);
90 return irqstatus & vp->tranxdone_status;
91}
92
93void omap4_prm_vp_clear_txdone(u8 vp_id)
94{
95 struct omap4_vp *vp = &omap4_vp[vp_id];
96
97 omap4_prminst_write_inst_reg(vp->tranxdone_status,
98 OMAP4430_PRM_PARTITION,
99 OMAP4430_PRM_OCP_SOCKET_INST,
100 vp->irqstatus_mpu);
101};