diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-12-28 04:10:44 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2013-01-02 14:07:16 -0500 |
commit | 7e7fff8254e318cede06a1a8c55b0d86dd4d8c5b (patch) | |
tree | 38ad0446026932ed55ae1af167dae17c0a417f3a /arch/arm/mach-omap2/prm3xxx.c | |
parent | cfef4b2723d525a6588c4c55b42f9b98be27937f (diff) |
ARM: OMAP2/3: PRM: fix bogus OMAP2xxx powerstate return values
On OMAP2xxx chips, the register bitfields for the
PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED are
different than those used on OMAP3/4. The order is reversed. So, for
example, on OMAP2xxx, 0x0 indicates 'ON'; but on OMAP3/4, 0x0
indicates 'OFF'. Similarly, on OMAP2xxx, 0x3 indicates 'OFF', but on
OMAP3/4, 0x3 indicates 'ON'.
To fix this, we treat the OMAP3/4 values as the powerdomain API
values, and create new low-level powerdomain functions for the
OMAP2xxx chips which translate between the OMAP2xxx values and the
OMAP3/4 values.
Without this patch, the conversion of the OMAP2xxx PM code to the
functional powerstate code results in a non-booting kernel.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/prm3xxx.c')
-rw-r--r-- | arch/arm/mach-omap2/prm3xxx.c | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index db198d058584..4d43474d7455 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c | |||
@@ -278,6 +278,28 @@ static u32 omap3xxx_prm_read_reset_sources(void) | |||
278 | 278 | ||
279 | /* Powerdomain low-level functions */ | 279 | /* Powerdomain low-level functions */ |
280 | 280 | ||
281 | static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
282 | { | ||
283 | omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | ||
284 | (pwrst << OMAP_POWERSTATE_SHIFT), | ||
285 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | ||
286 | return 0; | ||
287 | } | ||
288 | |||
289 | static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
290 | { | ||
291 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
292 | OMAP2_PM_PWSTCTRL, | ||
293 | OMAP_POWERSTATE_MASK); | ||
294 | } | ||
295 | |||
296 | static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
297 | { | ||
298 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
299 | OMAP2_PM_PWSTST, | ||
300 | OMAP_POWERSTATEST_MASK); | ||
301 | } | ||
302 | |||
281 | /* Applicable only for OMAP3. Not supported on OMAP2 */ | 303 | /* Applicable only for OMAP3. Not supported on OMAP2 */ |
282 | static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | 304 | static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) |
283 | { | 305 | { |
@@ -356,9 +378,9 @@ static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | |||
356 | } | 378 | } |
357 | 379 | ||
358 | struct pwrdm_ops omap3_pwrdm_operations = { | 380 | struct pwrdm_ops omap3_pwrdm_operations = { |
359 | .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, | 381 | .pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst, |
360 | .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, | 382 | .pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst, |
361 | .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, | 383 | .pwrdm_read_pwrst = omap3_pwrdm_read_pwrst, |
362 | .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, | 384 | .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, |
363 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, | 385 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, |
364 | .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, | 386 | .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, |