diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-01-28 14:18:22 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-08 12:50:37 -0500 |
| commit | da0747d4faf55320f0f6cbcd8525e2a8e4619925 (patch) | |
| tree | b3fce6c33df8f555d9adbe00d679e48f9f4a81c0 /arch/arm/mach-omap2/prcm-common.h | |
| parent | 027d8ded5d1c142eb120caff7a395c0637467ac9 (diff) | |
[ARM] OMAP2 PRCM: clean up CM_IDLEST bits
This patch fixes a few OMAP2xxx CM_IDLEST bits that were incorrectly
marked as being OMAP2xxx-wide, when they were actually 2420-specific.
Also, originally when the PRCM register macros were defined, bit shift
macros used a "_SHIFT" suffix, and mask macros used none. This became
a source of bugs and confusion, as the mask macros were mistakenly
used for shift values. Gradually, the mask macros have been updated,
piece by piece, to add a "_MASK" suffix on the end to clarify. This
patch applies this change to the CM_IDLEST_* register bits.
The patch also adds a few bits that were missing, mostly from the 3430ES1
to ES2 revisions.
linux-omap source commits are d18eff5b5fa15e170794397a6a94486d1f774f77,
e1f1a5cc24615fb790cc763c96d1c5cfe6296f5b, and part of
9fe6b6cf8d9e0cbb429fd64553a4b3160a9e99e1
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/prcm-common.h')
| -rw-r--r-- | arch/arm/mach-omap2/prcm-common.h | 198 |
1 files changed, 133 insertions, 65 deletions
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 4a32822ff3fc..812d50ee495d 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -113,33 +113,58 @@ | |||
| 113 | #define OMAP2430_EN_USBHS (1 << 6) | 113 | #define OMAP2430_EN_USBHS (1 << 6) |
| 114 | 114 | ||
| 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ |
| 116 | #define OMAP2420_ST_MMC (1 << 26) | 116 | #define OMAP2420_ST_MMC_SHIFT 26 |
| 117 | #define OMAP24XX_ST_UART2 (1 << 22) | 117 | #define OMAP2420_ST_MMC_MASK (1 << 26) |
| 118 | #define OMAP24XX_ST_UART1 (1 << 21) | 118 | #define OMAP24XX_ST_UART2_SHIFT 22 |
| 119 | #define OMAP24XX_ST_MCSPI2 (1 << 18) | 119 | #define OMAP24XX_ST_UART2_MASK (1 << 22) |
| 120 | #define OMAP24XX_ST_MCSPI1 (1 << 17) | 120 | #define OMAP24XX_ST_UART1_SHIFT 21 |
| 121 | #define OMAP24XX_ST_GPT12 (1 << 14) | 121 | #define OMAP24XX_ST_UART1_MASK (1 << 21) |
| 122 | #define OMAP24XX_ST_GPT11 (1 << 13) | 122 | #define OMAP24XX_ST_MCSPI2_SHIFT 18 |
| 123 | #define OMAP24XX_ST_GPT10 (1 << 12) | 123 | #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) |
| 124 | #define OMAP24XX_ST_GPT9 (1 << 11) | 124 | #define OMAP24XX_ST_MCSPI1_SHIFT 17 |
| 125 | #define OMAP24XX_ST_GPT8 (1 << 10) | 125 | #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) |
| 126 | #define OMAP24XX_ST_GPT7 (1 << 9) | 126 | #define OMAP24XX_ST_GPT12_SHIFT 14 |
| 127 | #define OMAP24XX_ST_GPT6 (1 << 8) | 127 | #define OMAP24XX_ST_GPT12_MASK (1 << 14) |
| 128 | #define OMAP24XX_ST_GPT5 (1 << 7) | 128 | #define OMAP24XX_ST_GPT11_SHIFT 13 |
| 129 | #define OMAP24XX_ST_GPT4 (1 << 6) | 129 | #define OMAP24XX_ST_GPT11_MASK (1 << 13) |
| 130 | #define OMAP24XX_ST_GPT3 (1 << 5) | 130 | #define OMAP24XX_ST_GPT10_SHIFT 12 |
| 131 | #define OMAP24XX_ST_GPT2 (1 << 4) | 131 | #define OMAP24XX_ST_GPT10_MASK (1 << 12) |
| 132 | #define OMAP2420_ST_VLYNQ (1 << 3) | 132 | #define OMAP24XX_ST_GPT9_SHIFT 11 |
| 133 | #define OMAP24XX_ST_GPT9_MASK (1 << 11) | ||
| 134 | #define OMAP24XX_ST_GPT8_SHIFT 10 | ||
| 135 | #define OMAP24XX_ST_GPT8_MASK (1 << 10) | ||
| 136 | #define OMAP24XX_ST_GPT7_SHIFT 9 | ||
| 137 | #define OMAP24XX_ST_GPT7_MASK (1 << 9) | ||
| 138 | #define OMAP24XX_ST_GPT6_SHIFT 8 | ||
| 139 | #define OMAP24XX_ST_GPT6_MASK (1 << 8) | ||
| 140 | #define OMAP24XX_ST_GPT5_SHIFT 7 | ||
| 141 | #define OMAP24XX_ST_GPT5_MASK (1 << 7) | ||
| 142 | #define OMAP24XX_ST_GPT4_SHIFT 6 | ||
| 143 | #define OMAP24XX_ST_GPT4_MASK (1 << 6) | ||
| 144 | #define OMAP24XX_ST_GPT3_SHIFT 5 | ||
| 145 | #define OMAP24XX_ST_GPT3_MASK (1 << 5) | ||
| 146 | #define OMAP24XX_ST_GPT2_SHIFT 4 | ||
| 147 | #define OMAP24XX_ST_GPT2_MASK (1 << 4) | ||
| 148 | #define OMAP2420_ST_VLYNQ_SHIFT 3 | ||
| 149 | #define OMAP2420_ST_VLYNQ_MASK (1 << 3) | ||
| 133 | 150 | ||
| 134 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | 151 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ |
| 135 | #define OMAP2430_ST_MDM_INTC (1 << 11) | 152 | #define OMAP2430_ST_MDM_INTC_SHIFT 11 |
| 136 | #define OMAP2430_ST_GPIO5 (1 << 10) | 153 | #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) |
| 137 | #define OMAP2430_ST_MCSPI3 (1 << 9) | 154 | #define OMAP2430_ST_GPIO5_SHIFT 10 |
| 138 | #define OMAP2430_ST_MMCHS2 (1 << 8) | 155 | #define OMAP2430_ST_GPIO5_MASK (1 << 10) |
| 139 | #define OMAP2430_ST_MMCHS1 (1 << 7) | 156 | #define OMAP2430_ST_MCSPI3_SHIFT 9 |
| 140 | #define OMAP2430_ST_USBHS (1 << 6) | 157 | #define OMAP2430_ST_MCSPI3_MASK (1 << 9) |
| 141 | #define OMAP24XX_ST_UART3 (1 << 2) | 158 | #define OMAP2430_ST_MMCHS2_SHIFT 8 |
| 142 | #define OMAP24XX_ST_USB (1 << 0) | 159 | #define OMAP2430_ST_MMCHS2_MASK (1 << 8) |
| 160 | #define OMAP2430_ST_MMCHS1_SHIFT 7 | ||
| 161 | #define OMAP2430_ST_MMCHS1_MASK (1 << 7) | ||
| 162 | #define OMAP2430_ST_USBHS_SHIFT 6 | ||
| 163 | #define OMAP2430_ST_USBHS_MASK (1 << 6) | ||
| 164 | #define OMAP24XX_ST_UART3_SHIFT 2 | ||
| 165 | #define OMAP24XX_ST_UART3_MASK (1 << 2) | ||
| 166 | #define OMAP24XX_ST_USB_SHIFT 0 | ||
| 167 | #define OMAP24XX_ST_USB_MASK (1 << 0) | ||
| 143 | 168 | ||
| 144 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 169 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 145 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | 170 | #define OMAP24XX_EN_GPIOS_SHIFT 2 |
| @@ -148,11 +173,13 @@ | |||
| 148 | #define OMAP24XX_EN_GPT1 (1 << 0) | 173 | #define OMAP24XX_EN_GPT1 (1 << 0) |
| 149 | 174 | ||
| 150 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | 175 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ |
| 151 | #define OMAP24XX_ST_GPIOS (1 << 2) | 176 | #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) |
| 152 | #define OMAP24XX_ST_GPT1 (1 << 0) | 177 | #define OMAP24XX_ST_GPIOS_MASK 2 |
| 178 | #define OMAP24XX_ST_GPT1_SHIFT (1 << 0) | ||
| 179 | #define OMAP24XX_ST_GPT1_MASK 0 | ||
| 153 | 180 | ||
| 154 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | 181 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ |
| 155 | #define OMAP2430_ST_MDM (1 << 0) | 182 | #define OMAP2430_ST_MDM_SHIFT (1 << 0) |
| 156 | 183 | ||
| 157 | 184 | ||
| 158 | /* 3430 register bits shared between CM & PRM registers */ | 185 | /* 3430 register bits shared between CM & PRM registers */ |
| @@ -205,24 +232,46 @@ | |||
| 205 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | 232 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 |
| 206 | 233 | ||
| 207 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | 234 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ |
| 208 | #define OMAP3430_ST_MMC2 (1 << 25) | 235 | #define OMAP3430_ST_MMC2_SHIFT 25 |
| 209 | #define OMAP3430_ST_MMC1 (1 << 24) | 236 | #define OMAP3430_ST_MMC2_MASK (1 << 25) |
| 210 | #define OMAP3430_ST_MCSPI4 (1 << 21) | 237 | #define OMAP3430_ST_MMC1_SHIFT 24 |
| 211 | #define OMAP3430_ST_MCSPI3 (1 << 20) | 238 | #define OMAP3430_ST_MMC1_MASK (1 << 24) |
| 212 | #define OMAP3430_ST_MCSPI2 (1 << 19) | 239 | #define OMAP3430_ST_MCSPI4_SHIFT 21 |
| 213 | #define OMAP3430_ST_MCSPI1 (1 << 18) | 240 | #define OMAP3430_ST_MCSPI4_MASK (1 << 21) |
| 214 | #define OMAP3430_ST_I2C3 (1 << 17) | 241 | #define OMAP3430_ST_MCSPI3_SHIFT 20 |
| 215 | #define OMAP3430_ST_I2C2 (1 << 16) | 242 | #define OMAP3430_ST_MCSPI3_MASK (1 << 20) |
| 216 | #define OMAP3430_ST_I2C1 (1 << 15) | 243 | #define OMAP3430_ST_MCSPI2_SHIFT 19 |
| 217 | #define OMAP3430_ST_UART2 (1 << 14) | 244 | #define OMAP3430_ST_MCSPI2_MASK (1 << 19) |
| 218 | #define OMAP3430_ST_UART1 (1 << 13) | 245 | #define OMAP3430_ST_MCSPI1_SHIFT 18 |
| 219 | #define OMAP3430_ST_GPT11 (1 << 12) | 246 | #define OMAP3430_ST_MCSPI1_MASK (1 << 18) |
| 220 | #define OMAP3430_ST_GPT10 (1 << 11) | 247 | #define OMAP3430_ST_I2C3_SHIFT 17 |
| 221 | #define OMAP3430_ST_MCBSP5 (1 << 10) | 248 | #define OMAP3430_ST_I2C3_MASK (1 << 17) |
| 222 | #define OMAP3430_ST_MCBSP1 (1 << 9) | 249 | #define OMAP3430_ST_I2C2_SHIFT 16 |
| 223 | #define OMAP3430_ST_FSHOSTUSB (1 << 5) | 250 | #define OMAP3430_ST_I2C2_MASK (1 << 16) |
| 224 | #define OMAP3430_ST_HSOTGUSB (1 << 4) | 251 | #define OMAP3430_ST_I2C1_SHIFT 15 |
| 225 | #define OMAP3430_ST_D2D (1 << 3) | 252 | #define OMAP3430_ST_I2C1_MASK (1 << 15) |
| 253 | #define OMAP3430_ST_UART2_SHIFT 14 | ||
| 254 | #define OMAP3430_ST_UART2_MASK (1 << 14) | ||
| 255 | #define OMAP3430_ST_UART1_SHIFT 13 | ||
| 256 | #define OMAP3430_ST_UART1_MASK (1 << 13) | ||
| 257 | #define OMAP3430_ST_GPT11_SHIFT 12 | ||
| 258 | #define OMAP3430_ST_GPT11_MASK (1 << 12) | ||
| 259 | #define OMAP3430_ST_GPT10_SHIFT 11 | ||
| 260 | #define OMAP3430_ST_GPT10_MASK (1 << 11) | ||
| 261 | #define OMAP3430_ST_MCBSP5_SHIFT 10 | ||
| 262 | #define OMAP3430_ST_MCBSP5_MASK (1 << 10) | ||
| 263 | #define OMAP3430_ST_MCBSP1_SHIFT 9 | ||
| 264 | #define OMAP3430_ST_MCBSP1_MASK (1 << 9) | ||
| 265 | #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 | ||
| 266 | #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) | ||
| 267 | #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 | ||
| 268 | #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) | ||
| 269 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 | ||
| 270 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) | ||
| 271 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 | ||
| 272 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) | ||
| 273 | #define OMAP3430_ST_D2D_SHIFT 3 | ||
| 274 | #define OMAP3430_ST_D2D_MASK (1 << 3) | ||
| 226 | 275 | ||
| 227 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 276 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 228 | #define OMAP3430_EN_GPIO1 (1 << 3) | 277 | #define OMAP3430_EN_GPIO1 (1 << 3) |
| @@ -241,11 +290,16 @@ | |||
| 241 | #define OMAP3430_EN_GPT12_SHIFT 1 | 290 | #define OMAP3430_EN_GPT12_SHIFT 1 |
| 242 | 291 | ||
| 243 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | 292 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ |
| 244 | #define OMAP3430_ST_SR2 (1 << 7) | 293 | #define OMAP3430_ST_SR2_SHIFT 7 |
| 245 | #define OMAP3430_ST_SR1 (1 << 6) | 294 | #define OMAP3430_ST_SR2_MASK (1 << 7) |
| 246 | #define OMAP3430_ST_GPIO1 (1 << 3) | 295 | #define OMAP3430_ST_SR1_SHIFT 6 |
| 247 | #define OMAP3430_ST_GPT12 (1 << 1) | 296 | #define OMAP3430_ST_SR1_MASK (1 << 6) |
| 248 | #define OMAP3430_ST_GPT1 (1 << 0) | 297 | #define OMAP3430_ST_GPIO1_SHIFT 3 |
| 298 | #define OMAP3430_ST_GPIO1_MASK (1 << 3) | ||
| 299 | #define OMAP3430_ST_GPT12_SHIFT 1 | ||
| 300 | #define OMAP3430_ST_GPT12_MASK (1 << 1) | ||
| 301 | #define OMAP3430_ST_GPT1_SHIFT 0 | ||
| 302 | #define OMAP3430_ST_GPT1_MASK (1 << 0) | ||
| 249 | 303 | ||
| 250 | /* | 304 | /* |
| 251 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | 305 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, |
| @@ -296,20 +350,34 @@ | |||
| 296 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | 350 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
| 297 | 351 | ||
| 298 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | 352 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ |
| 299 | #define OMAP3430_ST_GPIO6 (1 << 17) | 353 | #define OMAP3430_ST_GPIO6_SHIFT 17 |
| 300 | #define OMAP3430_ST_GPIO5 (1 << 16) | 354 | #define OMAP3430_ST_GPIO6_MASK (1 << 17) |
| 301 | #define OMAP3430_ST_GPIO4 (1 << 15) | 355 | #define OMAP3430_ST_GPIO5_SHIFT 16 |
| 302 | #define OMAP3430_ST_GPIO3 (1 << 14) | 356 | #define OMAP3430_ST_GPIO5_MASK (1 << 16) |
| 303 | #define OMAP3430_ST_GPIO2 (1 << 13) | 357 | #define OMAP3430_ST_GPIO4_SHIFT 15 |
| 304 | #define OMAP3430_ST_UART3 (1 << 11) | 358 | #define OMAP3430_ST_GPIO4_MASK (1 << 15) |
| 305 | #define OMAP3430_ST_GPT9 (1 << 10) | 359 | #define OMAP3430_ST_GPIO3_SHIFT 14 |
| 306 | #define OMAP3430_ST_GPT8 (1 << 9) | 360 | #define OMAP3430_ST_GPIO3_MASK (1 << 14) |
| 307 | #define OMAP3430_ST_GPT7 (1 << 8) | 361 | #define OMAP3430_ST_GPIO2_SHIFT 13 |
| 308 | #define OMAP3430_ST_GPT6 (1 << 7) | 362 | #define OMAP3430_ST_GPIO2_MASK (1 << 13) |
| 309 | #define OMAP3430_ST_GPT5 (1 << 6) | 363 | #define OMAP3430_ST_UART3_SHIFT 11 |
| 310 | #define OMAP3430_ST_GPT4 (1 << 5) | 364 | #define OMAP3430_ST_UART3_MASK (1 << 11) |
| 311 | #define OMAP3430_ST_GPT3 (1 << 4) | 365 | #define OMAP3430_ST_GPT9_SHIFT 10 |
| 312 | #define OMAP3430_ST_GPT2 (1 << 3) | 366 | #define OMAP3430_ST_GPT9_MASK (1 << 10) |
| 367 | #define OMAP3430_ST_GPT8_SHIFT 9 | ||
| 368 | #define OMAP3430_ST_GPT8_MASK (1 << 9) | ||
| 369 | #define OMAP3430_ST_GPT7_SHIFT 8 | ||
| 370 | #define OMAP3430_ST_GPT7_MASK (1 << 8) | ||
| 371 | #define OMAP3430_ST_GPT6_SHIFT 7 | ||
| 372 | #define OMAP3430_ST_GPT6_MASK (1 << 7) | ||
| 373 | #define OMAP3430_ST_GPT5_SHIFT 6 | ||
| 374 | #define OMAP3430_ST_GPT5_MASK (1 << 6) | ||
| 375 | #define OMAP3430_ST_GPT4_SHIFT 5 | ||
| 376 | #define OMAP3430_ST_GPT4_MASK (1 << 5) | ||
| 377 | #define OMAP3430_ST_GPT3_SHIFT 4 | ||
| 378 | #define OMAP3430_ST_GPT3_MASK (1 << 4) | ||
| 379 | #define OMAP3430_ST_GPT2_SHIFT 3 | ||
| 380 | #define OMAP3430_ST_GPT2_MASK (1 << 3) | ||
| 313 | 381 | ||
| 314 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | 382 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ |
| 315 | #define OMAP3430_EN_CORE_SHIFT 0 | 383 | #define OMAP3430_EN_CORE_SHIFT 0 |