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authorPaul Walmsley <paul@pwsan.com>2011-03-07 21:28:15 -0500
committerPaul Walmsley <paul@pwsan.com>2011-03-07 21:28:15 -0500
commit4cb49fec12e219ec174e04157f71c00f63eb4ce4 (patch)
tree991a0cb1e304d6c128f3af401786865347569990 /arch/arm/mach-omap2/powerdomains44xx_data.c
parentcad7a34b3afcd02e8e6bef5007e4b12f6cc8ec24 (diff)
OMAP2+: powerdomain: fix bank power state bitfields
The bank power state bitfields in the powerdomain data are encoded incorrectly. These fields are intended to be bitfields, representing a set of power states that the memory banks support. However, when only one power state was supported by a given bank, the field was incorrectly set to the bit shift -- not the mask. While here, update some file copyrights. The OMAP4 autogeneration scripts have been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: BenoƮt Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomains44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c84
1 files changed, 42 insertions, 42 deletions
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 226e01aac9eb..c4222c7036a5 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -2,7 +2,7 @@
2 * OMAP4 Power domains framework 2 * OMAP4 Power domains framework
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
@@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
40 .pwrsts_logic_ret = PWRSTS_OFF_RET, 40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5, 41 .banks = 5,
42 .pwrsts_mem_ret = { 42 .pwrsts_mem_ret = {
43 [0] = PWRDM_POWER_OFF, /* core_nret_bank */ 43 [0] = PWRSTS_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 44 [1] = PWRSTS_OFF_RET, /* core_ocmram */
45 [2] = PWRDM_POWER_RET, /* core_other_bank */ 45 [2] = PWRSTS_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */ 46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */ 47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 }, 48 },
49 .pwrsts_mem_on = { 49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, /* core_nret_bank */ 50 [0] = PWRSTS_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */ 51 [1] = PWRSTS_OFF_RET, /* core_ocmram */
52 [2] = PWRDM_POWER_ON, /* core_other_bank */ 52 [2] = PWRSTS_ON, /* core_other_bank */
53 [3] = PWRDM_POWER_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRDM_POWER_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
55 }, 55 },
56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 57};
@@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
65 .pwrsts = PWRSTS_OFF_ON, 65 .pwrsts = PWRSTS_OFF_ON,
66 .banks = 1, 66 .banks = 1,
67 .pwrsts_mem_ret = { 67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_OFF, /* gfx_mem */ 68 [0] = PWRSTS_OFF, /* gfx_mem */
69 }, 69 },
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* gfx_mem */ 71 [0] = PWRSTS_ON, /* gfx_mem */
72 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74}; 74};
@@ -83,12 +83,12 @@ static struct powerdomain abe_44xx_pwrdm = {
83 .pwrsts_logic_ret = PWRSTS_OFF, 83 .pwrsts_logic_ret = PWRSTS_OFF,
84 .banks = 2, 84 .banks = 2,
85 .pwrsts_mem_ret = { 85 .pwrsts_mem_ret = {
86 [0] = PWRDM_POWER_RET, /* aessmem */ 86 [0] = PWRSTS_RET, /* aessmem */
87 [1] = PWRDM_POWER_OFF, /* periphmem */ 87 [1] = PWRSTS_OFF, /* periphmem */
88 }, 88 },
89 .pwrsts_mem_on = { 89 .pwrsts_mem_on = {
90 [0] = PWRDM_POWER_ON, /* aessmem */ 90 [0] = PWRSTS_ON, /* aessmem */
91 [1] = PWRDM_POWER_ON, /* periphmem */ 91 [1] = PWRSTS_ON, /* periphmem */
92 }, 92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94}; 94};
@@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
103 .pwrsts_logic_ret = PWRSTS_OFF, 103 .pwrsts_logic_ret = PWRSTS_OFF,
104 .banks = 1, 104 .banks = 1,
105 .pwrsts_mem_ret = { 105 .pwrsts_mem_ret = {
106 [0] = PWRDM_POWER_OFF, /* dss_mem */ 106 [0] = PWRSTS_OFF, /* dss_mem */
107 }, 107 },
108 .pwrsts_mem_on = { 108 .pwrsts_mem_on = {
109 [0] = PWRDM_POWER_ON, /* dss_mem */ 109 [0] = PWRSTS_ON, /* dss_mem */
110 }, 110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112}; 112};
@@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
121 .pwrsts_logic_ret = PWRSTS_OFF_RET, 121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 3, 122 .banks = 3,
123 .pwrsts_mem_ret = { 123 .pwrsts_mem_ret = {
124 [0] = PWRDM_POWER_RET, /* tesla_edma */ 124 [0] = PWRSTS_RET, /* tesla_edma */
125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */ 125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */
126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */ 126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */
127 }, 127 },
128 .pwrsts_mem_on = { 128 .pwrsts_mem_on = {
129 [0] = PWRDM_POWER_ON, /* tesla_edma */ 129 [0] = PWRSTS_ON, /* tesla_edma */
130 [1] = PWRDM_POWER_ON, /* tesla_l1 */ 130 [1] = PWRSTS_ON, /* tesla_l1 */
131 [2] = PWRDM_POWER_ON, /* tesla_l2 */ 131 [2] = PWRSTS_ON, /* tesla_l2 */
132 }, 132 },
133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
134}; 134};
@@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
142 .pwrsts = PWRSTS_ON, 142 .pwrsts = PWRSTS_ON,
143 .banks = 1, 143 .banks = 1,
144 .pwrsts_mem_ret = { 144 .pwrsts_mem_ret = {
145 [0] = PWRDM_POWER_OFF, /* wkup_bank */ 145 [0] = PWRSTS_OFF, /* wkup_bank */
146 }, 146 },
147 .pwrsts_mem_on = { 147 .pwrsts_mem_on = {
148 [0] = PWRDM_POWER_ON, /* wkup_bank */ 148 [0] = PWRSTS_ON, /* wkup_bank */
149 }, 149 },
150}; 150};
151 151
@@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ 162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
163 }, 163 },
164 .pwrsts_mem_on = { 164 .pwrsts_mem_on = {
165 [0] = PWRDM_POWER_ON, /* cpu0_l1 */ 165 [0] = PWRSTS_ON, /* cpu0_l1 */
166 }, 166 },
167}; 167};
168 168
@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ 179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
180 }, 180 },
181 .pwrsts_mem_on = { 181 .pwrsts_mem_on = {
182 [0] = PWRDM_POWER_ON, /* cpu1_l1 */ 182 [0] = PWRSTS_ON, /* cpu1_l1 */
183 }, 183 },
184}; 184};
185 185
@@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
192 .pwrsts = PWRSTS_OFF_ON, 192 .pwrsts = PWRSTS_OFF_ON,
193 .banks = 1, 193 .banks = 1,
194 .pwrsts_mem_ret = { 194 .pwrsts_mem_ret = {
195 [0] = PWRDM_POWER_OFF, /* emu_bank */ 195 [0] = PWRSTS_OFF, /* emu_bank */
196 }, 196 },
197 .pwrsts_mem_on = { 197 .pwrsts_mem_on = {
198 [0] = PWRDM_POWER_ON, /* emu_bank */ 198 [0] = PWRSTS_ON, /* emu_bank */
199 }, 199 },
200}; 200};
201 201
@@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
211 .pwrsts_mem_ret = { 211 .pwrsts_mem_ret = {
212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */ 212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */ 213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
214 [2] = PWRDM_POWER_RET, /* mpu_ram */ 214 [2] = PWRSTS_RET, /* mpu_ram */
215 }, 215 },
216 .pwrsts_mem_on = { 216 .pwrsts_mem_on = {
217 [0] = PWRDM_POWER_ON, /* mpu_l1 */ 217 [0] = PWRSTS_ON, /* mpu_l1 */
218 [1] = PWRDM_POWER_ON, /* mpu_l2 */ 218 [1] = PWRSTS_ON, /* mpu_l2 */
219 [2] = PWRDM_POWER_ON, /* mpu_ram */ 219 [2] = PWRSTS_ON, /* mpu_ram */
220 }, 220 },
221}; 221};
222 222
@@ -230,16 +230,16 @@ static struct powerdomain ivahd_44xx_pwrdm = {
230 .pwrsts_logic_ret = PWRSTS_OFF, 230 .pwrsts_logic_ret = PWRSTS_OFF,
231 .banks = 4, 231 .banks = 4,
232 .pwrsts_mem_ret = { 232 .pwrsts_mem_ret = {
233 [0] = PWRDM_POWER_OFF, /* hwa_mem */ 233 [0] = PWRSTS_OFF, /* hwa_mem */
234 [1] = PWRSTS_OFF_RET, /* sl2_mem */ 234 [1] = PWRSTS_OFF_RET, /* sl2_mem */
235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */ 235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */ 236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
237 }, 237 },
238 .pwrsts_mem_on = { 238 .pwrsts_mem_on = {
239 [0] = PWRDM_POWER_ON, /* hwa_mem */ 239 [0] = PWRSTS_ON, /* hwa_mem */
240 [1] = PWRDM_POWER_ON, /* sl2_mem */ 240 [1] = PWRSTS_ON, /* sl2_mem */
241 [2] = PWRDM_POWER_ON, /* tcm1_mem */ 241 [2] = PWRSTS_ON, /* tcm1_mem */
242 [3] = PWRDM_POWER_ON, /* tcm2_mem */ 242 [3] = PWRSTS_ON, /* tcm2_mem */
243 }, 243 },
244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 245};
@@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
253 .pwrsts = PWRSTS_OFF_ON, 253 .pwrsts = PWRSTS_OFF_ON,
254 .banks = 1, 254 .banks = 1,
255 .pwrsts_mem_ret = { 255 .pwrsts_mem_ret = {
256 [0] = PWRDM_POWER_OFF, /* cam_mem */ 256 [0] = PWRSTS_OFF, /* cam_mem */
257 }, 257 },
258 .pwrsts_mem_on = { 258 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* cam_mem */ 259 [0] = PWRSTS_ON, /* cam_mem */
260 }, 260 },
261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
262}; 262};
@@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
271 .pwrsts_logic_ret = PWRSTS_OFF_RET, 271 .pwrsts_logic_ret = PWRSTS_OFF_RET,
272 .banks = 1, 272 .banks = 1,
273 .pwrsts_mem_ret = { 273 .pwrsts_mem_ret = {
274 [0] = PWRDM_POWER_OFF, /* l3init_bank1 */ 274 [0] = PWRSTS_OFF, /* l3init_bank1 */
275 }, 275 },
276 .pwrsts_mem_on = { 276 .pwrsts_mem_on = {
277 [0] = PWRDM_POWER_ON, /* l3init_bank1 */ 277 [0] = PWRSTS_ON, /* l3init_bank1 */
278 }, 278 },
279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
280}; 280};
@@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
289 .pwrsts_logic_ret = PWRSTS_OFF_RET, 289 .pwrsts_logic_ret = PWRSTS_OFF_RET,
290 .banks = 2, 290 .banks = 2,
291 .pwrsts_mem_ret = { 291 .pwrsts_mem_ret = {
292 [0] = PWRDM_POWER_OFF, /* nonretained_bank */ 292 [0] = PWRSTS_OFF, /* nonretained_bank */
293 [1] = PWRDM_POWER_RET, /* retained_bank */ 293 [1] = PWRSTS_RET, /* retained_bank */
294 }, 294 },
295 .pwrsts_mem_on = { 295 .pwrsts_mem_on = {
296 [0] = PWRDM_POWER_ON, /* nonretained_bank */ 296 [0] = PWRSTS_ON, /* nonretained_bank */
297 [1] = PWRDM_POWER_ON, /* retained_bank */ 297 [1] = PWRSTS_ON, /* retained_bank */
298 }, 298 },
299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
300}; 300};