diff options
author | Paul Walmsley <paul@pwsan.com> | 2010-01-26 22:12:59 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2010-01-26 22:12:59 -0500 |
commit | 55ed96945b1f3d0f4ad21a27b32ce4bd99d8c268 (patch) | |
tree | 0bec60498742922a9c00f39ff63eb48549d391fc /arch/arm/mach-omap2/powerdomains34xx.h | |
parent | 6b04e0d99d4113ede24e263e3df246a17f490339 (diff) |
OMAP2/3 clkdm/pwrdm: move wkdep/sleepdep handling from pwrdm to clkdm
Move clockdomain wakeup dependency and sleep dependency data
structures from the powerdomain layer to the clockdomain layer, where
they belong. These dependencies were originally placed in the
powerdomain layer due to unclear documentation; however, it is clear
now that these dependencies are between clockdomains. For OMAP2/3,
this is not such a big problem, but for OMAP4 this needs to be fixed.
Thanks to Benoît Cousson <b-cousson@ti.com> for his advice on this
patch.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomains34xx.h')
-rw-r--r-- | arch/arm/mach-omap2/powerdomains34xx.h | 145 |
1 files changed, 1 insertions, 144 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 588f7e07d0ea..28228ef20e86 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * OMAP34XX powerdomain definitions | 2 | * OMAP34XX powerdomain definitions |
3 | * | 3 | * |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2008 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
6 | * | 6 | * |
7 | * Written by Paul Walmsley | 7 | * Written by Paul Walmsley |
8 | * Debugging and integration fixes by Jouni Högander | 8 | * Debugging and integration fixes by Jouni Högander |
@@ -35,127 +35,6 @@ | |||
35 | #ifdef CONFIG_ARCH_OMAP34XX | 35 | #ifdef CONFIG_ARCH_OMAP34XX |
36 | 36 | ||
37 | /* | 37 | /* |
38 | * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP | ||
39 | * (USBHOST is ES2 only) | ||
40 | */ | ||
41 | static struct pwrdm_dep per_usbhost_wkdeps[] = { | ||
42 | { | ||
43 | .pwrdm_name = "core_pwrdm", | ||
44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
45 | }, | ||
46 | { | ||
47 | .pwrdm_name = "iva2_pwrdm", | ||
48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
49 | }, | ||
50 | { | ||
51 | .pwrdm_name = "mpu_pwrdm", | ||
52 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
53 | }, | ||
54 | { | ||
55 | .pwrdm_name = "wkup_pwrdm", | ||
56 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
57 | }, | ||
58 | { NULL }, | ||
59 | }; | ||
60 | |||
61 | /* | ||
62 | * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER | ||
63 | */ | ||
64 | static struct pwrdm_dep mpu_34xx_wkdeps[] = { | ||
65 | { | ||
66 | .pwrdm_name = "core_pwrdm", | ||
67 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
68 | }, | ||
69 | { | ||
70 | .pwrdm_name = "iva2_pwrdm", | ||
71 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
72 | }, | ||
73 | { | ||
74 | .pwrdm_name = "dss_pwrdm", | ||
75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
76 | }, | ||
77 | { | ||
78 | .pwrdm_name = "per_pwrdm", | ||
79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
80 | }, | ||
81 | { NULL }, | ||
82 | }; | ||
83 | |||
84 | /* | ||
85 | * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER | ||
86 | */ | ||
87 | static struct pwrdm_dep iva2_wkdeps[] = { | ||
88 | { | ||
89 | .pwrdm_name = "core_pwrdm", | ||
90 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
91 | }, | ||
92 | { | ||
93 | .pwrdm_name = "mpu_pwrdm", | ||
94 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
95 | }, | ||
96 | { | ||
97 | .pwrdm_name = "wkup_pwrdm", | ||
98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
99 | }, | ||
100 | { | ||
101 | .pwrdm_name = "dss_pwrdm", | ||
102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
103 | }, | ||
104 | { | ||
105 | .pwrdm_name = "per_pwrdm", | ||
106 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
107 | }, | ||
108 | { NULL }, | ||
109 | }; | ||
110 | |||
111 | |||
112 | /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */ | ||
113 | static struct pwrdm_dep cam_dss_wkdeps[] = { | ||
114 | { | ||
115 | .pwrdm_name = "iva2_pwrdm", | ||
116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
117 | }, | ||
118 | { | ||
119 | .pwrdm_name = "mpu_pwrdm", | ||
120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
121 | }, | ||
122 | { | ||
123 | .pwrdm_name = "wkup_pwrdm", | ||
124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
125 | }, | ||
126 | { NULL }, | ||
127 | }; | ||
128 | |||
129 | /* 3430: PM_WKDEP_NEON: MPU */ | ||
130 | static struct pwrdm_dep neon_wkdeps[] = { | ||
131 | { | ||
132 | .pwrdm_name = "mpu_pwrdm", | ||
133 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
134 | }, | ||
135 | { NULL }, | ||
136 | }; | ||
137 | |||
138 | |||
139 | /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */ | ||
140 | |||
141 | /* | ||
142 | * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA | ||
143 | * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA | ||
144 | */ | ||
145 | static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = { | ||
146 | { | ||
147 | .pwrdm_name = "mpu_pwrdm", | ||
148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
149 | }, | ||
150 | { | ||
151 | .pwrdm_name = "iva2_pwrdm", | ||
152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | ||
153 | }, | ||
154 | { NULL }, | ||
155 | }; | ||
156 | |||
157 | |||
158 | /* | ||
159 | * Powerdomains | 38 | * Powerdomains |
160 | */ | 39 | */ |
161 | 40 | ||
@@ -163,8 +42,6 @@ static struct powerdomain iva2_pwrdm = { | |||
163 | .name = "iva2_pwrdm", | 42 | .name = "iva2_pwrdm", |
164 | .prcm_offs = OMAP3430_IVA2_MOD, | 43 | .prcm_offs = OMAP3430_IVA2_MOD, |
165 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 44 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
166 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | ||
167 | .wkdep_srcs = iva2_wkdeps, | ||
168 | .pwrsts = PWRSTS_OFF_RET_ON, | 45 | .pwrsts = PWRSTS_OFF_RET_ON, |
169 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 46 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
170 | .banks = 4, | 47 | .banks = 4, |
@@ -186,8 +63,6 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
186 | .name = "mpu_pwrdm", | 63 | .name = "mpu_pwrdm", |
187 | .prcm_offs = MPU_MOD, | 64 | .prcm_offs = MPU_MOD, |
188 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 65 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
189 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
190 | .wkdep_srcs = mpu_34xx_wkdeps, | ||
191 | .pwrsts = PWRSTS_OFF_RET_ON, | 66 | .pwrsts = PWRSTS_OFF_RET_ON, |
192 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 67 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
193 | .flags = PWRDM_HAS_MPU_QUIRK, | 68 | .flags = PWRDM_HAS_MPU_QUIRK, |
@@ -200,7 +75,6 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
200 | }, | 75 | }, |
201 | }; | 76 | }; |
202 | 77 | ||
203 | /* No wkdeps or sleepdeps for 34xx core apparently */ | ||
204 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | 78 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { |
205 | .name = "core_pwrdm", | 79 | .name = "core_pwrdm", |
206 | .prcm_offs = CORE_MOD, | 80 | .prcm_offs = CORE_MOD, |
@@ -208,7 +82,6 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | |||
208 | CHIP_IS_OMAP3430ES2 | | 82 | CHIP_IS_OMAP3430ES2 | |
209 | CHIP_IS_OMAP3430ES3_0), | 83 | CHIP_IS_OMAP3430ES3_0), |
210 | .pwrsts = PWRSTS_OFF_RET_ON, | 84 | .pwrsts = PWRSTS_OFF_RET_ON, |
211 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
212 | .banks = 2, | 85 | .banks = 2, |
213 | .pwrsts_mem_ret = { | 86 | .pwrsts_mem_ret = { |
214 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 87 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
@@ -220,13 +93,11 @@ static struct powerdomain core_34xx_pre_es3_1_pwrdm = { | |||
220 | }, | 93 | }, |
221 | }; | 94 | }; |
222 | 95 | ||
223 | /* No wkdeps or sleepdeps for 34xx core apparently */ | ||
224 | static struct powerdomain core_34xx_es3_1_pwrdm = { | 96 | static struct powerdomain core_34xx_es3_1_pwrdm = { |
225 | .name = "core_pwrdm", | 97 | .name = "core_pwrdm", |
226 | .prcm_offs = CORE_MOD, | 98 | .prcm_offs = CORE_MOD, |
227 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | 99 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), |
228 | .pwrsts = PWRSTS_OFF_RET_ON, | 100 | .pwrsts = PWRSTS_OFF_RET_ON, |
229 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
230 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 101 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
231 | .banks = 2, | 102 | .banks = 2, |
232 | .pwrsts_mem_ret = { | 103 | .pwrsts_mem_ret = { |
@@ -239,14 +110,10 @@ static struct powerdomain core_34xx_es3_1_pwrdm = { | |||
239 | }, | 110 | }, |
240 | }; | 111 | }; |
241 | 112 | ||
242 | /* Another case of bit name collisions between several registers: EN_DSS */ | ||
243 | static struct powerdomain dss_pwrdm = { | 113 | static struct powerdomain dss_pwrdm = { |
244 | .name = "dss_pwrdm", | 114 | .name = "dss_pwrdm", |
245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 115 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
246 | .prcm_offs = OMAP3430_DSS_MOD, | 116 | .prcm_offs = OMAP3430_DSS_MOD, |
247 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
248 | .wkdep_srcs = cam_dss_wkdeps, | ||
249 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
250 | .pwrsts = PWRSTS_OFF_RET_ON, | 117 | .pwrsts = PWRSTS_OFF_RET_ON, |
251 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 118 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
252 | .banks = 1, | 119 | .banks = 1, |
@@ -267,8 +134,6 @@ static struct powerdomain sgx_pwrdm = { | |||
267 | .name = "sgx_pwrdm", | 134 | .name = "sgx_pwrdm", |
268 | .prcm_offs = OMAP3430ES2_SGX_MOD, | 135 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
269 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
270 | .wkdep_srcs = gfx_sgx_wkdeps, | ||
271 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
272 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ | 137 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
273 | .pwrsts = PWRSTS_OFF_ON, | 138 | .pwrsts = PWRSTS_OFF_ON, |
274 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 139 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
@@ -285,8 +150,6 @@ static struct powerdomain cam_pwrdm = { | |||
285 | .name = "cam_pwrdm", | 150 | .name = "cam_pwrdm", |
286 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 151 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
287 | .prcm_offs = OMAP3430_CAM_MOD, | 152 | .prcm_offs = OMAP3430_CAM_MOD, |
288 | .wkdep_srcs = cam_dss_wkdeps, | ||
289 | .sleepdep_srcs = cam_gfx_sleepdeps, | ||
290 | .pwrsts = PWRSTS_OFF_RET_ON, | 153 | .pwrsts = PWRSTS_OFF_RET_ON, |
291 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 154 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
292 | .banks = 1, | 155 | .banks = 1, |
@@ -302,9 +165,6 @@ static struct powerdomain per_pwrdm = { | |||
302 | .name = "per_pwrdm", | 165 | .name = "per_pwrdm", |
303 | .prcm_offs = OMAP3430_PER_MOD, | 166 | .prcm_offs = OMAP3430_PER_MOD, |
304 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 167 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
305 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
306 | .wkdep_srcs = per_usbhost_wkdeps, | ||
307 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
308 | .pwrsts = PWRSTS_OFF_RET_ON, | 168 | .pwrsts = PWRSTS_OFF_RET_ON, |
309 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 169 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
310 | .banks = 1, | 170 | .banks = 1, |
@@ -326,7 +186,6 @@ static struct powerdomain neon_pwrdm = { | |||
326 | .name = "neon_pwrdm", | 186 | .name = "neon_pwrdm", |
327 | .prcm_offs = OMAP3430_NEON_MOD, | 187 | .prcm_offs = OMAP3430_NEON_MOD, |
328 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 188 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
329 | .wkdep_srcs = neon_wkdeps, | ||
330 | .pwrsts = PWRSTS_OFF_RET_ON, | 189 | .pwrsts = PWRSTS_OFF_RET_ON, |
331 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 190 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
332 | }; | 191 | }; |
@@ -335,8 +194,6 @@ static struct powerdomain usbhost_pwrdm = { | |||
335 | .name = "usbhost_pwrdm", | 194 | .name = "usbhost_pwrdm", |
336 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 195 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
337 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 196 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
338 | .wkdep_srcs = per_usbhost_wkdeps, | ||
339 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | ||
340 | .pwrsts = PWRSTS_OFF_RET_ON, | 197 | .pwrsts = PWRSTS_OFF_RET_ON, |
341 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 198 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
342 | /* | 199 | /* |