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authorThara Gopinath <thara@ti.com>2009-12-08 18:33:15 -0500
committerpaul <paul@twilight.(none)>2009-12-11 19:00:42 -0500
commit3863c74b512c1afd3ce6b2f81d8dea9f1d860968 (patch)
tree1d7d15664c0ae3a71be7949e9c52ca2f79a73811 /arch/arm/mach-omap2/powerdomains34xx.h
parent18862cbe47e37beba98f22c088fbe6fe029df889 (diff)
OMAP3: PM: Fix for MPU power domain MEM BANK position
MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomains34xx.h')
-rw-r--r--arch/arm/mach-omap2/powerdomains34xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index fd09b0827df0..588f7e07d0ea 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
190 .wkdep_srcs = mpu_34xx_wkdeps, 190 .wkdep_srcs = mpu_34xx_wkdeps,
191 .pwrsts = PWRSTS_OFF_RET_ON, 191 .pwrsts = PWRSTS_OFF_RET_ON,
192 .pwrsts_logic_ret = PWRSTS_OFF_RET, 192 .pwrsts_logic_ret = PWRSTS_OFF_RET,
193 .flags = PWRDM_HAS_MPU_QUIRK,
193 .banks = 1, 194 .banks = 1,
194 .pwrsts_mem_ret = { 195 .pwrsts_mem_ret = {
195 [0] = PWRSTS_OFF_RET, 196 [0] = PWRSTS_OFF_RET,