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authorRajendra Nayak <rnayak@ti.com>2010-12-21 22:01:19 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 22:01:19 -0500
commit9b7fc907d9378f86eb6b823bbe84ec9ed584b091 (patch)
treeb4519c2eb01d58ca4a407048bcb3fd83cf846e1f /arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
parent12627578523d2d9396cae76b1dad0ed3dccf1730 (diff)
OMAP: powerdomain: Arch specific funcs for mem control
Define the following architecture specific funtions for omap2/3/4 .pwrdm_set_mem_onst .pwrdm_set_mem_retst .pwrdm_read_mem_pwrst .pwrdm_read_prev_mem_pwrst .pwrdm_read_mem_retst .pwrdm_clear_all_prev_pwrst .pwrdm_enable_hdwr_sar .pwrdm_disable_hdwr_sar .pwrdm_wait_transition .pwrdm_set_lowpwrstchange Convert the platform-independent framework to call these functions. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: rearranged Makefile changes] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomain2xxx_3xxx.c')
-rw-r--r--arch/arm/mach-omap2/powerdomain2xxx_3xxx.c131
1 files changed, 131 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index b7ea191539e5..6cdf67860cb3 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -41,6 +41,50 @@ static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
41 OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); 41 OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK);
42} 42}
43 43
44static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
45 u8 pwrst)
46{
47 u32 m;
48
49 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
50
51 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
52 OMAP2_PM_PWSTCTRL);
53
54 return 0;
55}
56
57static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
58 u8 pwrst)
59{
60 u32 m;
61
62 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
63
64 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
65 OMAP2_PM_PWSTCTRL);
66
67 return 0;
68}
69
70static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
71{
72 u32 m;
73
74 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
75
76 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m);
77}
78
79static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
80{
81 u32 m;
82
83 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
84
85 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, m);
86}
87
44static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) 88static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
45{ 89{
46 u32 v; 90 u32 v;
@@ -52,6 +96,33 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
52 return 0; 96 return 0;
53} 97}
54 98
99static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
100{
101 u32 c = 0;
102
103 /*
104 * REVISIT: pwrdm_wait_transition() may be better implemented
105 * via a callback and a periodic timer check -- how long do we expect
106 * powerdomain transitions to take?
107 */
108
109 /* XXX Is this udelay() value meaningful? */
110 while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
111 OMAP_INTRANSITION_MASK) &&
112 (c++ < PWRDM_TRANSITION_BAILOUT))
113 udelay(1);
114
115 if (c > PWRDM_TRANSITION_BAILOUT) {
116 printk(KERN_ERR "powerdomain: waited too long for "
117 "powerdomain %s to complete transition\n", pwrdm->name);
118 return -EAGAIN;
119 }
120
121 pr_debug("powerdomain: completed transition in %d loops\n", c);
122
123 return 0;
124}
125
55/* Applicable only for OMAP3. Not supported on OMAP2 */ 126/* Applicable only for OMAP3. Not supported on OMAP2 */
56static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) 127static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
57{ 128{
@@ -77,11 +148,62 @@ static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
77 OMAP3430_LASTLOGICSTATEENTERED_MASK); 148 OMAP3430_LASTLOGICSTATEENTERED_MASK);
78} 149}
79 150
151static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
152{
153 switch (bank) {
154 case 0:
155 return OMAP3430_LASTMEM1STATEENTERED_MASK;
156 case 1:
157 return OMAP3430_LASTMEM2STATEENTERED_MASK;
158 case 2:
159 return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
160 case 3:
161 return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
162 default:
163 WARN_ON(1); /* should never happen */
164 return -EEXIST;
165 }
166 return 0;
167}
168
169static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
170{
171 u32 m;
172
173 m = omap3_get_mem_bank_lastmemst_mask(bank);
174
175 return prm_read_mod_bits_shift(pwrdm->prcm_offs,
176 OMAP3430_PM_PREPWSTST, m);
177}
178
179static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
180{
181 prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
182 return 0;
183}
184
185static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
186{
187 return prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
188 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
189}
190
191static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
192{
193 return prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
194 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
195}
196
80struct pwrdm_ops omap2_pwrdm_operations = { 197struct pwrdm_ops omap2_pwrdm_operations = {
81 .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, 198 .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
82 .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, 199 .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
83 .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, 200 .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
84 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, 201 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
202 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
203 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
204 .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
205 .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
206 .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
85}; 207};
86 208
87struct pwrdm_ops omap3_pwrdm_operations = { 209struct pwrdm_ops omap3_pwrdm_operations = {
@@ -93,4 +215,13 @@ struct pwrdm_ops omap3_pwrdm_operations = {
93 .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, 215 .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
94 .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, 216 .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
95 .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, 217 .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst,
218 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
219 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
220 .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
221 .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
222 .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst,
223 .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst,
224 .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar,
225 .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
226 .pwrdm_wait_transition = omap2_pwrdm_wait_transition,
96}; 227};