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authorAbhijit Pagare <abhijitpagare@ti.com>2010-01-26 22:12:51 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:51 -0500
commit3790300903e6a98ce5f5391f4d435959266f79e7 (patch)
treecd78bf9d180466df0cd5b2f0c5b5c46d6471a54e /arch/arm/mach-omap2/powerdomain.c
parentc6a6e6e203ee9a34fa53f773272f21d48b4e3454 (diff)
ARM: OMAP4: PM: OMAP4 Power Domain Porting Related Clean-up.
Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4. Hence we need different macros for identifying platform specific offsets. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomain.c')
-rw-r--r--arch/arm/mach-omap2/powerdomain.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 26b3f3ee82a3..e503050dda06 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -710,7 +710,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
710 710
711 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, 711 prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
712 (pwrst << OMAP_POWERSTATE_SHIFT), 712 (pwrst << OMAP_POWERSTATE_SHIFT),
713 pwrdm->prcm_offs, PM_PWSTCTRL); 713 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
714 714
715 return 0; 715 return 0;
716} 716}
@@ -728,7 +728,7 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
728 if (!pwrdm) 728 if (!pwrdm)
729 return -EINVAL; 729 return -EINVAL;
730 730
731 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTCTRL, 731 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL,
732 OMAP_POWERSTATE_MASK); 732 OMAP_POWERSTATE_MASK);
733} 733}
734 734
@@ -745,7 +745,7 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
745 if (!pwrdm) 745 if (!pwrdm)
746 return -EINVAL; 746 return -EINVAL;
747 747
748 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, 748 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
749 OMAP_POWERSTATEST_MASK); 749 OMAP_POWERSTATEST_MASK);
750} 750}
751 751
@@ -796,7 +796,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
796 */ 796 */
797 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE, 797 prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE,
798 (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)), 798 (pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE)),
799 pwrdm->prcm_offs, PM_PWSTCTRL); 799 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
800 800
801 return 0; 801 return 0;
802} 802}
@@ -856,7 +856,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
856 } 856 }
857 857
858 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), 858 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
859 pwrdm->prcm_offs, PM_PWSTCTRL); 859 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
860 860
861 return 0; 861 return 0;
862} 862}
@@ -917,7 +917,7 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
917 } 917 }
918 918
919 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, 919 prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
920 PM_PWSTCTRL); 920 OMAP2_PM_PWSTCTRL);
921 921
922 return 0; 922 return 0;
923} 923}
@@ -936,7 +936,7 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
936 if (!pwrdm) 936 if (!pwrdm)
937 return -EINVAL; 937 return -EINVAL;
938 938
939 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, 939 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
940 OMAP3430_LOGICSTATEST); 940 OMAP3430_LOGICSTATEST);
941} 941}
942 942
@@ -1010,7 +1010,7 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
1010 return -EEXIST; 1010 return -EEXIST;
1011 } 1011 }
1012 1012
1013 return prm_read_mod_bits_shift(pwrdm->prcm_offs, PM_PWSTST, m); 1013 return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m);
1014} 1014}
1015 1015
1016/** 1016/**
@@ -1114,7 +1114,7 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
1114 pwrdm->name); 1114 pwrdm->name);
1115 1115
1116 prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 1116 prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
1117 pwrdm->prcm_offs, PM_PWSTCTRL); 1117 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
1118 1118
1119 return 0; 1119 return 0;
1120} 1120}
@@ -1142,7 +1142,7 @@ int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
1142 pwrdm->name); 1142 pwrdm->name);
1143 1143
1144 prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, 1144 prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
1145 pwrdm->prcm_offs, PM_PWSTCTRL); 1145 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
1146 1146
1147 return 0; 1147 return 0;
1148} 1148}
@@ -1183,7 +1183,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
1183 */ 1183 */
1184 1184
1185 /* XXX Is this udelay() value meaningful? */ 1185 /* XXX Is this udelay() value meaningful? */
1186 while ((prm_read_mod_reg(pwrdm->prcm_offs, PM_PWSTST) & 1186 while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
1187 OMAP_INTRANSITION) && 1187 OMAP_INTRANSITION) &&
1188 (c++ < PWRDM_TRANSITION_BAILOUT)) 1188 (c++ < PWRDM_TRANSITION_BAILOUT))
1189 udelay(1); 1189 udelay(1);