diff options
author | Paul Walmsley <paul@pwsan.com> | 2008-06-25 20:09:37 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-21 16:26:39 -0400 |
commit | 0b7cbfb5e1f03f58241bf236cca303ee45e14b4f (patch) | |
tree | e5507290b827ee4fa60cf7a7a7f3f473d2c1a453 /arch/arm/mach-omap2/powerdomain.c | |
parent | 5955902fb5c31f6a784ddb7aa16079a2bec588f5 (diff) |
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/powerdomain.c')
-rw-r--r-- | arch/arm/mach-omap2/powerdomain.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 9a803492b28f..73e2971b1757 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
@@ -1003,6 +1003,74 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |||
1003 | } | 1003 | } |
1004 | 1004 | ||
1005 | /** | 1005 | /** |
1006 | * pwrdm_enable_hdwr_sar - enable automatic hardware SAR for a pwrdm | ||
1007 | * @pwrdm: struct powerdomain * | ||
1008 | * | ||
1009 | * Enable automatic context save-and-restore upon power state change | ||
1010 | * for some devices in a powerdomain. Warning: this only affects a | ||
1011 | * subset of devices in a powerdomain; check the TRM closely. Returns | ||
1012 | * -EINVAL if the powerdomain pointer is null or if the powerdomain | ||
1013 | * does not support automatic save-and-restore, or returns 0 upon | ||
1014 | * success. | ||
1015 | */ | ||
1016 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | ||
1017 | { | ||
1018 | if (!pwrdm) | ||
1019 | return -EINVAL; | ||
1020 | |||
1021 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | ||
1022 | return -EINVAL; | ||
1023 | |||
1024 | pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", | ||
1025 | pwrdm->name); | ||
1026 | |||
1027 | prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
1028 | pwrdm->prcm_offs, PM_PWSTCTRL); | ||
1029 | |||
1030 | return 0; | ||
1031 | } | ||
1032 | |||
1033 | /** | ||
1034 | * pwrdm_disable_hdwr_sar - disable automatic hardware SAR for a pwrdm | ||
1035 | * @pwrdm: struct powerdomain * | ||
1036 | * | ||
1037 | * Disable automatic context save-and-restore upon power state change | ||
1038 | * for some devices in a powerdomain. Warning: this only affects a | ||
1039 | * subset of devices in a powerdomain; check the TRM closely. Returns | ||
1040 | * -EINVAL if the powerdomain pointer is null or if the powerdomain | ||
1041 | * does not support automatic save-and-restore, or returns 0 upon | ||
1042 | * success. | ||
1043 | */ | ||
1044 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | ||
1045 | { | ||
1046 | if (!pwrdm) | ||
1047 | return -EINVAL; | ||
1048 | |||
1049 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | ||
1050 | return -EINVAL; | ||
1051 | |||
1052 | pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", | ||
1053 | pwrdm->name); | ||
1054 | |||
1055 | prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, | ||
1056 | pwrdm->prcm_offs, PM_PWSTCTRL); | ||
1057 | |||
1058 | return 0; | ||
1059 | } | ||
1060 | |||
1061 | /** | ||
1062 | * pwrdm_has_hdwr_sar - test whether powerdomain supports hardware SAR | ||
1063 | * @pwrdm: struct powerdomain * | ||
1064 | * | ||
1065 | * Returns 1 if powerdomain 'pwrdm' supports hardware save-and-restore | ||
1066 | * for some devices, or 0 if it does not. | ||
1067 | */ | ||
1068 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) | ||
1069 | { | ||
1070 | return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0; | ||
1071 | } | ||
1072 | |||
1073 | /** | ||
1006 | * pwrdm_wait_transition - wait for powerdomain power transition to finish | 1074 | * pwrdm_wait_transition - wait for powerdomain power transition to finish |
1007 | * @pwrdm: struct powerdomain * to wait for | 1075 | * @pwrdm: struct powerdomain * to wait for |
1008 | * | 1076 | * |