OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_"

Now that OMAP4-specific PRCM functions have been added, distinguish the
existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_".

This patch should not result in any functional change.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Cc: Liam Girdwood <lrg@slimlogic.co.uk>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>

1 files changed, 72 insertions, 71 deletions

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index cfff321c747e..1ca6ef4c25b3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -105,12 +105,12 @@ static void omap3_enable_io_chain(void)
         int timeout = 0;
 
         if (omap_rev() >= OMAP3430_REV_ES3_1) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                      PM_WKEN);
                 /* Do a readback to assure write has been done */
-                prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+                omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-                while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+                while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
                          OMAP3430_ST_IO_CHAIN_MASK)) {
                         timeout++;
                         if (timeout > 1000) {
@@ -118,7 +118,7 @@ static void omap3_enable_io_chain(void)
                                        "activation failed.\n");
                                 return;
                         }
-                        prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
+                        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
                                              WKUP_MOD, PM_WKEN);
                 }
         }
@@ -127,7 +127,7 @@ static void omap3_enable_io_chain(void)
 static void omap3_disable_io_chain(void)
 {
         if (omap_rev() >= OMAP3430_REV_ES3_1)
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                        PM_WKEN);
 }
 
@@ -221,27 +221,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
         int c = 0;
 
-        wkst = prm_read_mod_reg(module, wkst_off);
-        wkst &= prm_read_mod_reg(module, grpsel_off);
+        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
         if (wkst) {
-                iclk = cm_read_mod_reg(module, iclk_off);
-                fclk = cm_read_mod_reg(module, fclk_off);
+                iclk = omap2_cm_read_mod_reg(module, iclk_off);
+                fclk = omap2_cm_read_mod_reg(module, fclk_off);
                 while (wkst) {
                         clken = wkst;
-                        cm_set_mod_reg_bits(clken, module, iclk_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
                         /*
                          * For USBHOST, we don't know whether HOST1 or
                          * HOST2 woke us up, so enable both f-clocks
                          */
                         if (module == OMAP3430ES2_USBHOST_MOD)
                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-                        cm_set_mod_reg_bits(clken, module, fclk_off);
-                        prm_write_mod_reg(wkst, module, wkst_off);
-                        wkst = prm_read_mod_reg(module, wkst_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
+                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
+                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
                         c++;
                 }
-                cm_write_mod_reg(iclk, module, iclk_off);
-                cm_write_mod_reg(fclk, module, fclk_off);
+                omap2_cm_write_mod_reg(iclk, module, iclk_off);
+                omap2_cm_write_mod_reg(fclk, module, fclk_off);
         }
 
         return c;
@@ -284,9 +284,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         u32 irqenable_mpu, irqstatus_mpu;
         int c = 0;
 
-        irqenable_mpu = prm_read_mod_reg(OCP_MOD,
+        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
         irqstatus_mpu &= irqenable_mpu;
 
@@ -307,10 +307,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
                              "no code to handle it (%08x)\n", irqstatus_mpu);
                 }
 
-                prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-                irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
                 irqstatus_mpu &= irqenable_mpu;
 
@@ -398,7 +398,7 @@ void omap_sram_idle(void)
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
              core_next_state < PWRDM_POWER_ON)) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
 
@@ -471,7 +471,7 @@ void omap_sram_idle(void)
                 omap_uart_resume_idle(0);
                 omap_uart_resume_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF)
-                        prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
+                        omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
         }
@@ -495,7 +495,8 @@ console_still_active:
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
              core_next_state < PWRDM_POWER_ON)) {
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                             PM_WKEN);
                 omap3_disable_io_chain();
         }
 
@@ -633,21 +634,21 @@ static struct platform_suspend_ops omap_pm_ops = {
 static void __init omap3_iva_idle(void)
 {
         /* ensure IVA2 clock is disabled */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* if no clock activity, nothing else to do */
-        if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+        if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
               OMAP3430_CLKACTIVITY_IVA2_MASK))
                 return;
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Enable IVA2 clock */
-        cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
+        omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Set IVA2 boot mode to 'idle' */
@@ -655,13 +656,13 @@ static void __init omap3_iva_idle(void)
                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 
         /* Un-reset IVA2 */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Disable IVA2 clock */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
@@ -685,10 +686,10 @@ static void __init omap3_d2d_idle(void)
         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 
         /* reset modem */
-        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
                           CORE_MOD, OMAP2_RM_RSTCTRL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 }
 
 static void __init prcm_setup_regs(void)
@@ -703,23 +704,23 @@ static void __init prcm_setup_regs(void)
 
         /* XXX Reset all wkdeps. This should be done when initializing
          * powerdomains */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
-                prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
         } else
-                prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 
         /*
          * Enable interface clock autoidle for all modules.
          * Note that in the long run this should be done by clockfw
          */
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_MODEM_MASK |
                 OMAP3430ES2_AUTO_MMC3_MASK |
                 OMAP3430ES2_AUTO_ICR_MASK |
@@ -752,7 +753,7 @@ static void __init prcm_setup_regs(void)
                 OMAP3430_AUTO_SSI_MASK,
                 CORE_MOD, CM_AUTOIDLE1);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_PKA_MASK |
                 OMAP3430_AUTO_AES1_MASK |
                 OMAP3430_AUTO_RNG_MASK |
@@ -761,13 +762,13 @@ static void __init prcm_setup_regs(void)
                 CORE_MOD, CM_AUTOIDLE2);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
+                omap2_cm_write_mod_reg(
                         OMAP3430_AUTO_MAD2D_MASK |
                         OMAP3430ES2_AUTO_USBTLL_MASK,
                         CORE_MOD, CM_AUTOIDLE3);
         }
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_WDT2_MASK |
                 OMAP3430_AUTO_WDT1_MASK |
                 OMAP3430_AUTO_GPIO1_MASK |
@@ -776,17 +777,17 @@ static void __init prcm_setup_regs(void)
                 OMAP3430_AUTO_GPT1_MASK,
                 WKUP_MOD, CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_DSS_MASK,
                 OMAP3430_DSS_MOD,
                 CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_CAM_MASK,
                 OMAP3430_CAM_MOD,
                 CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 omap3630_auto_uart4_mask |
                 OMAP3430_AUTO_GPIO6_MASK |
                 OMAP3430_AUTO_GPIO5_MASK |
@@ -810,7 +811,7 @@ static void __init prcm_setup_regs(void)
                 CM_AUTOIDLE);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
+                omap2_cm_write_mod_reg(
                         OMAP3430ES2_AUTO_USBHOST_MASK,
                         OMAP3430ES2_USBHOST_MOD,
                         CM_AUTOIDLE);
@@ -822,16 +823,16 @@ static void __init prcm_setup_regs(void)
          * Set all plls to autoidle. This is needed until autoidle is
          * enabled by clockfw
          */
-        cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
                          MPU_MOD,
                          CM_AUTOIDLE2);
-        cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+        omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
                          PLL_MOD,
                          CM_AUTOIDLE);
-        cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
                          PLL_MOD,
                          CM_AUTOIDLE2);
 
@@ -840,31 +841,31 @@ static void __init prcm_setup_regs(void)
          * sys_clkreq. In the long run clock framework should
          * take care of this.
          */
-        prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+        omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
                              OMAP3430_GR_MOD,
                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 
         /* setup wakup source */
-        prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
                           WKUP_MOD, PM_WKEN);
         /* No need to write EN_IO, that is always enabled */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
                           OMAP3430_GRPSEL_GPT1_MASK |
                           OMAP3430_GRPSEL_GPT12_MASK,
                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
         /* For some reason IO doesn't generate wakeup event even if
          * it is selected to mpu wakeup goup */
-        prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
         /* Enable PM_WKEN to support DSS LPR */
-        prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(omap3630_en_uart4_mask |
+        omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
@@ -872,7 +873,7 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(omap3630_grpsel_uart4_mask |
+        omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
                           OMAP3430_GRPSEL_GPIO2_MASK |
                           OMAP3430_GRPSEL_GPIO3_MASK |
                           OMAP3430_GRPSEL_GPIO4_MASK |
@@ -885,22 +886,22 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
-        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 
         /* Clear any pending 'reset' flags */
-        prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 
         /* Clear any pending PRCM interrupts */
-        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
         omap3_iva_idle();
         omap3_d2d_idle();