diff options
author | Tony Lindgren <tony@atomide.com> | 2011-03-11 12:20:03 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2011-03-11 12:20:03 -0500 |
commit | a2358a7bc35e388978fc2f7f6b071a0fd27d78c1 (patch) | |
tree | fbdc2ddb066243a11aebc490c4d54e6a42be51e2 /arch/arm/mach-omap2/pm34xx.c | |
parent | 94a06b74e724caabcf0464c81527cfbcae0c8aff (diff) | |
parent | a08572ae529b1e8de12393eeced661feae8fd44c (diff) |
Merge branch 'integration-2.6.39-for-tony' of git://git.pwsan.com/linux-integration into omap-for-linus
Conflicts:
arch/arm/mach-omap2/pm34xx.c
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
-rw-r--r-- | arch/arm/mach-omap2/pm34xx.c | 127 |
1 files changed, 4 insertions, 123 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1883a464aace..b5361a1260fc 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -491,7 +491,7 @@ console_still_active: | |||
491 | 491 | ||
492 | pwrdm_post_transition(); | 492 | pwrdm_post_transition(); |
493 | 493 | ||
494 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); | 494 | clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
495 | } | 495 | } |
496 | 496 | ||
497 | int omap3_can_sleep(void) | 497 | int omap3_can_sleep(void) |
@@ -683,134 +683,15 @@ static void __init omap3_d2d_idle(void) | |||
683 | 683 | ||
684 | static void __init prcm_setup_regs(void) | 684 | static void __init prcm_setup_regs(void) |
685 | { | 685 | { |
686 | u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? | ||
687 | OMAP3630_AUTO_UART4_MASK : 0; | ||
688 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? | 686 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
689 | OMAP3630_EN_UART4_MASK : 0; | 687 | OMAP3630_EN_UART4_MASK : 0; |
690 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | 688 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? |
691 | OMAP3630_GRPSEL_UART4_MASK : 0; | 689 | OMAP3630_GRPSEL_UART4_MASK : 0; |
692 | 690 | ||
693 | /* | 691 | /* XXX This should be handled by hwmod code or SCM init code */ |
694 | * Enable interface clock autoidle for all modules. | ||
695 | * Note that in the long run this should be done by clockfw | ||
696 | */ | ||
697 | omap2_cm_write_mod_reg( | ||
698 | OMAP3430_AUTO_MODEM_MASK | | ||
699 | OMAP3430ES2_AUTO_MMC3_MASK | | ||
700 | OMAP3430ES2_AUTO_ICR_MASK | | ||
701 | OMAP3430_AUTO_AES2_MASK | | ||
702 | OMAP3430_AUTO_SHA12_MASK | | ||
703 | OMAP3430_AUTO_DES2_MASK | | ||
704 | OMAP3430_AUTO_MMC2_MASK | | ||
705 | OMAP3430_AUTO_MMC1_MASK | | ||
706 | OMAP3430_AUTO_MSPRO_MASK | | ||
707 | OMAP3430_AUTO_HDQ_MASK | | ||
708 | OMAP3430_AUTO_MCSPI4_MASK | | ||
709 | OMAP3430_AUTO_MCSPI3_MASK | | ||
710 | OMAP3430_AUTO_MCSPI2_MASK | | ||
711 | OMAP3430_AUTO_MCSPI1_MASK | | ||
712 | OMAP3430_AUTO_I2C3_MASK | | ||
713 | OMAP3430_AUTO_I2C2_MASK | | ||
714 | OMAP3430_AUTO_I2C1_MASK | | ||
715 | OMAP3430_AUTO_UART2_MASK | | ||
716 | OMAP3430_AUTO_UART1_MASK | | ||
717 | OMAP3430_AUTO_GPT11_MASK | | ||
718 | OMAP3430_AUTO_GPT10_MASK | | ||
719 | OMAP3430_AUTO_MCBSP5_MASK | | ||
720 | OMAP3430_AUTO_MCBSP1_MASK | | ||
721 | OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */ | ||
722 | OMAP3430_AUTO_MAILBOXES_MASK | | ||
723 | OMAP3430_AUTO_OMAPCTRL_MASK | | ||
724 | OMAP3430ES1_AUTO_FSHOSTUSB_MASK | | ||
725 | OMAP3430_AUTO_HSOTGUSB_MASK | | ||
726 | OMAP3430_AUTO_SAD2D_MASK | | ||
727 | OMAP3430_AUTO_SSI_MASK, | ||
728 | CORE_MOD, CM_AUTOIDLE1); | ||
729 | |||
730 | omap2_cm_write_mod_reg( | ||
731 | OMAP3430_AUTO_PKA_MASK | | ||
732 | OMAP3430_AUTO_AES1_MASK | | ||
733 | OMAP3430_AUTO_RNG_MASK | | ||
734 | OMAP3430_AUTO_SHA11_MASK | | ||
735 | OMAP3430_AUTO_DES1_MASK, | ||
736 | CORE_MOD, CM_AUTOIDLE2); | ||
737 | |||
738 | if (omap_rev() > OMAP3430_REV_ES1_0) { | ||
739 | omap2_cm_write_mod_reg( | ||
740 | OMAP3430_AUTO_MAD2D_MASK | | ||
741 | OMAP3430ES2_AUTO_USBTLL_MASK, | ||
742 | CORE_MOD, CM_AUTOIDLE3); | ||
743 | } | ||
744 | |||
745 | omap2_cm_write_mod_reg( | ||
746 | OMAP3430_AUTO_WDT2_MASK | | ||
747 | OMAP3430_AUTO_WDT1_MASK | | ||
748 | OMAP3430_AUTO_GPIO1_MASK | | ||
749 | OMAP3430_AUTO_32KSYNC_MASK | | ||
750 | OMAP3430_AUTO_GPT12_MASK | | ||
751 | OMAP3430_AUTO_GPT1_MASK, | ||
752 | WKUP_MOD, CM_AUTOIDLE); | ||
753 | |||
754 | omap2_cm_write_mod_reg( | ||
755 | OMAP3430_AUTO_DSS_MASK, | ||
756 | OMAP3430_DSS_MOD, | ||
757 | CM_AUTOIDLE); | ||
758 | |||
759 | omap2_cm_write_mod_reg( | ||
760 | OMAP3430_AUTO_CAM_MASK, | ||
761 | OMAP3430_CAM_MOD, | ||
762 | CM_AUTOIDLE); | ||
763 | |||
764 | omap2_cm_write_mod_reg( | ||
765 | omap3630_auto_uart4_mask | | ||
766 | OMAP3430_AUTO_GPIO6_MASK | | ||
767 | OMAP3430_AUTO_GPIO5_MASK | | ||
768 | OMAP3430_AUTO_GPIO4_MASK | | ||
769 | OMAP3430_AUTO_GPIO3_MASK | | ||
770 | OMAP3430_AUTO_GPIO2_MASK | | ||
771 | OMAP3430_AUTO_WDT3_MASK | | ||
772 | OMAP3430_AUTO_UART3_MASK | | ||
773 | OMAP3430_AUTO_GPT9_MASK | | ||
774 | OMAP3430_AUTO_GPT8_MASK | | ||
775 | OMAP3430_AUTO_GPT7_MASK | | ||
776 | OMAP3430_AUTO_GPT6_MASK | | ||
777 | OMAP3430_AUTO_GPT5_MASK | | ||
778 | OMAP3430_AUTO_GPT4_MASK | | ||
779 | OMAP3430_AUTO_GPT3_MASK | | ||
780 | OMAP3430_AUTO_GPT2_MASK | | ||
781 | OMAP3430_AUTO_MCBSP4_MASK | | ||
782 | OMAP3430_AUTO_MCBSP3_MASK | | ||
783 | OMAP3430_AUTO_MCBSP2_MASK, | ||
784 | OMAP3430_PER_MOD, | ||
785 | CM_AUTOIDLE); | ||
786 | |||
787 | if (omap_rev() > OMAP3430_REV_ES1_0) { | ||
788 | omap2_cm_write_mod_reg( | ||
789 | OMAP3430ES2_AUTO_USBHOST_MASK, | ||
790 | OMAP3430ES2_USBHOST_MOD, | ||
791 | CM_AUTOIDLE); | ||
792 | } | ||
793 | |||
794 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); | 692 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
795 | 693 | ||
796 | /* | 694 | /* |
797 | * Set all plls to autoidle. This is needed until autoidle is | ||
798 | * enabled by clockfw | ||
799 | */ | ||
800 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, | ||
801 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
802 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, | ||
803 | MPU_MOD, | ||
804 | CM_AUTOIDLE2); | ||
805 | omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | | ||
806 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), | ||
807 | PLL_MOD, | ||
808 | CM_AUTOIDLE); | ||
809 | omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, | ||
810 | PLL_MOD, | ||
811 | CM_AUTOIDLE2); | ||
812 | |||
813 | /* | ||
814 | * Enable control of expternal oscillator through | 695 | * Enable control of expternal oscillator through |
815 | * sys_clkreq. In the long run clock framework should | 696 | * sys_clkreq. In the long run clock framework should |
816 | * take care of this. | 697 | * take care of this. |
@@ -969,10 +850,10 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |||
969 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | 850 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
970 | { | 851 | { |
971 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | 852 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) |
972 | omap2_clkdm_allow_idle(clkdm); | 853 | clkdm_allow_idle(clkdm); |
973 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | 854 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
974 | atomic_read(&clkdm->usecount) == 0) | 855 | atomic_read(&clkdm->usecount) == 0) |
975 | omap2_clkdm_sleep(clkdm); | 856 | clkdm_sleep(clkdm); |
976 | return 0; | 857 | return 0; |
977 | } | 858 | } |
978 | 859 | ||