aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/pm34xx.c
diff options
context:
space:
mode:
authorPaul Walmsley <paul@pwsan.com>2010-05-18 20:47:24 -0400
committerPaul Walmsley <paul@pwsan.com>2010-05-20 14:31:05 -0400
commit2bc4ef71c5a3b6986b452d6c530777974d11ef4a (patch)
treefbb479aae791394b75fd598d279bb52cf015042d /arch/arm/mach-omap2/pm34xx.c
parentf38ca10a79a0cd9902b8a470901951354802faa1 (diff)
OMAP3 PRCM: convert OMAP3 PRCM macros to the _SHIFT/_MASK suffixes
Fix all of the remaining OMAP3 PRCM register shift/bitmask macros that did not use the _SHIFT/_MASK suffixes to use them. This makes the use of these macros consistent. It is intended to reduce error, as code can be inspected visually by reviewers to ensure that bitshifts and bitmasks are used in the appropriate places. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
-rw-r--r--arch/arm/mach-omap2/pm34xx.c178
1 files changed, 90 insertions, 88 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 24c1966f935e..dd09d80ea3eb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -94,19 +94,20 @@ static void omap3_enable_io_chain(void)
94 int timeout = 0; 94 int timeout = 0;
95 95
96 if (omap_rev() >= OMAP3430_REV_ES3_1) { 96 if (omap_rev() >= OMAP3430_REV_ES3_1) {
97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 97 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
98 PM_WKEN);
98 /* Do a readback to assure write has been done */ 99 /* Do a readback to assure write has been done */
99 prm_read_mod_reg(WKUP_MOD, PM_WKEN); 100 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
100 101
101 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & 102 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
102 OMAP3430_ST_IO_CHAIN)) { 103 OMAP3430_ST_IO_CHAIN_MASK)) {
103 timeout++; 104 timeout++;
104 if (timeout > 1000) { 105 if (timeout > 1000) {
105 printk(KERN_ERR "Wake up daisy chain " 106 printk(KERN_ERR "Wake up daisy chain "
106 "activation failed.\n"); 107 "activation failed.\n");
107 return; 108 return;
108 } 109 }
109 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, 110 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
110 WKUP_MOD, PM_WKST); 111 WKUP_MOD, PM_WKST);
111 } 112 }
112 } 113 }
@@ -115,7 +116,8 @@ static void omap3_enable_io_chain(void)
115static void omap3_disable_io_chain(void) 116static void omap3_disable_io_chain(void)
116{ 117{
117 if (omap_rev() >= OMAP3430_REV_ES3_1) 118 if (omap_rev() >= OMAP3430_REV_ES3_1)
118 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); 119 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
120 PM_WKEN);
119} 121}
120 122
121static void omap3_core_save_context(void) 123static void omap3_core_save_context(void)
@@ -278,7 +280,8 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
278 irqstatus_mpu &= irqenable_mpu; 280 irqstatus_mpu &= irqenable_mpu;
279 281
280 do { 282 do {
281 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { 283 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
284 OMAP3430_IO_ST_MASK)) {
282 c = _prcm_int_handle_wakeup(); 285 c = _prcm_int_handle_wakeup();
283 286
284 /* 287 /*
@@ -384,7 +387,7 @@ void omap_sram_idle(void)
384 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 387 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
385 if (per_next_state < PWRDM_POWER_ON || 388 if (per_next_state < PWRDM_POWER_ON ||
386 core_next_state < PWRDM_POWER_ON) { 389 core_next_state < PWRDM_POWER_ON) {
387 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); 390 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
388 omap3_enable_io_chain(); 391 omap3_enable_io_chain();
389 } 392 }
390 393
@@ -458,7 +461,7 @@ void omap_sram_idle(void)
458 omap_uart_resume_idle(0); 461 omap_uart_resume_idle(0);
459 omap_uart_resume_idle(1); 462 omap_uart_resume_idle(1);
460 if (core_next_state == PWRDM_POWER_OFF) 463 if (core_next_state == PWRDM_POWER_OFF)
461 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, 464 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
462 OMAP3430_GR_MOD, 465 OMAP3430_GR_MOD,
463 OMAP3_PRM_VOLTCTRL_OFFSET); 466 OMAP3_PRM_VOLTCTRL_OFFSET);
464 } 467 }
@@ -476,9 +479,8 @@ void omap_sram_idle(void)
476 } 479 }
477 480
478 /* Disable IO-PAD and IO-CHAIN wakeup */ 481 /* Disable IO-PAD and IO-CHAIN wakeup */
479 if (per_next_state < PWRDM_POWER_ON || 482 if (core_next_state < PWRDM_POWER_ON) {
480 core_next_state < PWRDM_POWER_ON) { 483 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
481 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
482 omap3_disable_io_chain(); 484 omap3_disable_io_chain();
483 } 485 }
484 486
@@ -699,9 +701,9 @@ static void __init omap3_iva_idle(void)
699 return; 701 return;
700 702
701 /* Reset IVA2 */ 703 /* Reset IVA2 */
702 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 704 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
703 OMAP3430_RST2_IVA2 | 705 OMAP3430_RST2_IVA2_MASK |
704 OMAP3430_RST3_IVA2, 706 OMAP3430_RST3_IVA2_MASK,
705 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 707 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
706 708
707 /* Enable IVA2 clock */ 709 /* Enable IVA2 clock */
@@ -719,9 +721,9 @@ static void __init omap3_iva_idle(void)
719 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); 721 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
720 722
721 /* Reset IVA2 */ 723 /* Reset IVA2 */
722 prm_write_mod_reg(OMAP3430_RST1_IVA2 | 724 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
723 OMAP3430_RST2_IVA2 | 725 OMAP3430_RST2_IVA2_MASK |
724 OMAP3430_RST3_IVA2, 726 OMAP3430_RST3_IVA2_MASK,
725 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); 727 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
726} 728}
727 729
@@ -743,8 +745,8 @@ static void __init omap3_d2d_idle(void)
743 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 745 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
744 746
745 /* reset modem */ 747 /* reset modem */
746 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | 748 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
747 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, 749 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
748 CORE_MOD, OMAP2_RM_RSTCTRL); 750 CORE_MOD, OMAP2_RM_RSTCTRL);
749 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); 751 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
750} 752}
@@ -770,97 +772,97 @@ static void __init prcm_setup_regs(void)
770 * Note that in the long run this should be done by clockfw 772 * Note that in the long run this should be done by clockfw
771 */ 773 */
772 cm_write_mod_reg( 774 cm_write_mod_reg(
773 OMAP3430_AUTO_MODEM | 775 OMAP3430_AUTO_MODEM_MASK |
774 OMAP3430ES2_AUTO_MMC3 | 776 OMAP3430ES2_AUTO_MMC3_MASK |
775 OMAP3430ES2_AUTO_ICR | 777 OMAP3430ES2_AUTO_ICR_MASK |
776 OMAP3430_AUTO_AES2 | 778 OMAP3430_AUTO_AES2_MASK |
777 OMAP3430_AUTO_SHA12 | 779 OMAP3430_AUTO_SHA12_MASK |
778 OMAP3430_AUTO_DES2 | 780 OMAP3430_AUTO_DES2_MASK |
779 OMAP3430_AUTO_MMC2 | 781 OMAP3430_AUTO_MMC2_MASK |
780 OMAP3430_AUTO_MMC1 | 782 OMAP3430_AUTO_MMC1_MASK |
781 OMAP3430_AUTO_MSPRO | 783 OMAP3430_AUTO_MSPRO_MASK |
782 OMAP3430_AUTO_HDQ | 784 OMAP3430_AUTO_HDQ_MASK |
783 OMAP3430_AUTO_MCSPI4 | 785 OMAP3430_AUTO_MCSPI4_MASK |
784 OMAP3430_AUTO_MCSPI3 | 786 OMAP3430_AUTO_MCSPI3_MASK |
785 OMAP3430_AUTO_MCSPI2 | 787 OMAP3430_AUTO_MCSPI2_MASK |
786 OMAP3430_AUTO_MCSPI1 | 788 OMAP3430_AUTO_MCSPI1_MASK |
787 OMAP3430_AUTO_I2C3 | 789 OMAP3430_AUTO_I2C3_MASK |
788 OMAP3430_AUTO_I2C2 | 790 OMAP3430_AUTO_I2C2_MASK |
789 OMAP3430_AUTO_I2C1 | 791 OMAP3430_AUTO_I2C1_MASK |
790 OMAP3430_AUTO_UART2 | 792 OMAP3430_AUTO_UART2_MASK |
791 OMAP3430_AUTO_UART1 | 793 OMAP3430_AUTO_UART1_MASK |
792 OMAP3430_AUTO_GPT11 | 794 OMAP3430_AUTO_GPT11_MASK |
793 OMAP3430_AUTO_GPT10 | 795 OMAP3430_AUTO_GPT10_MASK |
794 OMAP3430_AUTO_MCBSP5 | 796 OMAP3430_AUTO_MCBSP5_MASK |
795 OMAP3430_AUTO_MCBSP1 | 797 OMAP3430_AUTO_MCBSP1_MASK |
796 OMAP3430ES1_AUTO_FAC | /* This is es1 only */ 798 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
797 OMAP3430_AUTO_MAILBOXES | 799 OMAP3430_AUTO_MAILBOXES_MASK |
798 OMAP3430_AUTO_OMAPCTRL | 800 OMAP3430_AUTO_OMAPCTRL_MASK |
799 OMAP3430ES1_AUTO_FSHOSTUSB | 801 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
800 OMAP3430_AUTO_HSOTGUSB | 802 OMAP3430_AUTO_HSOTGUSB_MASK |
801 OMAP3430_AUTO_SAD2D | 803 OMAP3430_AUTO_SAD2D_MASK |
802 OMAP3430_AUTO_SSI, 804 OMAP3430_AUTO_SSI_MASK,
803 CORE_MOD, CM_AUTOIDLE1); 805 CORE_MOD, CM_AUTOIDLE1);
804 806
805 cm_write_mod_reg( 807 cm_write_mod_reg(
806 OMAP3430_AUTO_PKA | 808 OMAP3430_AUTO_PKA_MASK |
807 OMAP3430_AUTO_AES1 | 809 OMAP3430_AUTO_AES1_MASK |
808 OMAP3430_AUTO_RNG | 810 OMAP3430_AUTO_RNG_MASK |
809 OMAP3430_AUTO_SHA11 | 811 OMAP3430_AUTO_SHA11_MASK |
810 OMAP3430_AUTO_DES1, 812 OMAP3430_AUTO_DES1_MASK,
811 CORE_MOD, CM_AUTOIDLE2); 813 CORE_MOD, CM_AUTOIDLE2);
812 814
813 if (omap_rev() > OMAP3430_REV_ES1_0) { 815 if (omap_rev() > OMAP3430_REV_ES1_0) {
814 cm_write_mod_reg( 816 cm_write_mod_reg(
815 OMAP3430_AUTO_MAD2D | 817 OMAP3430_AUTO_MAD2D_MASK |
816 OMAP3430ES2_AUTO_USBTLL, 818 OMAP3430ES2_AUTO_USBTLL_MASK,
817 CORE_MOD, CM_AUTOIDLE3); 819 CORE_MOD, CM_AUTOIDLE3);
818 } 820 }
819 821
820 cm_write_mod_reg( 822 cm_write_mod_reg(
821 OMAP3430_AUTO_WDT2 | 823 OMAP3430_AUTO_WDT2_MASK |
822 OMAP3430_AUTO_WDT1 | 824 OMAP3430_AUTO_WDT1_MASK |
823 OMAP3430_AUTO_GPIO1 | 825 OMAP3430_AUTO_GPIO1_MASK |
824 OMAP3430_AUTO_32KSYNC | 826 OMAP3430_AUTO_32KSYNC_MASK |
825 OMAP3430_AUTO_GPT12 | 827 OMAP3430_AUTO_GPT12_MASK |
826 OMAP3430_AUTO_GPT1 , 828 OMAP3430_AUTO_GPT1_MASK,
827 WKUP_MOD, CM_AUTOIDLE); 829 WKUP_MOD, CM_AUTOIDLE);
828 830
829 cm_write_mod_reg( 831 cm_write_mod_reg(
830 OMAP3430_AUTO_DSS, 832 OMAP3430_AUTO_DSS_MASK,
831 OMAP3430_DSS_MOD, 833 OMAP3430_DSS_MOD,
832 CM_AUTOIDLE); 834 CM_AUTOIDLE);
833 835
834 cm_write_mod_reg( 836 cm_write_mod_reg(
835 OMAP3430_AUTO_CAM, 837 OMAP3430_AUTO_CAM_MASK,
836 OMAP3430_CAM_MOD, 838 OMAP3430_CAM_MOD,
837 CM_AUTOIDLE); 839 CM_AUTOIDLE);
838 840
839 cm_write_mod_reg( 841 cm_write_mod_reg(
840 OMAP3430_AUTO_GPIO6 | 842 OMAP3430_AUTO_GPIO6_MASK |
841 OMAP3430_AUTO_GPIO5 | 843 OMAP3430_AUTO_GPIO5_MASK |
842 OMAP3430_AUTO_GPIO4 | 844 OMAP3430_AUTO_GPIO4_MASK |
843 OMAP3430_AUTO_GPIO3 | 845 OMAP3430_AUTO_GPIO3_MASK |
844 OMAP3430_AUTO_GPIO2 | 846 OMAP3430_AUTO_GPIO2_MASK |
845 OMAP3430_AUTO_WDT3 | 847 OMAP3430_AUTO_WDT3_MASK |
846 OMAP3430_AUTO_UART3 | 848 OMAP3430_AUTO_UART3_MASK |
847 OMAP3430_AUTO_GPT9 | 849 OMAP3430_AUTO_GPT9_MASK |
848 OMAP3430_AUTO_GPT8 | 850 OMAP3430_AUTO_GPT8_MASK |
849 OMAP3430_AUTO_GPT7 | 851 OMAP3430_AUTO_GPT7_MASK |
850 OMAP3430_AUTO_GPT6 | 852 OMAP3430_AUTO_GPT6_MASK |
851 OMAP3430_AUTO_GPT5 | 853 OMAP3430_AUTO_GPT5_MASK |
852 OMAP3430_AUTO_GPT4 | 854 OMAP3430_AUTO_GPT4_MASK |
853 OMAP3430_AUTO_GPT3 | 855 OMAP3430_AUTO_GPT3_MASK |
854 OMAP3430_AUTO_GPT2 | 856 OMAP3430_AUTO_GPT2_MASK |
855 OMAP3430_AUTO_MCBSP4 | 857 OMAP3430_AUTO_MCBSP4_MASK |
856 OMAP3430_AUTO_MCBSP3 | 858 OMAP3430_AUTO_MCBSP3_MASK |
857 OMAP3430_AUTO_MCBSP2, 859 OMAP3430_AUTO_MCBSP2_MASK,
858 OMAP3430_PER_MOD, 860 OMAP3430_PER_MOD,
859 CM_AUTOIDLE); 861 CM_AUTOIDLE);
860 862
861 if (omap_rev() > OMAP3430_REV_ES1_0) { 863 if (omap_rev() > OMAP3430_REV_ES1_0) {
862 cm_write_mod_reg( 864 cm_write_mod_reg(
863 OMAP3430ES2_AUTO_USBHOST, 865 OMAP3430ES2_AUTO_USBHOST_MASK,
864 OMAP3430ES2_USBHOST_MOD, 866 OMAP3430ES2_USBHOST_MOD,
865 CM_AUTOIDLE); 867 CM_AUTOIDLE);
866 } 868 }
@@ -895,7 +897,7 @@ static void __init prcm_setup_regs(void)
895 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 897 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
896 898
897 /* setup wakup source */ 899 /* setup wakup source */
898 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | 900 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1 |
899 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, 901 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
900 WKUP_MOD, PM_WKEN); 902 WKUP_MOD, PM_WKEN);
901 /* No need to write EN_IO, that is always enabled */ 903 /* No need to write EN_IO, that is always enabled */
@@ -904,11 +906,11 @@ static void __init prcm_setup_regs(void)
904 WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 906 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
905 /* For some reason IO doesn't generate wakeup event even if 907 /* For some reason IO doesn't generate wakeup event even if
906 * it is selected to mpu wakeup goup */ 908 * it is selected to mpu wakeup goup */
907 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, 909 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
908 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); 910 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
909 911
910 /* Enable PM_WKEN to support DSS LPR */ 912 /* Enable PM_WKEN to support DSS LPR */
911 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS, 913 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
912 OMAP3430_DSS_MOD, PM_WKEN); 914 OMAP3430_DSS_MOD, PM_WKEN);
913 915
914 /* Enable wakeups in PER */ 916 /* Enable wakeups in PER */
@@ -919,9 +921,9 @@ static void __init prcm_setup_regs(void)
919 OMAP3430_EN_MCBSP4, 921 OMAP3430_EN_MCBSP4,
920 OMAP3430_PER_MOD, PM_WKEN); 922 OMAP3430_PER_MOD, PM_WKEN);
921 /* and allow them to wake up MPU */ 923 /* and allow them to wake up MPU */
922 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | 924 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_EN_GPIO3 |
923 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | 925 OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_EN_GPIO5 |
924 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | 926 OMAP3430_GRPSEL_GPIO6_MASK | OMAP3430_EN_UART3 |
925 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | 927 OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 |
926 OMAP3430_EN_MCBSP4, 928 OMAP3430_EN_MCBSP4,
927 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 929 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 11:14:43 -0500