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authorAbhijit Pagare <abhijitpagare@ti.com>2010-01-26 22:12:53 -0500
committerPaul Walmsley <paul@pwsan.com>2010-01-26 22:12:53 -0500
commit84c0c39aec31a09571fc08a752a2f4da0fe9fcf2 (patch)
treecae08d44938c6df7f7bc740d2feea26086a192f4 /arch/arm/mach-omap2/pm-debug.c
parent3a759f09d7b9c6bbefffadd38fdc116125c49730 (diff)
ARM: OMAP4: PM: Make OMAP3 Clock-domain framework compatible for OMAP4.
Here the ".clkstctrl_reg" field is added to the clockdomain stucture as the module offsets for OMAP4 do not map one to one for powerdomains and clockdomains as it used to for OMAP3. Hence we need to use absolute addresses to access the control registers. Some of the clock domains have modules falling in the address space of PRM partition. Hence necessitating the use of absolute adresses. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm-debug.c')
-rw-r--r--arch/arm/mach-omap2/pm-debug.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 03dc845c82cb..5b6ae1e88e01 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -67,7 +67,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
67#if 0 67#if 0
68 /* MPU */ 68 /* MPU */
69 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET); 69 DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
70 DUMP_CM_MOD_REG(MPU_MOD, CM_CLKSTCTRL); 70 DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
71 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL); 71 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
72 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST); 72 DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
73 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP); 73 DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
@@ -103,7 +103,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
103 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST); 103 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
104 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE); 104 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
105 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL); 105 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
106 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSTCTRL); 106 DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
107 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL); 107 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
108 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST); 108 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
109 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL); 109 DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);