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authorTomi Valkeinen <tomi.valkeinen@ti.com>2012-06-13 04:24:38 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-06-13 04:24:38 -0400
commit289733ed456f7c1cbdb1f1ca58312f77c239953b (patch)
tree99bed0a5c21d0bdc5f6c10bc80a1ae8dbbd56be6 /arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
parentc3a21fc79b6bc097d8b0e47498903a649a111127 (diff)
parentcfaf025112d3856637ff34a767ef785ef5cf2ca9 (diff)
Merge tag 'v3.5-rc2'
Merge v3.5-rc2 to get latest device tree and dynamic debug changes.
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c3089
1 files changed, 1342 insertions, 1747 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index db86ce90c69f..b26d3c9bca16 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2,6 +2,7 @@
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley 6 * Paul Walmsley
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
@@ -38,491 +39,56 @@
38/* 39/*
39 * OMAP3xxx hardware module integration data 40 * OMAP3xxx hardware module integration data
40 * 41 *
41 * ALl of the data in this section should be autogeneratable from the 42 * All of the data in this section should be autogeneratable from the
42 * TI hardware database or other technical documentation. Data that 43 * TI hardware database or other technical documentation. Data that
43 * is driver-specific or driver-kernel integration-specific belongs 44 * is driver-specific or driver-kernel integration-specific belongs
44 * elsewhere. 45 * elsewhere.
45 */ 46 */
46 47
47static struct omap_hwmod omap3xxx_mpu_hwmod; 48/*
48static struct omap_hwmod omap3xxx_iva_hwmod; 49 * IP blocks
49static struct omap_hwmod omap3xxx_l3_main_hwmod; 50 */
50static struct omap_hwmod omap3xxx_l4_core_hwmod;
51static struct omap_hwmod omap3xxx_l4_per_hwmod;
52static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
53static struct omap_hwmod omap3430es1_dss_core_hwmod;
54static struct omap_hwmod omap3xxx_dss_core_hwmod;
55static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
56static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
57static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
58static struct omap_hwmod omap3xxx_dss_venc_hwmod;
59static struct omap_hwmod omap3xxx_i2c1_hwmod;
60static struct omap_hwmod omap3xxx_i2c2_hwmod;
61static struct omap_hwmod omap3xxx_i2c3_hwmod;
62static struct omap_hwmod omap3xxx_gpio1_hwmod;
63static struct omap_hwmod omap3xxx_gpio2_hwmod;
64static struct omap_hwmod omap3xxx_gpio3_hwmod;
65static struct omap_hwmod omap3xxx_gpio4_hwmod;
66static struct omap_hwmod omap3xxx_gpio5_hwmod;
67static struct omap_hwmod omap3xxx_gpio6_hwmod;
68static struct omap_hwmod omap34xx_sr1_hwmod;
69static struct omap_hwmod omap34xx_sr2_hwmod;
70static struct omap_hwmod omap34xx_mcspi1;
71static struct omap_hwmod omap34xx_mcspi2;
72static struct omap_hwmod omap34xx_mcspi3;
73static struct omap_hwmod omap34xx_mcspi4;
74static struct omap_hwmod omap3xxx_mmc1_hwmod;
75static struct omap_hwmod omap3xxx_mmc2_hwmod;
76static struct omap_hwmod omap3xxx_mmc3_hwmod;
77static struct omap_hwmod am35xx_usbhsotg_hwmod;
78
79static struct omap_hwmod omap3xxx_dma_system_hwmod;
80
81static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
89static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
90
91/* L3 -> L4_CORE interface */
92static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
93 .master = &omap3xxx_l3_main_hwmod,
94 .slave = &omap3xxx_l4_core_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96};
97
98/* L3 -> L4_PER interface */
99static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .master = &omap3xxx_l3_main_hwmod,
101 .slave = &omap3xxx_l4_per_hwmod,
102 .user = OCP_USER_MPU | OCP_USER_SDMA,
103};
104 51
105/* L3 taret configuration and error log registers */ 52/* L3 */
106static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 53static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
107 { .irq = INT_34XX_L3_DBG_IRQ }, 54 { .irq = INT_34XX_L3_DBG_IRQ },
108 { .irq = INT_34XX_L3_APP_IRQ }, 55 { .irq = INT_34XX_L3_APP_IRQ },
109 { .irq = -1 } 56 { .irq = -1 }
110}; 57};
111 58
112static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
113 {
114 .pa_start = 0x68000000,
115 .pa_end = 0x6800ffff,
116 .flags = ADDR_TYPE_RT,
117 },
118 { }
119};
120
121/* MPU -> L3 interface */
122static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
123 .master = &omap3xxx_mpu_hwmod,
124 .slave = &omap3xxx_l3_main_hwmod,
125 .addr = omap3xxx_l3_main_addrs,
126 .user = OCP_USER_MPU,
127};
128
129/* Slave interfaces on the L3 interconnect */
130static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
131 &omap3xxx_mpu__l3_main,
132};
133
134/* DSS -> l3 */
135static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
136 .master = &omap3xxx_dss_core_hwmod,
137 .slave = &omap3xxx_l3_main_hwmod,
138 .fw = {
139 .omap2 = {
140 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
141 .flags = OMAP_FIREWALL_L3,
142 }
143 },
144 .user = OCP_USER_MPU | OCP_USER_SDMA,
145};
146
147/* Master interfaces on the L3 interconnect */
148static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
149 &omap3xxx_l3_main__l4_core,
150 &omap3xxx_l3_main__l4_per,
151};
152
153/* L3 */
154static struct omap_hwmod omap3xxx_l3_main_hwmod = { 59static struct omap_hwmod omap3xxx_l3_main_hwmod = {
155 .name = "l3_main", 60 .name = "l3_main",
156 .class = &l3_hwmod_class, 61 .class = &l3_hwmod_class,
157 .mpu_irqs = omap3xxx_l3_main_irqs, 62 .mpu_irqs = omap3xxx_l3_main_irqs,
158 .masters = omap3xxx_l3_main_masters,
159 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
160 .slaves = omap3xxx_l3_main_slaves,
161 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
162 .flags = HWMOD_NO_IDLEST, 63 .flags = HWMOD_NO_IDLEST,
163}; 64};
164 65
165static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
166static struct omap_hwmod omap3xxx_uart1_hwmod;
167static struct omap_hwmod omap3xxx_uart2_hwmod;
168static struct omap_hwmod omap3xxx_uart3_hwmod;
169static struct omap_hwmod omap3xxx_uart4_hwmod;
170static struct omap_hwmod am35xx_uart4_hwmod;
171static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
172
173/* l3_core -> usbhsotg interface */
174static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
175 .master = &omap3xxx_usbhsotg_hwmod,
176 .slave = &omap3xxx_l3_main_hwmod,
177 .clk = "core_l3_ick",
178 .user = OCP_USER_MPU,
179};
180
181/* l3_core -> am35xx_usbhsotg interface */
182static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
183 .master = &am35xx_usbhsotg_hwmod,
184 .slave = &omap3xxx_l3_main_hwmod,
185 .clk = "core_l3_ick",
186 .user = OCP_USER_MPU,
187};
188/* L4_CORE -> L4_WKUP interface */
189static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190 .master = &omap3xxx_l4_core_hwmod,
191 .slave = &omap3xxx_l4_wkup_hwmod,
192 .user = OCP_USER_MPU | OCP_USER_SDMA,
193};
194
195/* L4 CORE -> MMC1 interface */
196static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
197 .master = &omap3xxx_l4_core_hwmod,
198 .slave = &omap3xxx_mmc1_hwmod,
199 .clk = "mmchs1_ick",
200 .addr = omap2430_mmc1_addr_space,
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202 .flags = OMAP_FIREWALL_L4
203};
204
205/* L4 CORE -> MMC2 interface */
206static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
207 .master = &omap3xxx_l4_core_hwmod,
208 .slave = &omap3xxx_mmc2_hwmod,
209 .clk = "mmchs2_ick",
210 .addr = omap2430_mmc2_addr_space,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
212 .flags = OMAP_FIREWALL_L4
213};
214
215/* L4 CORE -> MMC3 interface */
216static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
217 {
218 .pa_start = 0x480ad000,
219 .pa_end = 0x480ad1ff,
220 .flags = ADDR_TYPE_RT,
221 },
222 { }
223};
224
225static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
226 .master = &omap3xxx_l4_core_hwmod,
227 .slave = &omap3xxx_mmc3_hwmod,
228 .clk = "mmchs3_ick",
229 .addr = omap3xxx_mmc3_addr_space,
230 .user = OCP_USER_MPU | OCP_USER_SDMA,
231 .flags = OMAP_FIREWALL_L4
232};
233
234/* L4 CORE -> UART1 interface */
235static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
236 {
237 .pa_start = OMAP3_UART1_BASE,
238 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
239 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
240 },
241 { }
242};
243
244static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
245 .master = &omap3xxx_l4_core_hwmod,
246 .slave = &omap3xxx_uart1_hwmod,
247 .clk = "uart1_ick",
248 .addr = omap3xxx_uart1_addr_space,
249 .user = OCP_USER_MPU | OCP_USER_SDMA,
250};
251
252/* L4 CORE -> UART2 interface */
253static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
254 {
255 .pa_start = OMAP3_UART2_BASE,
256 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
257 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
258 },
259 { }
260};
261
262static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
263 .master = &omap3xxx_l4_core_hwmod,
264 .slave = &omap3xxx_uart2_hwmod,
265 .clk = "uart2_ick",
266 .addr = omap3xxx_uart2_addr_space,
267 .user = OCP_USER_MPU | OCP_USER_SDMA,
268};
269
270/* L4 PER -> UART3 interface */
271static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
272 {
273 .pa_start = OMAP3_UART3_BASE,
274 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
275 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
276 },
277 { }
278};
279
280static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
281 .master = &omap3xxx_l4_per_hwmod,
282 .slave = &omap3xxx_uart3_hwmod,
283 .clk = "uart3_ick",
284 .addr = omap3xxx_uart3_addr_space,
285 .user = OCP_USER_MPU | OCP_USER_SDMA,
286};
287
288/* L4 PER -> UART4 interface */
289static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
290 {
291 .pa_start = OMAP3_UART4_BASE,
292 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
293 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
294 },
295 { }
296};
297
298static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
299 .master = &omap3xxx_l4_per_hwmod,
300 .slave = &omap3xxx_uart4_hwmod,
301 .clk = "uart4_ick",
302 .addr = omap3xxx_uart4_addr_space,
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304};
305
306/* AM35xx: L4 CORE -> UART4 interface */
307static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
308 {
309 .pa_start = OMAP3_UART4_AM35XX_BASE,
310 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
311 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
312 },
313};
314
315static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
316 .master = &omap3xxx_l4_core_hwmod,
317 .slave = &am35xx_uart4_hwmod,
318 .clk = "uart4_ick",
319 .addr = am35xx_uart4_addr_space,
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321};
322
323/* L4 CORE -> I2C1 interface */
324static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
325 .master = &omap3xxx_l4_core_hwmod,
326 .slave = &omap3xxx_i2c1_hwmod,
327 .clk = "i2c1_ick",
328 .addr = omap2_i2c1_addr_space,
329 .fw = {
330 .omap2 = {
331 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
332 .l4_prot_group = 7,
333 .flags = OMAP_FIREWALL_L4,
334 }
335 },
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337};
338
339/* L4 CORE -> I2C2 interface */
340static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
341 .master = &omap3xxx_l4_core_hwmod,
342 .slave = &omap3xxx_i2c2_hwmod,
343 .clk = "i2c2_ick",
344 .addr = omap2_i2c2_addr_space,
345 .fw = {
346 .omap2 = {
347 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
348 .l4_prot_group = 7,
349 .flags = OMAP_FIREWALL_L4,
350 }
351 },
352 .user = OCP_USER_MPU | OCP_USER_SDMA,
353};
354
355/* L4 CORE -> I2C3 interface */
356static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
357 {
358 .pa_start = 0x48060000,
359 .pa_end = 0x48060000 + SZ_128 - 1,
360 .flags = ADDR_TYPE_RT,
361 },
362 { }
363};
364
365static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
366 .master = &omap3xxx_l4_core_hwmod,
367 .slave = &omap3xxx_i2c3_hwmod,
368 .clk = "i2c3_ick",
369 .addr = omap3xxx_i2c3_addr_space,
370 .fw = {
371 .omap2 = {
372 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
373 .l4_prot_group = 7,
374 .flags = OMAP_FIREWALL_L4,
375 }
376 },
377 .user = OCP_USER_MPU | OCP_USER_SDMA,
378};
379
380static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
381 { .irq = 18},
382 { .irq = -1 }
383};
384
385static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
386 { .irq = 19},
387 { .irq = -1 }
388};
389
390/* L4 CORE -> SR1 interface */
391static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
392 {
393 .pa_start = OMAP34XX_SR1_BASE,
394 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
395 .flags = ADDR_TYPE_RT,
396 },
397 { }
398};
399
400static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
401 .master = &omap3xxx_l4_core_hwmod,
402 .slave = &omap34xx_sr1_hwmod,
403 .clk = "sr_l4_ick",
404 .addr = omap3_sr1_addr_space,
405 .user = OCP_USER_MPU,
406};
407
408/* L4 CORE -> SR1 interface */
409static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
410 {
411 .pa_start = OMAP34XX_SR2_BASE,
412 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
413 .flags = ADDR_TYPE_RT,
414 },
415 { }
416};
417
418static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
419 .master = &omap3xxx_l4_core_hwmod,
420 .slave = &omap34xx_sr2_hwmod,
421 .clk = "sr_l4_ick",
422 .addr = omap3_sr2_addr_space,
423 .user = OCP_USER_MPU,
424};
425
426/*
427* usbhsotg interface data
428*/
429
430static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
431 {
432 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
433 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
434 .flags = ADDR_TYPE_RT
435 },
436 { }
437};
438
439/* l4_core -> usbhsotg */
440static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
441 .master = &omap3xxx_l4_core_hwmod,
442 .slave = &omap3xxx_usbhsotg_hwmod,
443 .clk = "l4_ick",
444 .addr = omap3xxx_usbhsotg_addrs,
445 .user = OCP_USER_MPU,
446};
447
448static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
449 &omap3xxx_usbhsotg__l3,
450};
451
452static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
453 &omap3xxx_l4_core__usbhsotg,
454};
455
456static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
457 {
458 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
459 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
460 .flags = ADDR_TYPE_RT
461 },
462 { }
463};
464
465/* l4_core -> usbhsotg */
466static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
467 .master = &omap3xxx_l4_core_hwmod,
468 .slave = &am35xx_usbhsotg_hwmod,
469 .clk = "l4_ick",
470 .addr = am35xx_usbhsotg_addrs,
471 .user = OCP_USER_MPU,
472};
473
474static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
475 &am35xx_usbhsotg__l3,
476};
477
478static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
479 &am35xx_l4_core__usbhsotg,
480};
481/* Slave interfaces on the L4_CORE interconnect */
482static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
483 &omap3xxx_l3_main__l4_core,
484};
485
486/* L4 CORE */ 66/* L4 CORE */
487static struct omap_hwmod omap3xxx_l4_core_hwmod = { 67static struct omap_hwmod omap3xxx_l4_core_hwmod = {
488 .name = "l4_core", 68 .name = "l4_core",
489 .class = &l4_hwmod_class, 69 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_core_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
492 .flags = HWMOD_NO_IDLEST, 70 .flags = HWMOD_NO_IDLEST,
493}; 71};
494 72
495/* Slave interfaces on the L4_PER interconnect */
496static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
497 &omap3xxx_l3_main__l4_per,
498};
499
500/* L4 PER */ 73/* L4 PER */
501static struct omap_hwmod omap3xxx_l4_per_hwmod = { 74static struct omap_hwmod omap3xxx_l4_per_hwmod = {
502 .name = "l4_per", 75 .name = "l4_per",
503 .class = &l4_hwmod_class, 76 .class = &l4_hwmod_class,
504 .slaves = omap3xxx_l4_per_slaves,
505 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
506 .flags = HWMOD_NO_IDLEST, 77 .flags = HWMOD_NO_IDLEST,
507}; 78};
508 79
509/* Slave interfaces on the L4_WKUP interconnect */
510static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
511 &omap3xxx_l4_core__l4_wkup,
512};
513
514/* L4 WKUP */ 80/* L4 WKUP */
515static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 81static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
516 .name = "l4_wkup", 82 .name = "l4_wkup",
517 .class = &l4_hwmod_class, 83 .class = &l4_hwmod_class,
518 .slaves = omap3xxx_l4_wkup_slaves,
519 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
520 .flags = HWMOD_NO_IDLEST, 84 .flags = HWMOD_NO_IDLEST,
521}; 85};
522 86
523/* Master interfaces on the MPU device */ 87/* L4 SEC */
524static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { 88static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
525 &omap3xxx_mpu__l3_main, 89 .name = "l4_sec",
90 .class = &l4_hwmod_class,
91 .flags = HWMOD_NO_IDLEST,
526}; 92};
527 93
528/* MPU */ 94/* MPU */
@@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
530 .name = "mpu", 96 .name = "mpu",
531 .class = &mpu_hwmod_class, 97 .class = &mpu_hwmod_class,
532 .main_clk = "arm_fck", 98 .main_clk = "arm_fck",
533 .masters = omap3xxx_mpu_masters,
534 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
535}; 99};
536 100
537/* 101/* IVA2 (IVA2) */
538 * IVA2_2 interface data 102static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
539 */ 103 { .name = "logic", .rst_shift = 0 },
540 104 { .name = "seq0", .rst_shift = 1 },
541/* IVA2 <- L3 interface */ 105 { .name = "seq1", .rst_shift = 2 },
542static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
543 .master = &omap3xxx_l3_main_hwmod,
544 .slave = &omap3xxx_iva_hwmod,
545 .clk = "iva2_ck",
546 .user = OCP_USER_MPU | OCP_USER_SDMA,
547}; 106};
548 107
549static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
550 &omap3xxx_l3__iva,
551};
552
553/*
554 * IVA2 (IVA2)
555 */
556
557static struct omap_hwmod omap3xxx_iva_hwmod = { 108static struct omap_hwmod omap3xxx_iva_hwmod = {
558 .name = "iva", 109 .name = "iva",
559 .class = &iva_hwmod_class, 110 .class = &iva_hwmod_class,
560 .masters = omap3xxx_iva_masters, 111 .clkdm_name = "iva2_clkdm",
561 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), 112 .rst_lines = omap3xxx_iva_resets,
113 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
114 .main_clk = "iva2_ck",
562}; 115};
563 116
564/* timer class */ 117/* timer class */
@@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
597 150
598/* secure timers dev attribute */ 151/* secure timers dev attribute */
599static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 152static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
600 .timer_capability = OMAP_TIMER_SECURE, 153 .timer_capability = OMAP_TIMER_SECURE,
601}; 154};
602 155
603/* always-on timers dev attribute */ 156/* always-on timers dev attribute */
604static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 157static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
605 .timer_capability = OMAP_TIMER_ALWON, 158 .timer_capability = OMAP_TIMER_ALWON,
606}; 159};
607 160
608/* pwm timers dev attribute */ 161/* pwm timers dev attribute */
609static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 162static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
610 .timer_capability = OMAP_TIMER_HAS_PWM, 163 .timer_capability = OMAP_TIMER_HAS_PWM,
611}; 164};
612 165
613/* timer1 */ 166/* timer1 */
614static struct omap_hwmod omap3xxx_timer1_hwmod;
615
616static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
617 {
618 .pa_start = 0x48318000,
619 .pa_end = 0x48318000 + SZ_1K - 1,
620 .flags = ADDR_TYPE_RT
621 },
622 { }
623};
624
625/* l4_wkup -> timer1 */
626static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
627 .master = &omap3xxx_l4_wkup_hwmod,
628 .slave = &omap3xxx_timer1_hwmod,
629 .clk = "gpt1_ick",
630 .addr = omap3xxx_timer1_addrs,
631 .user = OCP_USER_MPU | OCP_USER_SDMA,
632};
633
634/* timer1 slave port */
635static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
636 &omap3xxx_l4_wkup__timer1,
637};
638
639/* timer1 hwmod */
640static struct omap_hwmod omap3xxx_timer1_hwmod = { 167static struct omap_hwmod omap3xxx_timer1_hwmod = {
641 .name = "timer1", 168 .name = "timer1",
642 .mpu_irqs = omap2_timer1_mpu_irqs, 169 .mpu_irqs = omap2_timer1_mpu_irqs,
@@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
651 }, 178 },
652 }, 179 },
653 .dev_attr = &capability_alwon_dev_attr, 180 .dev_attr = &capability_alwon_dev_attr,
654 .slaves = omap3xxx_timer1_slaves,
655 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
656 .class = &omap3xxx_timer_1ms_hwmod_class, 181 .class = &omap3xxx_timer_1ms_hwmod_class,
657}; 182};
658 183
659/* timer2 */ 184/* timer2 */
660static struct omap_hwmod omap3xxx_timer2_hwmod;
661
662static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
663 {
664 .pa_start = 0x49032000,
665 .pa_end = 0x49032000 + SZ_1K - 1,
666 .flags = ADDR_TYPE_RT
667 },
668 { }
669};
670
671/* l4_per -> timer2 */
672static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
673 .master = &omap3xxx_l4_per_hwmod,
674 .slave = &omap3xxx_timer2_hwmod,
675 .clk = "gpt2_ick",
676 .addr = omap3xxx_timer2_addrs,
677 .user = OCP_USER_MPU | OCP_USER_SDMA,
678};
679
680/* timer2 slave port */
681static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
682 &omap3xxx_l4_per__timer2,
683};
684
685/* timer2 hwmod */
686static struct omap_hwmod omap3xxx_timer2_hwmod = { 185static struct omap_hwmod omap3xxx_timer2_hwmod = {
687 .name = "timer2", 186 .name = "timer2",
688 .mpu_irqs = omap2_timer2_mpu_irqs, 187 .mpu_irqs = omap2_timer2_mpu_irqs,
@@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
697 }, 196 },
698 }, 197 },
699 .dev_attr = &capability_alwon_dev_attr, 198 .dev_attr = &capability_alwon_dev_attr,
700 .slaves = omap3xxx_timer2_slaves,
701 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
702 .class = &omap3xxx_timer_1ms_hwmod_class, 199 .class = &omap3xxx_timer_1ms_hwmod_class,
703}; 200};
704 201
705/* timer3 */ 202/* timer3 */
706static struct omap_hwmod omap3xxx_timer3_hwmod;
707
708static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
709 {
710 .pa_start = 0x49034000,
711 .pa_end = 0x49034000 + SZ_1K - 1,
712 .flags = ADDR_TYPE_RT
713 },
714 { }
715};
716
717/* l4_per -> timer3 */
718static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
719 .master = &omap3xxx_l4_per_hwmod,
720 .slave = &omap3xxx_timer3_hwmod,
721 .clk = "gpt3_ick",
722 .addr = omap3xxx_timer3_addrs,
723 .user = OCP_USER_MPU | OCP_USER_SDMA,
724};
725
726/* timer3 slave port */
727static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
728 &omap3xxx_l4_per__timer3,
729};
730
731/* timer3 hwmod */
732static struct omap_hwmod omap3xxx_timer3_hwmod = { 203static struct omap_hwmod omap3xxx_timer3_hwmod = {
733 .name = "timer3", 204 .name = "timer3",
734 .mpu_irqs = omap2_timer3_mpu_irqs, 205 .mpu_irqs = omap2_timer3_mpu_irqs,
@@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 }, 214 },
744 }, 215 },
745 .dev_attr = &capability_alwon_dev_attr, 216 .dev_attr = &capability_alwon_dev_attr,
746 .slaves = omap3xxx_timer3_slaves,
747 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
748 .class = &omap3xxx_timer_hwmod_class, 217 .class = &omap3xxx_timer_hwmod_class,
749}; 218};
750 219
751/* timer4 */ 220/* timer4 */
752static struct omap_hwmod omap3xxx_timer4_hwmod;
753
754static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
755 {
756 .pa_start = 0x49036000,
757 .pa_end = 0x49036000 + SZ_1K - 1,
758 .flags = ADDR_TYPE_RT
759 },
760 { }
761};
762
763/* l4_per -> timer4 */
764static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
765 .master = &omap3xxx_l4_per_hwmod,
766 .slave = &omap3xxx_timer4_hwmod,
767 .clk = "gpt4_ick",
768 .addr = omap3xxx_timer4_addrs,
769 .user = OCP_USER_MPU | OCP_USER_SDMA,
770};
771
772/* timer4 slave port */
773static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
774 &omap3xxx_l4_per__timer4,
775};
776
777/* timer4 hwmod */
778static struct omap_hwmod omap3xxx_timer4_hwmod = { 221static struct omap_hwmod omap3xxx_timer4_hwmod = {
779 .name = "timer4", 222 .name = "timer4",
780 .mpu_irqs = omap2_timer4_mpu_irqs, 223 .mpu_irqs = omap2_timer4_mpu_irqs,
@@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
789 }, 232 },
790 }, 233 },
791 .dev_attr = &capability_alwon_dev_attr, 234 .dev_attr = &capability_alwon_dev_attr,
792 .slaves = omap3xxx_timer4_slaves,
793 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
794 .class = &omap3xxx_timer_hwmod_class, 235 .class = &omap3xxx_timer_hwmod_class,
795}; 236};
796 237
797/* timer5 */ 238/* timer5 */
798static struct omap_hwmod omap3xxx_timer5_hwmod;
799
800static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
801 {
802 .pa_start = 0x49038000,
803 .pa_end = 0x49038000 + SZ_1K - 1,
804 .flags = ADDR_TYPE_RT
805 },
806 { }
807};
808
809/* l4_per -> timer5 */
810static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
811 .master = &omap3xxx_l4_per_hwmod,
812 .slave = &omap3xxx_timer5_hwmod,
813 .clk = "gpt5_ick",
814 .addr = omap3xxx_timer5_addrs,
815 .user = OCP_USER_MPU | OCP_USER_SDMA,
816};
817
818/* timer5 slave port */
819static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
820 &omap3xxx_l4_per__timer5,
821};
822
823/* timer5 hwmod */
824static struct omap_hwmod omap3xxx_timer5_hwmod = { 239static struct omap_hwmod omap3xxx_timer5_hwmod = {
825 .name = "timer5", 240 .name = "timer5",
826 .mpu_irqs = omap2_timer5_mpu_irqs, 241 .mpu_irqs = omap2_timer5_mpu_irqs,
@@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
835 }, 250 },
836 }, 251 },
837 .dev_attr = &capability_alwon_dev_attr, 252 .dev_attr = &capability_alwon_dev_attr,
838 .slaves = omap3xxx_timer5_slaves,
839 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
840 .class = &omap3xxx_timer_hwmod_class, 253 .class = &omap3xxx_timer_hwmod_class,
841}; 254};
842 255
843/* timer6 */ 256/* timer6 */
844static struct omap_hwmod omap3xxx_timer6_hwmod;
845
846static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
847 {
848 .pa_start = 0x4903A000,
849 .pa_end = 0x4903A000 + SZ_1K - 1,
850 .flags = ADDR_TYPE_RT
851 },
852 { }
853};
854
855/* l4_per -> timer6 */
856static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
857 .master = &omap3xxx_l4_per_hwmod,
858 .slave = &omap3xxx_timer6_hwmod,
859 .clk = "gpt6_ick",
860 .addr = omap3xxx_timer6_addrs,
861 .user = OCP_USER_MPU | OCP_USER_SDMA,
862};
863
864/* timer6 slave port */
865static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
866 &omap3xxx_l4_per__timer6,
867};
868
869/* timer6 hwmod */
870static struct omap_hwmod omap3xxx_timer6_hwmod = { 257static struct omap_hwmod omap3xxx_timer6_hwmod = {
871 .name = "timer6", 258 .name = "timer6",
872 .mpu_irqs = omap2_timer6_mpu_irqs, 259 .mpu_irqs = omap2_timer6_mpu_irqs,
@@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
881 }, 268 },
882 }, 269 },
883 .dev_attr = &capability_alwon_dev_attr, 270 .dev_attr = &capability_alwon_dev_attr,
884 .slaves = omap3xxx_timer6_slaves,
885 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
886 .class = &omap3xxx_timer_hwmod_class, 271 .class = &omap3xxx_timer_hwmod_class,
887}; 272};
888 273
889/* timer7 */ 274/* timer7 */
890static struct omap_hwmod omap3xxx_timer7_hwmod;
891
892static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
893 {
894 .pa_start = 0x4903C000,
895 .pa_end = 0x4903C000 + SZ_1K - 1,
896 .flags = ADDR_TYPE_RT
897 },
898 { }
899};
900
901/* l4_per -> timer7 */
902static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
903 .master = &omap3xxx_l4_per_hwmod,
904 .slave = &omap3xxx_timer7_hwmod,
905 .clk = "gpt7_ick",
906 .addr = omap3xxx_timer7_addrs,
907 .user = OCP_USER_MPU | OCP_USER_SDMA,
908};
909
910/* timer7 slave port */
911static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
912 &omap3xxx_l4_per__timer7,
913};
914
915/* timer7 hwmod */
916static struct omap_hwmod omap3xxx_timer7_hwmod = { 275static struct omap_hwmod omap3xxx_timer7_hwmod = {
917 .name = "timer7", 276 .name = "timer7",
918 .mpu_irqs = omap2_timer7_mpu_irqs, 277 .mpu_irqs = omap2_timer7_mpu_irqs,
@@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
927 }, 286 },
928 }, 287 },
929 .dev_attr = &capability_alwon_dev_attr, 288 .dev_attr = &capability_alwon_dev_attr,
930 .slaves = omap3xxx_timer7_slaves,
931 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
932 .class = &omap3xxx_timer_hwmod_class, 289 .class = &omap3xxx_timer_hwmod_class,
933}; 290};
934 291
935/* timer8 */ 292/* timer8 */
936static struct omap_hwmod omap3xxx_timer8_hwmod;
937
938static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
939 {
940 .pa_start = 0x4903E000,
941 .pa_end = 0x4903E000 + SZ_1K - 1,
942 .flags = ADDR_TYPE_RT
943 },
944 { }
945};
946
947/* l4_per -> timer8 */
948static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
949 .master = &omap3xxx_l4_per_hwmod,
950 .slave = &omap3xxx_timer8_hwmod,
951 .clk = "gpt8_ick",
952 .addr = omap3xxx_timer8_addrs,
953 .user = OCP_USER_MPU | OCP_USER_SDMA,
954};
955
956/* timer8 slave port */
957static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
958 &omap3xxx_l4_per__timer8,
959};
960
961/* timer8 hwmod */
962static struct omap_hwmod omap3xxx_timer8_hwmod = { 293static struct omap_hwmod omap3xxx_timer8_hwmod = {
963 .name = "timer8", 294 .name = "timer8",
964 .mpu_irqs = omap2_timer8_mpu_irqs, 295 .mpu_irqs = omap2_timer8_mpu_irqs,
@@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
973 }, 304 },
974 }, 305 },
975 .dev_attr = &capability_pwm_dev_attr, 306 .dev_attr = &capability_pwm_dev_attr,
976 .slaves = omap3xxx_timer8_slaves,
977 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
978 .class = &omap3xxx_timer_hwmod_class, 307 .class = &omap3xxx_timer_hwmod_class,
979}; 308};
980 309
981/* timer9 */ 310/* timer9 */
982static struct omap_hwmod omap3xxx_timer9_hwmod;
983
984static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
985 {
986 .pa_start = 0x49040000,
987 .pa_end = 0x49040000 + SZ_1K - 1,
988 .flags = ADDR_TYPE_RT
989 },
990 { }
991};
992
993/* l4_per -> timer9 */
994static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
995 .master = &omap3xxx_l4_per_hwmod,
996 .slave = &omap3xxx_timer9_hwmod,
997 .clk = "gpt9_ick",
998 .addr = omap3xxx_timer9_addrs,
999 .user = OCP_USER_MPU | OCP_USER_SDMA,
1000};
1001
1002/* timer9 slave port */
1003static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1004 &omap3xxx_l4_per__timer9,
1005};
1006
1007/* timer9 hwmod */
1008static struct omap_hwmod omap3xxx_timer9_hwmod = { 311static struct omap_hwmod omap3xxx_timer9_hwmod = {
1009 .name = "timer9", 312 .name = "timer9",
1010 .mpu_irqs = omap2_timer9_mpu_irqs, 313 .mpu_irqs = omap2_timer9_mpu_irqs,
@@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1019 }, 322 },
1020 }, 323 },
1021 .dev_attr = &capability_pwm_dev_attr, 324 .dev_attr = &capability_pwm_dev_attr,
1022 .slaves = omap3xxx_timer9_slaves,
1023 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
1024 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
1025}; 326};
1026 327
1027/* timer10 */ 328/* timer10 */
1028static struct omap_hwmod omap3xxx_timer10_hwmod;
1029
1030/* l4_core -> timer10 */
1031static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1032 .master = &omap3xxx_l4_core_hwmod,
1033 .slave = &omap3xxx_timer10_hwmod,
1034 .clk = "gpt10_ick",
1035 .addr = omap2_timer10_addrs,
1036 .user = OCP_USER_MPU | OCP_USER_SDMA,
1037};
1038
1039/* timer10 slave port */
1040static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1041 &omap3xxx_l4_core__timer10,
1042};
1043
1044/* timer10 hwmod */
1045static struct omap_hwmod omap3xxx_timer10_hwmod = { 329static struct omap_hwmod omap3xxx_timer10_hwmod = {
1046 .name = "timer10", 330 .name = "timer10",
1047 .mpu_irqs = omap2_timer10_mpu_irqs, 331 .mpu_irqs = omap2_timer10_mpu_irqs,
@@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1056 }, 340 },
1057 }, 341 },
1058 .dev_attr = &capability_pwm_dev_attr, 342 .dev_attr = &capability_pwm_dev_attr,
1059 .slaves = omap3xxx_timer10_slaves,
1060 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1061 .class = &omap3xxx_timer_1ms_hwmod_class, 343 .class = &omap3xxx_timer_1ms_hwmod_class,
1062}; 344};
1063 345
1064/* timer11 */ 346/* timer11 */
1065static struct omap_hwmod omap3xxx_timer11_hwmod;
1066
1067/* l4_core -> timer11 */
1068static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1069 .master = &omap3xxx_l4_core_hwmod,
1070 .slave = &omap3xxx_timer11_hwmod,
1071 .clk = "gpt11_ick",
1072 .addr = omap2_timer11_addrs,
1073 .user = OCP_USER_MPU | OCP_USER_SDMA,
1074};
1075
1076/* timer11 slave port */
1077static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1078 &omap3xxx_l4_core__timer11,
1079};
1080
1081/* timer11 hwmod */
1082static struct omap_hwmod omap3xxx_timer11_hwmod = { 347static struct omap_hwmod omap3xxx_timer11_hwmod = {
1083 .name = "timer11", 348 .name = "timer11",
1084 .mpu_irqs = omap2_timer11_mpu_irqs, 349 .mpu_irqs = omap2_timer11_mpu_irqs,
@@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1093 }, 358 },
1094 }, 359 },
1095 .dev_attr = &capability_pwm_dev_attr, 360 .dev_attr = &capability_pwm_dev_attr,
1096 .slaves = omap3xxx_timer11_slaves,
1097 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1098 .class = &omap3xxx_timer_hwmod_class, 361 .class = &omap3xxx_timer_hwmod_class,
1099}; 362};
1100 363
1101/* timer12*/ 364/* timer12 */
1102static struct omap_hwmod omap3xxx_timer12_hwmod;
1103static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 365static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1104 { .irq = 95, }, 366 { .irq = 95, },
1105 { .irq = -1 } 367 { .irq = -1 }
1106}; 368};
1107 369
1108static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1109 {
1110 .pa_start = 0x48304000,
1111 .pa_end = 0x48304000 + SZ_1K - 1,
1112 .flags = ADDR_TYPE_RT
1113 },
1114 { }
1115};
1116
1117/* l4_core -> timer12 */
1118static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1119 .master = &omap3xxx_l4_core_hwmod,
1120 .slave = &omap3xxx_timer12_hwmod,
1121 .clk = "gpt12_ick",
1122 .addr = omap3xxx_timer12_addrs,
1123 .user = OCP_USER_MPU | OCP_USER_SDMA,
1124};
1125
1126/* timer12 slave port */
1127static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1128 &omap3xxx_l4_core__timer12,
1129};
1130
1131/* timer12 hwmod */
1132static struct omap_hwmod omap3xxx_timer12_hwmod = { 370static struct omap_hwmod omap3xxx_timer12_hwmod = {
1133 .name = "timer12", 371 .name = "timer12",
1134 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 372 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
@@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
1143 }, 381 },
1144 }, 382 },
1145 .dev_attr = &capability_secure_dev_attr, 383 .dev_attr = &capability_secure_dev_attr,
1146 .slaves = omap3xxx_timer12_slaves,
1147 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1148 .class = &omap3xxx_timer_hwmod_class, 384 .class = &omap3xxx_timer_hwmod_class,
1149}; 385};
1150 386
1151/* l4_wkup -> wd_timer2 */
1152static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1153 {
1154 .pa_start = 0x48314000,
1155 .pa_end = 0x4831407f,
1156 .flags = ADDR_TYPE_RT
1157 },
1158 { }
1159};
1160
1161static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1162 .master = &omap3xxx_l4_wkup_hwmod,
1163 .slave = &omap3xxx_wd_timer2_hwmod,
1164 .clk = "wdt2_ick",
1165 .addr = omap3xxx_wd_timer2_addrs,
1166 .user = OCP_USER_MPU | OCP_USER_SDMA,
1167};
1168
1169/* 387/*
1170 * 'wd_timer' class 388 * 'wd_timer' class
1171 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 389 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1200,12 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
1200static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 418static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1201 .name = "wd_timer", 419 .name = "wd_timer",
1202 .sysc = &omap3xxx_wd_timer_sysc, 420 .sysc = &omap3xxx_wd_timer_sysc,
1203 .pre_shutdown = &omap2_wd_timer_disable 421 .pre_shutdown = &omap2_wd_timer_disable,
1204}; 422 .reset = &omap2_wd_timer_reset,
1205
1206/* wd_timer2 */
1207static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1208 &omap3xxx_l4_wkup__wd_timer2,
1209}; 423};
1210 424
1211static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 425static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
@@ -1221,8 +435,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1221 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 435 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1222 }, 436 },
1223 }, 437 },
1224 .slaves = omap3xxx_wd_timer2_slaves,
1225 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1226 /* 438 /*
1227 * XXX: Use software supervised mode, HW supervised smartidle seems to 439 * XXX: Use software supervised mode, HW supervised smartidle seems to
1228 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 440 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1231,11 +443,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1231}; 443};
1232 444
1233/* UART1 */ 445/* UART1 */
1234
1235static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1236 &omap3_l4_core__uart1,
1237};
1238
1239static struct omap_hwmod omap3xxx_uart1_hwmod = { 446static struct omap_hwmod omap3xxx_uart1_hwmod = {
1240 .name = "uart1", 447 .name = "uart1",
1241 .mpu_irqs = omap2_uart1_mpu_irqs, 448 .mpu_irqs = omap2_uart1_mpu_irqs,
@@ -1250,17 +457,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1250 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 457 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1251 }, 458 },
1252 }, 459 },
1253 .slaves = omap3xxx_uart1_slaves,
1254 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1255 .class = &omap2_uart_class, 460 .class = &omap2_uart_class,
1256}; 461};
1257 462
1258/* UART2 */ 463/* UART2 */
1259
1260static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1261 &omap3_l4_core__uart2,
1262};
1263
1264static struct omap_hwmod omap3xxx_uart2_hwmod = { 464static struct omap_hwmod omap3xxx_uart2_hwmod = {
1265 .name = "uart2", 465 .name = "uart2",
1266 .mpu_irqs = omap2_uart2_mpu_irqs, 466 .mpu_irqs = omap2_uart2_mpu_irqs,
@@ -1275,17 +475,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1275 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 475 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1276 }, 476 },
1277 }, 477 },
1278 .slaves = omap3xxx_uart2_slaves,
1279 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1280 .class = &omap2_uart_class, 478 .class = &omap2_uart_class,
1281}; 479};
1282 480
1283/* UART3 */ 481/* UART3 */
1284
1285static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1286 &omap3_l4_per__uart3,
1287};
1288
1289static struct omap_hwmod omap3xxx_uart3_hwmod = { 482static struct omap_hwmod omap3xxx_uart3_hwmod = {
1290 .name = "uart3", 483 .name = "uart3",
1291 .mpu_irqs = omap2_uart3_mpu_irqs, 484 .mpu_irqs = omap2_uart3_mpu_irqs,
@@ -1300,13 +493,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1300 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 493 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301 }, 494 },
1302 }, 495 },
1303 .slaves = omap3xxx_uart3_slaves,
1304 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1305 .class = &omap2_uart_class, 496 .class = &omap2_uart_class,
1306}; 497};
1307 498
1308/* UART4 */ 499/* UART4 */
1309
1310static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 500static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1311 { .irq = INT_36XX_UART4_IRQ, }, 501 { .irq = INT_36XX_UART4_IRQ, },
1312 { .irq = -1 } 502 { .irq = -1 }
@@ -1318,11 +508,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1318 { .dma_req = -1 } 508 { .dma_req = -1 }
1319}; 509};
1320 510
1321static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 511static struct omap_hwmod omap36xx_uart4_hwmod = {
1322 &omap3_l4_per__uart4,
1323};
1324
1325static struct omap_hwmod omap3xxx_uart4_hwmod = {
1326 .name = "uart4", 512 .name = "uart4",
1327 .mpu_irqs = uart4_mpu_irqs, 513 .mpu_irqs = uart4_mpu_irqs,
1328 .sdma_reqs = uart4_sdma_reqs, 514 .sdma_reqs = uart4_sdma_reqs,
@@ -1336,8 +522,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1336 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 522 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1337 }, 523 },
1338 }, 524 },
1339 .slaves = omap3xxx_uart4_slaves,
1340 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1341 .class = &omap2_uart_class, 525 .class = &omap2_uart_class,
1342}; 526};
1343 527
@@ -1350,16 +534,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
1350 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 534 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
1351}; 535};
1352 536
1353static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
1354 &am35xx_l4_core__uart4,
1355};
1356
1357static struct omap_hwmod am35xx_uart4_hwmod = { 537static struct omap_hwmod am35xx_uart4_hwmod = {
1358 .name = "uart4", 538 .name = "uart4",
1359 .mpu_irqs = am35xx_uart4_mpu_irqs, 539 .mpu_irqs = am35xx_uart4_mpu_irqs,
1360 .sdma_reqs = am35xx_uart4_sdma_reqs, 540 .sdma_reqs = am35xx_uart4_sdma_reqs,
1361 .main_clk = "uart4_fck", 541 .main_clk = "uart4_fck",
1362 .prcm = { 542 .prcm = {
1363 .omap2 = { 543 .omap2 = {
1364 .module_offs = CORE_MOD, 544 .module_offs = CORE_MOD,
1365 .prcm_reg_id = 1, 545 .prcm_reg_id = 1,
@@ -1368,12 +548,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
1368 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, 548 .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
1369 }, 549 },
1370 }, 550 },
1371 .slaves = am35xx_uart4_slaves, 551 .class = &omap2_uart_class,
1372 .slaves_cnt = ARRAY_SIZE(am35xx_uart4_slaves),
1373 .class = &omap2_uart_class,
1374}; 552};
1375 553
1376
1377static struct omap_hwmod_class i2c_class = { 554static struct omap_hwmod_class i2c_class = {
1378 .name = "i2c", 555 .name = "i2c",
1379 .sysc = &i2c_sysc, 556 .sysc = &i2c_sysc,
@@ -1388,51 +565,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1388}; 565};
1389 566
1390/* dss */ 567/* dss */
1391/* dss master ports */
1392static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1393 &omap3xxx_dss__l3,
1394};
1395
1396/* l4_core -> dss */
1397static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1398 .master = &omap3xxx_l4_core_hwmod,
1399 .slave = &omap3430es1_dss_core_hwmod,
1400 .clk = "dss_ick",
1401 .addr = omap2_dss_addrs,
1402 .fw = {
1403 .omap2 = {
1404 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1405 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1406 .flags = OMAP_FIREWALL_L4,
1407 }
1408 },
1409 .user = OCP_USER_MPU | OCP_USER_SDMA,
1410};
1411
1412static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1413 .master = &omap3xxx_l4_core_hwmod,
1414 .slave = &omap3xxx_dss_core_hwmod,
1415 .clk = "dss_ick",
1416 .addr = omap2_dss_addrs,
1417 .fw = {
1418 .omap2 = {
1419 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1420 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1421 .flags = OMAP_FIREWALL_L4,
1422 }
1423 },
1424 .user = OCP_USER_MPU | OCP_USER_SDMA,
1425};
1426
1427/* dss slave ports */
1428static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1429 &omap3430es1_l4_core__dss,
1430};
1431
1432static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1433 &omap3xxx_l4_core__dss,
1434};
1435
1436static struct omap_hwmod_opt_clk dss_opt_clks[] = { 568static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1437 /* 569 /*
1438 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 570 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1460,10 +592,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1460 }, 592 },
1461 .opt_clks = dss_opt_clks, 593 .opt_clks = dss_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 594 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1463 .slaves = omap3430es1_dss_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1465 .masters = omap3xxx_dss_masters,
1466 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1467 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 595 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1468}; 596};
1469 597
@@ -1485,10 +613,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1485 }, 613 },
1486 .opt_clks = dss_opt_clks, 614 .opt_clks = dss_opt_clks,
1487 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 615 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1488 .slaves = omap3xxx_dss_slaves,
1489 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1490 .masters = omap3xxx_dss_masters,
1491 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1492}; 616};
1493 617
1494/* 618/*
@@ -1513,27 +637,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
1513 .sysc = &omap3_dispc_sysc, 637 .sysc = &omap3_dispc_sysc,
1514}; 638};
1515 639
1516/* l4_core -> dss_dispc */
1517static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1518 .master = &omap3xxx_l4_core_hwmod,
1519 .slave = &omap3xxx_dss_dispc_hwmod,
1520 .clk = "dss_ick",
1521 .addr = omap2_dss_dispc_addrs,
1522 .fw = {
1523 .omap2 = {
1524 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1525 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1526 .flags = OMAP_FIREWALL_L4,
1527 }
1528 },
1529 .user = OCP_USER_MPU | OCP_USER_SDMA,
1530};
1531
1532/* dss_dispc slave ports */
1533static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1534 &omap3xxx_l4_core__dss_dispc,
1535};
1536
1537static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 640static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1538 .name = "dss_dispc", 641 .name = "dss_dispc",
1539 .class = &omap3_dispc_hwmod_class, 642 .class = &omap3_dispc_hwmod_class,
@@ -1546,8 +649,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1546 .module_offs = OMAP3430_DSS_MOD, 649 .module_offs = OMAP3430_DSS_MOD,
1547 }, 650 },
1548 }, 651 },
1549 .slaves = omap3xxx_dss_dispc_slaves,
1550 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1551 .flags = HWMOD_NO_IDLEST, 652 .flags = HWMOD_NO_IDLEST,
1552 .dev_attr = &omap2_3_dss_dispc_dev_attr 653 .dev_attr = &omap2_3_dss_dispc_dev_attr
1553}; 654};
@@ -1567,36 +668,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1567}; 668};
1568 669
1569/* dss_dsi1 */ 670/* dss_dsi1 */
1570static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1571 {
1572 .pa_start = 0x4804FC00,
1573 .pa_end = 0x4804FFFF,
1574 .flags = ADDR_TYPE_RT
1575 },
1576 { }
1577};
1578
1579/* l4_core -> dss_dsi1 */
1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1581 .master = &omap3xxx_l4_core_hwmod,
1582 .slave = &omap3xxx_dss_dsi1_hwmod,
1583 .clk = "dss_ick",
1584 .addr = omap3xxx_dss_dsi1_addrs,
1585 .fw = {
1586 .omap2 = {
1587 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1588 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1589 .flags = OMAP_FIREWALL_L4,
1590 }
1591 },
1592 .user = OCP_USER_MPU | OCP_USER_SDMA,
1593};
1594
1595/* dss_dsi1 slave ports */
1596static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1597 &omap3xxx_l4_core__dss_dsi1,
1598};
1599
1600static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 671static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1601 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 672 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1602}; 673};
@@ -1615,32 +686,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1615 }, 686 },
1616 .opt_clks = dss_dsi1_opt_clks, 687 .opt_clks = dss_dsi1_opt_clks,
1617 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 688 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1618 .slaves = omap3xxx_dss_dsi1_slaves,
1619 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1620 .flags = HWMOD_NO_IDLEST, 689 .flags = HWMOD_NO_IDLEST,
1621}; 690};
1622 691
1623/* l4_core -> dss_rfbi */
1624static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1625 .master = &omap3xxx_l4_core_hwmod,
1626 .slave = &omap3xxx_dss_rfbi_hwmod,
1627 .clk = "dss_ick",
1628 .addr = omap2_dss_rfbi_addrs,
1629 .fw = {
1630 .omap2 = {
1631 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1632 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1633 .flags = OMAP_FIREWALL_L4,
1634 }
1635 },
1636 .user = OCP_USER_MPU | OCP_USER_SDMA,
1637};
1638
1639/* dss_rfbi slave ports */
1640static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1641 &omap3xxx_l4_core__dss_rfbi,
1642};
1643
1644static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 692static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1645 { .role = "ick", .clk = "dss_ick" }, 693 { .role = "ick", .clk = "dss_ick" },
1646}; 694};
@@ -1658,32 +706,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1658 }, 706 },
1659 .opt_clks = dss_rfbi_opt_clks, 707 .opt_clks = dss_rfbi_opt_clks,
1660 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 708 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1661 .slaves = omap3xxx_dss_rfbi_slaves,
1662 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1663 .flags = HWMOD_NO_IDLEST, 709 .flags = HWMOD_NO_IDLEST,
1664}; 710};
1665 711
1666/* l4_core -> dss_venc */
1667static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1668 .master = &omap3xxx_l4_core_hwmod,
1669 .slave = &omap3xxx_dss_venc_hwmod,
1670 .clk = "dss_ick",
1671 .addr = omap2_dss_venc_addrs,
1672 .fw = {
1673 .omap2 = {
1674 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1675 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1676 .flags = OMAP_FIREWALL_L4,
1677 }
1678 },
1679 .user = OCP_USER_MPU | OCP_USER_SDMA,
1680};
1681
1682/* dss_venc slave ports */
1683static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1684 &omap3xxx_l4_core__dss_venc,
1685};
1686
1687static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 712static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1688 /* required only on OMAP3430 */ 713 /* required only on OMAP3430 */
1689 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 714 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1702,13 +727,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1702 }, 727 },
1703 .opt_clks = dss_venc_opt_clks, 728 .opt_clks = dss_venc_opt_clks,
1704 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 729 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1705 .slaves = omap3xxx_dss_venc_slaves,
1706 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1707 .flags = HWMOD_NO_IDLEST, 730 .flags = HWMOD_NO_IDLEST,
1708}; 731};
1709 732
1710/* I2C1 */ 733/* I2C1 */
1711
1712static struct omap_i2c_dev_attr i2c1_dev_attr = { 734static struct omap_i2c_dev_attr i2c1_dev_attr = {
1713 .fifo_depth = 8, /* bytes */ 735 .fifo_depth = 8, /* bytes */
1714 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 736 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1716,10 +738,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
1716 OMAP_I2C_FLAG_BUS_SHIFT_2, 738 OMAP_I2C_FLAG_BUS_SHIFT_2,
1717}; 739};
1718 740
1719static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1720 &omap3_l4_core__i2c1,
1721};
1722
1723static struct omap_hwmod omap3xxx_i2c1_hwmod = { 741static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1724 .name = "i2c1", 742 .name = "i2c1",
1725 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 743 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1735,14 +753,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1735 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 753 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1736 }, 754 },
1737 }, 755 },
1738 .slaves = omap3xxx_i2c1_slaves,
1739 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1740 .class = &i2c_class, 756 .class = &i2c_class,
1741 .dev_attr = &i2c1_dev_attr, 757 .dev_attr = &i2c1_dev_attr,
1742}; 758};
1743 759
1744/* I2C2 */ 760/* I2C2 */
1745
1746static struct omap_i2c_dev_attr i2c2_dev_attr = { 761static struct omap_i2c_dev_attr i2c2_dev_attr = {
1747 .fifo_depth = 8, /* bytes */ 762 .fifo_depth = 8, /* bytes */
1748 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 763 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1750,10 +765,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
1750 OMAP_I2C_FLAG_BUS_SHIFT_2, 765 OMAP_I2C_FLAG_BUS_SHIFT_2,
1751}; 766};
1752 767
1753static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1754 &omap3_l4_core__i2c2,
1755};
1756
1757static struct omap_hwmod omap3xxx_i2c2_hwmod = { 768static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1758 .name = "i2c2", 769 .name = "i2c2",
1759 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 770 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1769,14 +780,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1769 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 780 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1770 }, 781 },
1771 }, 782 },
1772 .slaves = omap3xxx_i2c2_slaves,
1773 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1774 .class = &i2c_class, 783 .class = &i2c_class,
1775 .dev_attr = &i2c2_dev_attr, 784 .dev_attr = &i2c2_dev_attr,
1776}; 785};
1777 786
1778/* I2C3 */ 787/* I2C3 */
1779
1780static struct omap_i2c_dev_attr i2c3_dev_attr = { 788static struct omap_i2c_dev_attr i2c3_dev_attr = {
1781 .fifo_depth = 64, /* bytes */ 789 .fifo_depth = 64, /* bytes */
1782 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 790 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1795,10 +803,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1795 { .dma_req = -1 } 803 { .dma_req = -1 }
1796}; 804};
1797 805
1798static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1799 &omap3_l4_core__i2c3,
1800};
1801
1802static struct omap_hwmod omap3xxx_i2c3_hwmod = { 806static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1803 .name = "i2c3", 807 .name = "i2c3",
1804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 808 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1814,114 +818,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1814 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 818 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1815 }, 819 },
1816 }, 820 },
1817 .slaves = omap3xxx_i2c3_slaves,
1818 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1819 .class = &i2c_class, 821 .class = &i2c_class,
1820 .dev_attr = &i2c3_dev_attr, 822 .dev_attr = &i2c3_dev_attr,
1821}; 823};
1822 824
1823/* l4_wkup -> gpio1 */
1824static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1825 {
1826 .pa_start = 0x48310000,
1827 .pa_end = 0x483101ff,
1828 .flags = ADDR_TYPE_RT
1829 },
1830 { }
1831};
1832
1833static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1834 .master = &omap3xxx_l4_wkup_hwmod,
1835 .slave = &omap3xxx_gpio1_hwmod,
1836 .addr = omap3xxx_gpio1_addrs,
1837 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838};
1839
1840/* l4_per -> gpio2 */
1841static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1842 {
1843 .pa_start = 0x49050000,
1844 .pa_end = 0x490501ff,
1845 .flags = ADDR_TYPE_RT
1846 },
1847 { }
1848};
1849
1850static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1851 .master = &omap3xxx_l4_per_hwmod,
1852 .slave = &omap3xxx_gpio2_hwmod,
1853 .addr = omap3xxx_gpio2_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1855};
1856
1857/* l4_per -> gpio3 */
1858static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1859 {
1860 .pa_start = 0x49052000,
1861 .pa_end = 0x490521ff,
1862 .flags = ADDR_TYPE_RT
1863 },
1864 { }
1865};
1866
1867static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1868 .master = &omap3xxx_l4_per_hwmod,
1869 .slave = &omap3xxx_gpio3_hwmod,
1870 .addr = omap3xxx_gpio3_addrs,
1871 .user = OCP_USER_MPU | OCP_USER_SDMA,
1872};
1873
1874/* l4_per -> gpio4 */
1875static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1876 {
1877 .pa_start = 0x49054000,
1878 .pa_end = 0x490541ff,
1879 .flags = ADDR_TYPE_RT
1880 },
1881 { }
1882};
1883
1884static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1885 .master = &omap3xxx_l4_per_hwmod,
1886 .slave = &omap3xxx_gpio4_hwmod,
1887 .addr = omap3xxx_gpio4_addrs,
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> gpio5 */
1892static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1893 {
1894 .pa_start = 0x49056000,
1895 .pa_end = 0x490561ff,
1896 .flags = ADDR_TYPE_RT
1897 },
1898 { }
1899};
1900
1901static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1902 .master = &omap3xxx_l4_per_hwmod,
1903 .slave = &omap3xxx_gpio5_hwmod,
1904 .addr = omap3xxx_gpio5_addrs,
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906};
1907
1908/* l4_per -> gpio6 */
1909static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1910 {
1911 .pa_start = 0x49058000,
1912 .pa_end = 0x490581ff,
1913 .flags = ADDR_TYPE_RT
1914 },
1915 { }
1916};
1917
1918static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1919 .master = &omap3xxx_l4_per_hwmod,
1920 .slave = &omap3xxx_gpio6_hwmod,
1921 .addr = omap3xxx_gpio6_addrs,
1922 .user = OCP_USER_MPU | OCP_USER_SDMA,
1923};
1924
1925/* 825/*
1926 * 'gpio' class 826 * 'gpio' class
1927 * general purpose io module 827 * general purpose io module
@@ -1944,7 +844,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1944 .rev = 1, 844 .rev = 1,
1945}; 845};
1946 846
1947/* gpio_dev_attr*/ 847/* gpio_dev_attr */
1948static struct omap_gpio_dev_attr gpio_dev_attr = { 848static struct omap_gpio_dev_attr gpio_dev_attr = {
1949 .bank_width = 32, 849 .bank_width = 32,
1950 .dbck_flag = true, 850 .dbck_flag = true,
@@ -1955,10 +855,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1955 { .role = "dbclk", .clk = "gpio1_dbck", }, 855 { .role = "dbclk", .clk = "gpio1_dbck", },
1956}; 856};
1957 857
1958static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1959 &omap3xxx_l4_wkup__gpio1,
1960};
1961
1962static struct omap_hwmod omap3xxx_gpio1_hwmod = { 858static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1963 .name = "gpio1", 859 .name = "gpio1",
1964 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 860 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1975,8 +871,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1975 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 871 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1976 }, 872 },
1977 }, 873 },
1978 .slaves = omap3xxx_gpio1_slaves,
1979 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1980 .class = &omap3xxx_gpio_hwmod_class, 874 .class = &omap3xxx_gpio_hwmod_class,
1981 .dev_attr = &gpio_dev_attr, 875 .dev_attr = &gpio_dev_attr,
1982}; 876};
@@ -1986,10 +880,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1986 { .role = "dbclk", .clk = "gpio2_dbck", }, 880 { .role = "dbclk", .clk = "gpio2_dbck", },
1987}; 881};
1988 882
1989static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1990 &omap3xxx_l4_per__gpio2,
1991};
1992
1993static struct omap_hwmod omap3xxx_gpio2_hwmod = { 883static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1994 .name = "gpio2", 884 .name = "gpio2",
1995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 885 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2006,8 +896,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2006 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 896 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2007 }, 897 },
2008 }, 898 },
2009 .slaves = omap3xxx_gpio2_slaves,
2010 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2011 .class = &omap3xxx_gpio_hwmod_class, 899 .class = &omap3xxx_gpio_hwmod_class,
2012 .dev_attr = &gpio_dev_attr, 900 .dev_attr = &gpio_dev_attr,
2013}; 901};
@@ -2017,10 +905,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2017 { .role = "dbclk", .clk = "gpio3_dbck", }, 905 { .role = "dbclk", .clk = "gpio3_dbck", },
2018}; 906};
2019 907
2020static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2021 &omap3xxx_l4_per__gpio3,
2022};
2023
2024static struct omap_hwmod omap3xxx_gpio3_hwmod = { 908static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2025 .name = "gpio3", 909 .name = "gpio3",
2026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 910 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2037,8 +921,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2037 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 921 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2038 }, 922 },
2039 }, 923 },
2040 .slaves = omap3xxx_gpio3_slaves,
2041 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2042 .class = &omap3xxx_gpio_hwmod_class, 924 .class = &omap3xxx_gpio_hwmod_class,
2043 .dev_attr = &gpio_dev_attr, 925 .dev_attr = &gpio_dev_attr,
2044}; 926};
@@ -2048,10 +930,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2048 { .role = "dbclk", .clk = "gpio4_dbck", }, 930 { .role = "dbclk", .clk = "gpio4_dbck", },
2049}; 931};
2050 932
2051static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2052 &omap3xxx_l4_per__gpio4,
2053};
2054
2055static struct omap_hwmod omap3xxx_gpio4_hwmod = { 933static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2056 .name = "gpio4", 934 .name = "gpio4",
2057 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 935 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2068,8 +946,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2068 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 946 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2069 }, 947 },
2070 }, 948 },
2071 .slaves = omap3xxx_gpio4_slaves,
2072 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2073 .class = &omap3xxx_gpio_hwmod_class, 949 .class = &omap3xxx_gpio_hwmod_class,
2074 .dev_attr = &gpio_dev_attr, 950 .dev_attr = &gpio_dev_attr,
2075}; 951};
@@ -2084,10 +960,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2084 { .role = "dbclk", .clk = "gpio5_dbck", }, 960 { .role = "dbclk", .clk = "gpio5_dbck", },
2085}; 961};
2086 962
2087static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2088 &omap3xxx_l4_per__gpio5,
2089};
2090
2091static struct omap_hwmod omap3xxx_gpio5_hwmod = { 963static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2092 .name = "gpio5", 964 .name = "gpio5",
2093 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2104,8 +976,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2104 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 976 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2105 }, 977 },
2106 }, 978 },
2107 .slaves = omap3xxx_gpio5_slaves,
2108 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2109 .class = &omap3xxx_gpio_hwmod_class, 979 .class = &omap3xxx_gpio_hwmod_class,
2110 .dev_attr = &gpio_dev_attr, 980 .dev_attr = &gpio_dev_attr,
2111}; 981};
@@ -2120,10 +990,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2120 { .role = "dbclk", .clk = "gpio6_dbck", }, 990 { .role = "dbclk", .clk = "gpio6_dbck", },
2121}; 991};
2122 992
2123static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2124 &omap3xxx_l4_per__gpio6,
2125};
2126
2127static struct omap_hwmod omap3xxx_gpio6_hwmod = { 993static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2128 .name = "gpio6", 994 .name = "gpio6",
2129 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2140,20 +1006,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2140 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1006 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2141 }, 1007 },
2142 }, 1008 },
2143 .slaves = omap3xxx_gpio6_slaves,
2144 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2145 .class = &omap3xxx_gpio_hwmod_class, 1009 .class = &omap3xxx_gpio_hwmod_class,
2146 .dev_attr = &gpio_dev_attr, 1010 .dev_attr = &gpio_dev_attr,
2147}; 1011};
2148 1012
2149/* dma_system -> L3 */
2150static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2151 .master = &omap3xxx_dma_system_hwmod,
2152 .slave = &omap3xxx_l3_main_hwmod,
2153 .clk = "core_l3_ick",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2155};
2156
2157/* dma attributes */ 1013/* dma attributes */
2158static struct omap_dma_dev_attr dma_dev_attr = { 1014static struct omap_dma_dev_attr dma_dev_attr = {
2159 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1015 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -2180,34 +1036,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2180}; 1036};
2181 1037
2182/* dma_system */ 1038/* dma_system */
2183static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2184 {
2185 .pa_start = 0x48056000,
2186 .pa_end = 0x48056fff,
2187 .flags = ADDR_TYPE_RT
2188 },
2189 { }
2190};
2191
2192/* dma_system master ports */
2193static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2194 &omap3xxx_dma_system__l3,
2195};
2196
2197/* l4_cfg -> dma_system */
2198static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2199 .master = &omap3xxx_l4_core_hwmod,
2200 .slave = &omap3xxx_dma_system_hwmod,
2201 .clk = "core_l4_ick",
2202 .addr = omap3xxx_dma_system_addrs,
2203 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204};
2205
2206/* dma_system slave ports */
2207static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2208 &omap3xxx_l4_core__dma_system,
2209};
2210
2211static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1039static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2212 .name = "dma", 1040 .name = "dma",
2213 .class = &omap3xxx_dma_hwmod_class, 1041 .class = &omap3xxx_dma_hwmod_class,
@@ -2222,10 +1050,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2222 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1050 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2223 }, 1051 },
2224 }, 1052 },
2225 .slaves = omap3xxx_dma_system_slaves,
2226 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2227 .masters = omap3xxx_dma_system_masters,
2228 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2229 .dev_attr = &dma_dev_attr, 1053 .dev_attr = &dma_dev_attr,
2230 .flags = HWMOD_NO_IDLEST, 1054 .flags = HWMOD_NO_IDLEST,
2231}; 1055};
@@ -2252,36 +1076,12 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2252 1076
2253/* mcbsp1 */ 1077/* mcbsp1 */
2254static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1078static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2255 { .name = "irq", .irq = 16 }, 1079 { .name = "common", .irq = 16 },
2256 { .name = "tx", .irq = 59 }, 1080 { .name = "tx", .irq = 59 },
2257 { .name = "rx", .irq = 60 }, 1081 { .name = "rx", .irq = 60 },
2258 { .irq = -1 } 1082 { .irq = -1 }
2259}; 1083};
2260 1084
2261static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2262 {
2263 .name = "mpu",
2264 .pa_start = 0x48074000,
2265 .pa_end = 0x480740ff,
2266 .flags = ADDR_TYPE_RT
2267 },
2268 { }
2269};
2270
2271/* l4_core -> mcbsp1 */
2272static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap3xxx_mcbsp1_hwmod,
2275 .clk = "mcbsp1_ick",
2276 .addr = omap3xxx_mcbsp1_addrs,
2277 .user = OCP_USER_MPU | OCP_USER_SDMA,
2278};
2279
2280/* mcbsp1 slave ports */
2281static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2282 &omap3xxx_l4_core__mcbsp1,
2283};
2284
2285static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1085static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2286 .name = "mcbsp1", 1086 .name = "mcbsp1",
2287 .class = &omap3xxx_mcbsp_hwmod_class, 1087 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2297,42 +1097,16 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2297 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1097 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2298 }, 1098 },
2299 }, 1099 },
2300 .slaves = omap3xxx_mcbsp1_slaves,
2301 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2302}; 1100};
2303 1101
2304/* mcbsp2 */ 1102/* mcbsp2 */
2305static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1103static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2306 { .name = "irq", .irq = 17 }, 1104 { .name = "common", .irq = 17 },
2307 { .name = "tx", .irq = 62 }, 1105 { .name = "tx", .irq = 62 },
2308 { .name = "rx", .irq = 63 }, 1106 { .name = "rx", .irq = 63 },
2309 { .irq = -1 } 1107 { .irq = -1 }
2310}; 1108};
2311 1109
2312static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2313 {
2314 .name = "mpu",
2315 .pa_start = 0x49022000,
2316 .pa_end = 0x490220ff,
2317 .flags = ADDR_TYPE_RT
2318 },
2319 { }
2320};
2321
2322/* l4_per -> mcbsp2 */
2323static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2324 .master = &omap3xxx_l4_per_hwmod,
2325 .slave = &omap3xxx_mcbsp2_hwmod,
2326 .clk = "mcbsp2_ick",
2327 .addr = omap3xxx_mcbsp2_addrs,
2328 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329};
2330
2331/* mcbsp2 slave ports */
2332static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2333 &omap3xxx_l4_per__mcbsp2,
2334};
2335
2336static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1110static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2337 .sidetone = "mcbsp2_sidetone", 1111 .sidetone = "mcbsp2_sidetone",
2338}; 1112};
@@ -2352,45 +1126,19 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2352 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1126 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2353 }, 1127 },
2354 }, 1128 },
2355 .slaves = omap3xxx_mcbsp2_slaves,
2356 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2357 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1129 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2358}; 1130};
2359 1131
2360/* mcbsp3 */ 1132/* mcbsp3 */
2361static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1133static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2362 { .name = "irq", .irq = 22 }, 1134 { .name = "common", .irq = 22 },
2363 { .name = "tx", .irq = 89 }, 1135 { .name = "tx", .irq = 89 },
2364 { .name = "rx", .irq = 90 }, 1136 { .name = "rx", .irq = 90 },
2365 { .irq = -1 } 1137 { .irq = -1 }
2366}; 1138};
2367 1139
2368static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2369 {
2370 .name = "mpu",
2371 .pa_start = 0x49024000,
2372 .pa_end = 0x490240ff,
2373 .flags = ADDR_TYPE_RT
2374 },
2375 { }
2376};
2377
2378/* l4_per -> mcbsp3 */
2379static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2380 .master = &omap3xxx_l4_per_hwmod,
2381 .slave = &omap3xxx_mcbsp3_hwmod,
2382 .clk = "mcbsp3_ick",
2383 .addr = omap3xxx_mcbsp3_addrs,
2384 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385};
2386
2387/* mcbsp3 slave ports */
2388static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2389 &omap3xxx_l4_per__mcbsp3,
2390};
2391
2392static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1140static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2393 .sidetone = "mcbsp3_sidetone", 1141 .sidetone = "mcbsp3_sidetone",
2394}; 1142};
2395 1143
2396static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1144static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
@@ -2408,14 +1156,12 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2408 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1156 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2409 }, 1157 },
2410 }, 1158 },
2411 .slaves = omap3xxx_mcbsp3_slaves,
2412 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2413 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1159 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2414}; 1160};
2415 1161
2416/* mcbsp4 */ 1162/* mcbsp4 */
2417static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1163static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2418 { .name = "irq", .irq = 23 }, 1164 { .name = "common", .irq = 23 },
2419 { .name = "tx", .irq = 54 }, 1165 { .name = "tx", .irq = 54 },
2420 { .name = "rx", .irq = 55 }, 1166 { .name = "rx", .irq = 55 },
2421 { .irq = -1 } 1167 { .irq = -1 }
@@ -2427,30 +1173,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2427 { .dma_req = -1 } 1173 { .dma_req = -1 }
2428}; 1174};
2429 1175
2430static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2431 {
2432 .name = "mpu",
2433 .pa_start = 0x49026000,
2434 .pa_end = 0x490260ff,
2435 .flags = ADDR_TYPE_RT
2436 },
2437 { }
2438};
2439
2440/* l4_per -> mcbsp4 */
2441static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2442 .master = &omap3xxx_l4_per_hwmod,
2443 .slave = &omap3xxx_mcbsp4_hwmod,
2444 .clk = "mcbsp4_ick",
2445 .addr = omap3xxx_mcbsp4_addrs,
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2447};
2448
2449/* mcbsp4 slave ports */
2450static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2451 &omap3xxx_l4_per__mcbsp4,
2452};
2453
2454static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1176static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2455 .name = "mcbsp4", 1177 .name = "mcbsp4",
2456 .class = &omap3xxx_mcbsp_hwmod_class, 1178 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2466,13 +1188,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2466 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1188 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2467 }, 1189 },
2468 }, 1190 },
2469 .slaves = omap3xxx_mcbsp4_slaves,
2470 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2471}; 1191};
2472 1192
2473/* mcbsp5 */ 1193/* mcbsp5 */
2474static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1194static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2475 { .name = "irq", .irq = 27 }, 1195 { .name = "common", .irq = 27 },
2476 { .name = "tx", .irq = 81 }, 1196 { .name = "tx", .irq = 81 },
2477 { .name = "rx", .irq = 82 }, 1197 { .name = "rx", .irq = 82 },
2478 { .irq = -1 } 1198 { .irq = -1 }
@@ -2484,30 +1204,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2484 { .dma_req = -1 } 1204 { .dma_req = -1 }
2485}; 1205};
2486 1206
2487static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2488 {
2489 .name = "mpu",
2490 .pa_start = 0x48096000,
2491 .pa_end = 0x480960ff,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495};
2496
2497/* l4_core -> mcbsp5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2499 .master = &omap3xxx_l4_core_hwmod,
2500 .slave = &omap3xxx_mcbsp5_hwmod,
2501 .clk = "mcbsp5_ick",
2502 .addr = omap3xxx_mcbsp5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506/* mcbsp5 slave ports */
2507static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2508 &omap3xxx_l4_core__mcbsp5,
2509};
2510
2511static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1207static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2512 .name = "mcbsp5", 1208 .name = "mcbsp5",
2513 .class = &omap3xxx_mcbsp_hwmod_class, 1209 .class = &omap3xxx_mcbsp_hwmod_class,
@@ -2523,11 +1219,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2523 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1219 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2524 }, 1220 },
2525 }, 1221 },
2526 .slaves = omap3xxx_mcbsp5_slaves,
2527 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2528}; 1222};
2529/* 'mcbsp sidetone' class */
2530 1223
1224/* 'mcbsp sidetone' class */
2531static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1225static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2532 .sysc_offs = 0x0010, 1226 .sysc_offs = 0x0010,
2533 .sysc_flags = SYSC_HAS_AUTOIDLE, 1227 .sysc_flags = SYSC_HAS_AUTOIDLE,
@@ -2545,30 +1239,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2545 { .irq = -1 } 1239 { .irq = -1 }
2546}; 1240};
2547 1241
2548static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2549 {
2550 .name = "sidetone",
2551 .pa_start = 0x49028000,
2552 .pa_end = 0x490280ff,
2553 .flags = ADDR_TYPE_RT
2554 },
2555 { }
2556};
2557
2558/* l4_per -> mcbsp2_sidetone */
2559static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2560 .master = &omap3xxx_l4_per_hwmod,
2561 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2562 .clk = "mcbsp2_ick",
2563 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2564 .user = OCP_USER_MPU,
2565};
2566
2567/* mcbsp2_sidetone slave ports */
2568static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2569 &omap3xxx_l4_per__mcbsp2_sidetone,
2570};
2571
2572static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1242static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2573 .name = "mcbsp2_sidetone", 1243 .name = "mcbsp2_sidetone",
2574 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1244 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2583,8 +1253,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2583 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1253 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2584 }, 1254 },
2585 }, 1255 },
2586 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2587 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2588}; 1256};
2589 1257
2590/* mcbsp3_sidetone */ 1258/* mcbsp3_sidetone */
@@ -2593,30 +1261,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2593 { .irq = -1 } 1261 { .irq = -1 }
2594}; 1262};
2595 1263
2596static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2597 {
2598 .name = "sidetone",
2599 .pa_start = 0x4902A000,
2600 .pa_end = 0x4902A0ff,
2601 .flags = ADDR_TYPE_RT
2602 },
2603 { }
2604};
2605
2606/* l4_per -> mcbsp3_sidetone */
2607static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2608 .master = &omap3xxx_l4_per_hwmod,
2609 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2610 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2612 .user = OCP_USER_MPU,
2613};
2614
2615/* mcbsp3_sidetone slave ports */
2616static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2617 &omap3xxx_l4_per__mcbsp3_sidetone,
2618};
2619
2620static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1264static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2621 .name = "mcbsp3_sidetone", 1265 .name = "mcbsp3_sidetone",
2622 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1266 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2631,11 +1275,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2631 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1275 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2632 }, 1276 },
2633 }, 1277 },
2634 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2635 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2636}; 1278};
2637 1279
2638
2639/* SR common */ 1280/* SR common */
2640static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1281static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2641 .clkact_shift = 20, 1282 .clkact_shift = 20,
@@ -2656,7 +1297,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2656 1297
2657static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1298static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2658 .sidle_shift = 24, 1299 .sidle_shift = 24,
2659 .enwkup_shift = 26 1300 .enwkup_shift = 26,
2660}; 1301};
2661 1302
2662static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1303static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2678,12 +1319,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
2678 .sensor_voltdm_name = "mpu_iva", 1319 .sensor_voltdm_name = "mpu_iva",
2679}; 1320};
2680 1321
2681static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { 1322static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
2682 &omap3_l4_core__sr1, 1323 { .irq = 18 },
1324 { .irq = -1 }
2683}; 1325};
2684 1326
2685static struct omap_hwmod omap34xx_sr1_hwmod = { 1327static struct omap_hwmod omap34xx_sr1_hwmod = {
2686 .name = "sr1_hwmod", 1328 .name = "sr1",
2687 .class = &omap34xx_smartreflex_hwmod_class, 1329 .class = &omap34xx_smartreflex_hwmod_class,
2688 .main_clk = "sr1_fck", 1330 .main_clk = "sr1_fck",
2689 .prcm = { 1331 .prcm = {
@@ -2695,15 +1337,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
2695 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1337 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2696 }, 1338 },
2697 }, 1339 },
2698 .slaves = omap3_sr1_slaves,
2699 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2700 .dev_attr = &sr1_dev_attr, 1340 .dev_attr = &sr1_dev_attr,
2701 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1341 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2702 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1342 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2703}; 1343};
2704 1344
2705static struct omap_hwmod omap36xx_sr1_hwmod = { 1345static struct omap_hwmod omap36xx_sr1_hwmod = {
2706 .name = "sr1_hwmod", 1346 .name = "sr1",
2707 .class = &omap36xx_smartreflex_hwmod_class, 1347 .class = &omap36xx_smartreflex_hwmod_class,
2708 .main_clk = "sr1_fck", 1348 .main_clk = "sr1_fck",
2709 .prcm = { 1349 .prcm = {
@@ -2715,8 +1355,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
2715 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1355 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2716 }, 1356 },
2717 }, 1357 },
2718 .slaves = omap3_sr1_slaves,
2719 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2720 .dev_attr = &sr1_dev_attr, 1358 .dev_attr = &sr1_dev_attr,
2721 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1359 .mpu_irqs = omap3_smartreflex_mpu_irqs,
2722}; 1360};
@@ -2726,12 +1364,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
2726 .sensor_voltdm_name = "core", 1364 .sensor_voltdm_name = "core",
2727}; 1365};
2728 1366
2729static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { 1367static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
2730 &omap3_l4_core__sr2, 1368 { .irq = 19 },
1369 { .irq = -1 }
2731}; 1370};
2732 1371
2733static struct omap_hwmod omap34xx_sr2_hwmod = { 1372static struct omap_hwmod omap34xx_sr2_hwmod = {
2734 .name = "sr2_hwmod", 1373 .name = "sr2",
2735 .class = &omap34xx_smartreflex_hwmod_class, 1374 .class = &omap34xx_smartreflex_hwmod_class,
2736 .main_clk = "sr2_fck", 1375 .main_clk = "sr2_fck",
2737 .prcm = { 1376 .prcm = {
@@ -2743,15 +1382,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
2743 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1382 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2744 }, 1383 },
2745 }, 1384 },
2746 .slaves = omap3_sr2_slaves,
2747 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2748 .dev_attr = &sr2_dev_attr, 1385 .dev_attr = &sr2_dev_attr,
2749 .mpu_irqs = omap3_smartreflex_core_irqs, 1386 .mpu_irqs = omap3_smartreflex_core_irqs,
2750 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1387 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2751}; 1388};
2752 1389
2753static struct omap_hwmod omap36xx_sr2_hwmod = { 1390static struct omap_hwmod omap36xx_sr2_hwmod = {
2754 .name = "sr2_hwmod", 1391 .name = "sr2",
2755 .class = &omap36xx_smartreflex_hwmod_class, 1392 .class = &omap36xx_smartreflex_hwmod_class,
2756 .main_clk = "sr2_fck", 1393 .main_clk = "sr2_fck",
2757 .prcm = { 1394 .prcm = {
@@ -2763,8 +1400,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
2763 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1400 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2764 }, 1401 },
2765 }, 1402 },
2766 .slaves = omap3_sr2_slaves,
2767 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2768 .dev_attr = &sr2_dev_attr, 1403 .dev_attr = &sr2_dev_attr,
2769 .mpu_irqs = omap3_smartreflex_core_irqs, 1404 .mpu_irqs = omap3_smartreflex_core_irqs,
2770}; 1405};
@@ -2790,34 +1425,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2790 .sysc = &omap3xxx_mailbox_sysc, 1425 .sysc = &omap3xxx_mailbox_sysc,
2791}; 1426};
2792 1427
2793static struct omap_hwmod omap3xxx_mailbox_hwmod;
2794static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1428static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2795 { .irq = 26 }, 1429 { .irq = 26 },
2796 { .irq = -1 } 1430 { .irq = -1 }
2797}; 1431};
2798 1432
2799static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2800 {
2801 .pa_start = 0x48094000,
2802 .pa_end = 0x480941ff,
2803 .flags = ADDR_TYPE_RT,
2804 },
2805 { }
2806};
2807
2808/* l4_core -> mailbox */
2809static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2810 .master = &omap3xxx_l4_core_hwmod,
2811 .slave = &omap3xxx_mailbox_hwmod,
2812 .addr = omap3xxx_mailbox_addrs,
2813 .user = OCP_USER_MPU | OCP_USER_SDMA,
2814};
2815
2816/* mailbox slave ports */
2817static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2818 &omap3xxx_l4_core__mailbox,
2819};
2820
2821static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1433static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2822 .name = "mailbox", 1434 .name = "mailbox",
2823 .class = &omap3xxx_mailbox_hwmod_class, 1435 .class = &omap3xxx_mailbox_hwmod_class,
@@ -2832,53 +1444,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2832 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1444 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2833 }, 1445 },
2834 }, 1446 },
2835 .slaves = omap3xxx_mailbox_slaves,
2836 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2837};
2838
2839/* l4 core -> mcspi1 interface */
2840static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2841 .master = &omap3xxx_l4_core_hwmod,
2842 .slave = &omap34xx_mcspi1,
2843 .clk = "mcspi1_ick",
2844 .addr = omap2_mcspi1_addr_space,
2845 .user = OCP_USER_MPU | OCP_USER_SDMA,
2846};
2847
2848/* l4 core -> mcspi2 interface */
2849static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2850 .master = &omap3xxx_l4_core_hwmod,
2851 .slave = &omap34xx_mcspi2,
2852 .clk = "mcspi2_ick",
2853 .addr = omap2_mcspi2_addr_space,
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2855};
2856
2857/* l4 core -> mcspi3 interface */
2858static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2859 .master = &omap3xxx_l4_core_hwmod,
2860 .slave = &omap34xx_mcspi3,
2861 .clk = "mcspi3_ick",
2862 .addr = omap2430_mcspi3_addr_space,
2863 .user = OCP_USER_MPU | OCP_USER_SDMA,
2864};
2865
2866/* l4 core -> mcspi4 interface */
2867static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2868 {
2869 .pa_start = 0x480ba000,
2870 .pa_end = 0x480ba0ff,
2871 .flags = ADDR_TYPE_RT,
2872 },
2873 { }
2874};
2875
2876static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap34xx_mcspi4,
2879 .clk = "mcspi4_ick",
2880 .addr = omap34xx_mcspi4_addr_space,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882}; 1447};
2883 1448
2884/* 1449/*
@@ -2905,10 +1470,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
2905}; 1470};
2906 1471
2907/* mcspi1 */ 1472/* mcspi1 */
2908static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2909 &omap34xx_l4_core__mcspi1,
2910};
2911
2912static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1473static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2913 .num_chipselect = 4, 1474 .num_chipselect = 4,
2914}; 1475};
@@ -2927,17 +1488,11 @@ static struct omap_hwmod omap34xx_mcspi1 = {
2927 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1488 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2928 }, 1489 },
2929 }, 1490 },
2930 .slaves = omap34xx_mcspi1_slaves,
2931 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2932 .class = &omap34xx_mcspi_class, 1491 .class = &omap34xx_mcspi_class,
2933 .dev_attr = &omap_mcspi1_dev_attr, 1492 .dev_attr = &omap_mcspi1_dev_attr,
2934}; 1493};
2935 1494
2936/* mcspi2 */ 1495/* mcspi2 */
2937static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2938 &omap34xx_l4_core__mcspi2,
2939};
2940
2941static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1496static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2942 .num_chipselect = 2, 1497 .num_chipselect = 2,
2943}; 1498};
@@ -2956,8 +1511,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
2956 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1511 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2957 }, 1512 },
2958 }, 1513 },
2959 .slaves = omap34xx_mcspi2_slaves,
2960 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2961 .class = &omap34xx_mcspi_class, 1514 .class = &omap34xx_mcspi_class,
2962 .dev_attr = &omap_mcspi2_dev_attr, 1515 .dev_attr = &omap_mcspi2_dev_attr,
2963}; 1516};
@@ -2976,10 +1529,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2976 { .dma_req = -1 } 1529 { .dma_req = -1 }
2977}; 1530};
2978 1531
2979static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2980 &omap34xx_l4_core__mcspi3,
2981};
2982
2983static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1532static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2984 .num_chipselect = 2, 1533 .num_chipselect = 2,
2985}; 1534};
@@ -2998,13 +1547,11 @@ static struct omap_hwmod omap34xx_mcspi3 = {
2998 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1547 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2999 }, 1548 },
3000 }, 1549 },
3001 .slaves = omap34xx_mcspi3_slaves,
3002 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3003 .class = &omap34xx_mcspi_class, 1550 .class = &omap34xx_mcspi_class,
3004 .dev_attr = &omap_mcspi3_dev_attr, 1551 .dev_attr = &omap_mcspi3_dev_attr,
3005}; 1552};
3006 1553
3007/* SPI4 */ 1554/* mcspi4 */
3008static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1555static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3009 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 1556 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3010 { .irq = -1 } 1557 { .irq = -1 }
@@ -3016,10 +1563,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3016 { .dma_req = -1 } 1563 { .dma_req = -1 }
3017}; 1564};
3018 1565
3019static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3020 &omap34xx_l4_core__mcspi4,
3021};
3022
3023static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1566static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3024 .num_chipselect = 1, 1567 .num_chipselect = 1,
3025}; 1568};
@@ -3038,15 +1581,11 @@ static struct omap_hwmod omap34xx_mcspi4 = {
3038 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1581 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3039 }, 1582 },
3040 }, 1583 },
3041 .slaves = omap34xx_mcspi4_slaves,
3042 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3043 .class = &omap34xx_mcspi_class, 1584 .class = &omap34xx_mcspi_class,
3044 .dev_attr = &omap_mcspi4_dev_attr, 1585 .dev_attr = &omap_mcspi4_dev_attr,
3045}; 1586};
3046 1587
3047/* 1588/* usbhsotg */
3048 * usbhsotg
3049 */
3050static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1589static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3051 .rev_offs = 0x0400, 1590 .rev_offs = 0x0400,
3052 .sysc_offs = 0x0404, 1591 .sysc_offs = 0x0404,
@@ -3063,6 +1602,7 @@ static struct omap_hwmod_class usbotg_class = {
3063 .name = "usbotg", 1602 .name = "usbotg",
3064 .sysc = &omap3xxx_usbhsotg_sysc, 1603 .sysc = &omap3xxx_usbhsotg_sysc,
3065}; 1604};
1605
3066/* usb_otg_hs */ 1606/* usb_otg_hs */
3067static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1607static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3068 1608
@@ -3085,10 +1625,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3085 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1625 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3086 }, 1626 },
3087 }, 1627 },
3088 .masters = omap3xxx_usbhsotg_masters,
3089 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3090 .slaves = omap3xxx_usbhsotg_slaves,
3091 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3092 .class = &usbotg_class, 1628 .class = &usbotg_class,
3093 1629
3094 /* 1630 /*
@@ -3120,15 +1656,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3120 .omap2 = { 1656 .omap2 = {
3121 }, 1657 },
3122 }, 1658 },
3123 .masters = am35xx_usbhsotg_masters,
3124 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3125 .slaves = am35xx_usbhsotg_slaves,
3126 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3127 .class = &am35xx_usbotg_class, 1659 .class = &am35xx_usbotg_class,
3128}; 1660};
3129 1661
3130/* MMC/SD/SDIO common */ 1662/* MMC/SD/SDIO common */
3131
3132static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1663static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3133 .rev_offs = 0x1fc, 1664 .rev_offs = 0x1fc,
3134 .sysc_offs = 0x10, 1665 .sysc_offs = 0x10,
@@ -3162,10 +1693,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3162 { .role = "dbck", .clk = "omap_32k_fck", }, 1693 { .role = "dbck", .clk = "omap_32k_fck", },
3163}; 1694};
3164 1695
3165static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3166 &omap3xxx_l4_core__mmc1,
3167};
3168
3169static struct omap_mmc_dev_attr mmc1_dev_attr = { 1696static struct omap_mmc_dev_attr mmc1_dev_attr = {
3170 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1697 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3171}; 1698};
@@ -3193,8 +1720,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
3193 }, 1720 },
3194 }, 1721 },
3195 .dev_attr = &mmc1_pre_es3_dev_attr, 1722 .dev_attr = &mmc1_pre_es3_dev_attr,
3196 .slaves = omap3xxx_mmc1_slaves,
3197 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3198 .class = &omap34xx_mmc_class, 1723 .class = &omap34xx_mmc_class,
3199}; 1724};
3200 1725
@@ -3215,8 +1740,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
3215 }, 1740 },
3216 }, 1741 },
3217 .dev_attr = &mmc1_dev_attr, 1742 .dev_attr = &mmc1_dev_attr,
3218 .slaves = omap3xxx_mmc1_slaves,
3219 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3220 .class = &omap34xx_mmc_class, 1743 .class = &omap34xx_mmc_class,
3221}; 1744};
3222 1745
@@ -3237,10 +1760,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3237 { .role = "dbck", .clk = "omap_32k_fck", }, 1760 { .role = "dbck", .clk = "omap_32k_fck", },
3238}; 1761};
3239 1762
3240static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3241 &omap3xxx_l4_core__mmc2,
3242};
3243
3244/* See 35xx errata 2.1.1.128 in SPRZ278F */ 1763/* See 35xx errata 2.1.1.128 in SPRZ278F */
3245static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 1764static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
3246 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1765 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
@@ -3263,8 +1782,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
3263 }, 1782 },
3264 }, 1783 },
3265 .dev_attr = &mmc2_pre_es3_dev_attr, 1784 .dev_attr = &mmc2_pre_es3_dev_attr,
3266 .slaves = omap3xxx_mmc2_slaves,
3267 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3268 .class = &omap34xx_mmc_class, 1785 .class = &omap34xx_mmc_class,
3269}; 1786};
3270 1787
@@ -3284,8 +1801,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
3284 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1801 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3285 }, 1802 },
3286 }, 1803 },
3287 .slaves = omap3xxx_mmc2_slaves,
3288 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3289 .class = &omap34xx_mmc_class, 1804 .class = &omap34xx_mmc_class,
3290}; 1805};
3291 1806
@@ -3306,10 +1821,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3306 { .role = "dbck", .clk = "omap_32k_fck", }, 1821 { .role = "dbck", .clk = "omap_32k_fck", },
3307}; 1822};
3308 1823
3309static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3310 &omap3xxx_l4_core__mmc3,
3311};
3312
3313static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1824static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3314 .name = "mmc3", 1825 .name = "mmc3",
3315 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1826 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
@@ -3325,8 +1836,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3325 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1836 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3326 }, 1837 },
3327 }, 1838 },
3328 .slaves = omap3xxx_mmc3_slaves,
3329 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3330 .class = &omap34xx_mmc_class, 1839 .class = &omap34xx_mmc_class,
3331}; 1840};
3332 1841
@@ -3334,12 +1843,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3334 * 'usb_host_hs' class 1843 * 'usb_host_hs' class
3335 * high-speed multi-port usb host controller 1844 * high-speed multi-port usb host controller
3336 */ 1845 */
3337static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3338 .master = &omap3xxx_usb_host_hs_hwmod,
3339 .slave = &omap3xxx_l3_main_hwmod,
3340 .clk = "core_l3_ick",
3341 .user = OCP_USER_MPU,
3342};
3343 1846
3344static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1847static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
3345 .rev_offs = 0x0000, 1848 .rev_offs = 0x0000,
@@ -3358,42 +1861,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
3358 .sysc = &omap3xxx_usb_host_hs_sysc, 1861 .sysc = &omap3xxx_usb_host_hs_sysc,
3359}; 1862};
3360 1863
3361static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
3362 &omap3xxx_usb_host_hs__l3_main_2,
3363};
3364
3365static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3366 {
3367 .name = "uhh",
3368 .pa_start = 0x48064000,
3369 .pa_end = 0x480643ff,
3370 .flags = ADDR_TYPE_RT
3371 },
3372 {
3373 .name = "ohci",
3374 .pa_start = 0x48064400,
3375 .pa_end = 0x480647ff,
3376 },
3377 {
3378 .name = "ehci",
3379 .pa_start = 0x48064800,
3380 .pa_end = 0x48064cff,
3381 },
3382 {}
3383};
3384
3385static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3386 .master = &omap3xxx_l4_core_hwmod,
3387 .slave = &omap3xxx_usb_host_hs_hwmod,
3388 .clk = "usbhost_ick",
3389 .addr = omap3xxx_usb_host_hs_addrs,
3390 .user = OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
3394 &omap3xxx_l4_core__usb_host_hs,
3395};
3396
3397static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1864static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
3398 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1865 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
3399}; 1866};
@@ -3422,10 +1889,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
3422 }, 1889 },
3423 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 1890 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
3424 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 1891 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
3425 .slaves = omap3xxx_usb_host_hs_slaves,
3426 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
3427 .masters = omap3xxx_usb_host_hs_masters,
3428 .masters_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
3429 1892
3430 /* 1893 /*
3431 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1894 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3501,6 +1964,1134 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
3501 { .irq = -1 } 1964 { .irq = -1 }
3502}; 1965};
3503 1966
1967static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1968 .name = "usb_tll_hs",
1969 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1970 .clkdm_name = "l3_init_clkdm",
1971 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
1972 .main_clk = "usbtll_fck",
1973 .prcm = {
1974 .omap2 = {
1975 .module_offs = CORE_MOD,
1976 .prcm_reg_id = 3,
1977 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1978 .idlest_reg_id = 3,
1979 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1980 },
1981 },
1982};
1983
1984static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1985 .name = "hdq1w",
1986 .mpu_irqs = omap2_hdq1w_mpu_irqs,
1987 .main_clk = "hdq_fck",
1988 .prcm = {
1989 .omap2 = {
1990 .module_offs = CORE_MOD,
1991 .prcm_reg_id = 1,
1992 .module_bit = OMAP3430_EN_HDQ_SHIFT,
1993 .idlest_reg_id = 1,
1994 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1995 },
1996 },
1997 .class = &omap2_hdq1w_class,
1998};
1999
2000/*
2001 * '32K sync counter' class
2002 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2003 */
2004static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2005 .rev_offs = 0x0000,
2006 .sysc_offs = 0x0004,
2007 .sysc_flags = SYSC_HAS_SIDLEMODE,
2008 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2009 .sysc_fields = &omap_hwmod_sysc_type1,
2010};
2011
2012static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2013 .name = "counter",
2014 .sysc = &omap3xxx_counter_sysc,
2015};
2016
2017static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2018 .name = "counter_32k",
2019 .class = &omap3xxx_counter_hwmod_class,
2020 .clkdm_name = "wkup_clkdm",
2021 .flags = HWMOD_SWSUP_SIDLE,
2022 .main_clk = "wkup_32k_fck",
2023 .prcm = {
2024 .omap2 = {
2025 .module_offs = WKUP_MOD,
2026 .prcm_reg_id = 1,
2027 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2028 .idlest_reg_id = 1,
2029 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2030 },
2031 },
2032};
2033
2034/*
2035 * interfaces
2036 */
2037
2038/* L3 -> L4_CORE interface */
2039static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2040 .master = &omap3xxx_l3_main_hwmod,
2041 .slave = &omap3xxx_l4_core_hwmod,
2042 .user = OCP_USER_MPU | OCP_USER_SDMA,
2043};
2044
2045/* L3 -> L4_PER interface */
2046static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2047 .master = &omap3xxx_l3_main_hwmod,
2048 .slave = &omap3xxx_l4_per_hwmod,
2049 .user = OCP_USER_MPU | OCP_USER_SDMA,
2050};
2051
2052static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2053 {
2054 .pa_start = 0x68000000,
2055 .pa_end = 0x6800ffff,
2056 .flags = ADDR_TYPE_RT,
2057 },
2058 { }
2059};
2060
2061/* MPU -> L3 interface */
2062static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2063 .master = &omap3xxx_mpu_hwmod,
2064 .slave = &omap3xxx_l3_main_hwmod,
2065 .addr = omap3xxx_l3_main_addrs,
2066 .user = OCP_USER_MPU,
2067};
2068
2069/* DSS -> l3 */
2070static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2071 .master = &omap3430es1_dss_core_hwmod,
2072 .slave = &omap3xxx_l3_main_hwmod,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074};
2075
2076static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2077 .master = &omap3xxx_dss_core_hwmod,
2078 .slave = &omap3xxx_l3_main_hwmod,
2079 .fw = {
2080 .omap2 = {
2081 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2082 .flags = OMAP_FIREWALL_L3,
2083 }
2084 },
2085 .user = OCP_USER_MPU | OCP_USER_SDMA,
2086};
2087
2088/* l3_core -> usbhsotg interface */
2089static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2090 .master = &omap3xxx_usbhsotg_hwmod,
2091 .slave = &omap3xxx_l3_main_hwmod,
2092 .clk = "core_l3_ick",
2093 .user = OCP_USER_MPU,
2094};
2095
2096/* l3_core -> am35xx_usbhsotg interface */
2097static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2098 .master = &am35xx_usbhsotg_hwmod,
2099 .slave = &omap3xxx_l3_main_hwmod,
2100 .clk = "core_l3_ick",
2101 .user = OCP_USER_MPU,
2102};
2103/* L4_CORE -> L4_WKUP interface */
2104static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2105 .master = &omap3xxx_l4_core_hwmod,
2106 .slave = &omap3xxx_l4_wkup_hwmod,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* L4 CORE -> MMC1 interface */
2111static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2112 .master = &omap3xxx_l4_core_hwmod,
2113 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2114 .clk = "mmchs1_ick",
2115 .addr = omap2430_mmc1_addr_space,
2116 .user = OCP_USER_MPU | OCP_USER_SDMA,
2117 .flags = OMAP_FIREWALL_L4
2118};
2119
2120static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2121 .master = &omap3xxx_l4_core_hwmod,
2122 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2123 .clk = "mmchs1_ick",
2124 .addr = omap2430_mmc1_addr_space,
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2126 .flags = OMAP_FIREWALL_L4
2127};
2128
2129/* L4 CORE -> MMC2 interface */
2130static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2131 .master = &omap3xxx_l4_core_hwmod,
2132 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2133 .clk = "mmchs2_ick",
2134 .addr = omap2430_mmc2_addr_space,
2135 .user = OCP_USER_MPU | OCP_USER_SDMA,
2136 .flags = OMAP_FIREWALL_L4
2137};
2138
2139static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2140 .master = &omap3xxx_l4_core_hwmod,
2141 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2142 .clk = "mmchs2_ick",
2143 .addr = omap2430_mmc2_addr_space,
2144 .user = OCP_USER_MPU | OCP_USER_SDMA,
2145 .flags = OMAP_FIREWALL_L4
2146};
2147
2148/* L4 CORE -> MMC3 interface */
2149static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2150 {
2151 .pa_start = 0x480ad000,
2152 .pa_end = 0x480ad1ff,
2153 .flags = ADDR_TYPE_RT,
2154 },
2155 { }
2156};
2157
2158static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2159 .master = &omap3xxx_l4_core_hwmod,
2160 .slave = &omap3xxx_mmc3_hwmod,
2161 .clk = "mmchs3_ick",
2162 .addr = omap3xxx_mmc3_addr_space,
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164 .flags = OMAP_FIREWALL_L4
2165};
2166
2167/* L4 CORE -> UART1 interface */
2168static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2169 {
2170 .pa_start = OMAP3_UART1_BASE,
2171 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2172 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2173 },
2174 { }
2175};
2176
2177static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2178 .master = &omap3xxx_l4_core_hwmod,
2179 .slave = &omap3xxx_uart1_hwmod,
2180 .clk = "uart1_ick",
2181 .addr = omap3xxx_uart1_addr_space,
2182 .user = OCP_USER_MPU | OCP_USER_SDMA,
2183};
2184
2185/* L4 CORE -> UART2 interface */
2186static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2187 {
2188 .pa_start = OMAP3_UART2_BASE,
2189 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2190 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2191 },
2192 { }
2193};
2194
2195static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2196 .master = &omap3xxx_l4_core_hwmod,
2197 .slave = &omap3xxx_uart2_hwmod,
2198 .clk = "uart2_ick",
2199 .addr = omap3xxx_uart2_addr_space,
2200 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201};
2202
2203/* L4 PER -> UART3 interface */
2204static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2205 {
2206 .pa_start = OMAP3_UART3_BASE,
2207 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2208 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2209 },
2210 { }
2211};
2212
2213static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2214 .master = &omap3xxx_l4_per_hwmod,
2215 .slave = &omap3xxx_uart3_hwmod,
2216 .clk = "uart3_ick",
2217 .addr = omap3xxx_uart3_addr_space,
2218 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219};
2220
2221/* L4 PER -> UART4 interface */
2222static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2223 {
2224 .pa_start = OMAP3_UART4_BASE,
2225 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2226 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2227 },
2228 { }
2229};
2230
2231static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2232 .master = &omap3xxx_l4_per_hwmod,
2233 .slave = &omap36xx_uart4_hwmod,
2234 .clk = "uart4_ick",
2235 .addr = omap36xx_uart4_addr_space,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
2237};
2238
2239/* AM35xx: L4 CORE -> UART4 interface */
2240static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2241 {
2242 .pa_start = OMAP3_UART4_AM35XX_BASE,
2243 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2244 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2245 },
2246};
2247
2248static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2249 .master = &omap3xxx_l4_core_hwmod,
2250 .slave = &am35xx_uart4_hwmod,
2251 .clk = "uart4_ick",
2252 .addr = am35xx_uart4_addr_space,
2253 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254};
2255
2256/* L4 CORE -> I2C1 interface */
2257static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2258 .master = &omap3xxx_l4_core_hwmod,
2259 .slave = &omap3xxx_i2c1_hwmod,
2260 .clk = "i2c1_ick",
2261 .addr = omap2_i2c1_addr_space,
2262 .fw = {
2263 .omap2 = {
2264 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2265 .l4_prot_group = 7,
2266 .flags = OMAP_FIREWALL_L4,
2267 }
2268 },
2269 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270};
2271
2272/* L4 CORE -> I2C2 interface */
2273static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2274 .master = &omap3xxx_l4_core_hwmod,
2275 .slave = &omap3xxx_i2c2_hwmod,
2276 .clk = "i2c2_ick",
2277 .addr = omap2_i2c2_addr_space,
2278 .fw = {
2279 .omap2 = {
2280 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2281 .l4_prot_group = 7,
2282 .flags = OMAP_FIREWALL_L4,
2283 }
2284 },
2285 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286};
2287
2288/* L4 CORE -> I2C3 interface */
2289static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2290 {
2291 .pa_start = 0x48060000,
2292 .pa_end = 0x48060000 + SZ_128 - 1,
2293 .flags = ADDR_TYPE_RT,
2294 },
2295 { }
2296};
2297
2298static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2299 .master = &omap3xxx_l4_core_hwmod,
2300 .slave = &omap3xxx_i2c3_hwmod,
2301 .clk = "i2c3_ick",
2302 .addr = omap3xxx_i2c3_addr_space,
2303 .fw = {
2304 .omap2 = {
2305 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2306 .l4_prot_group = 7,
2307 .flags = OMAP_FIREWALL_L4,
2308 }
2309 },
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2311};
2312
2313/* L4 CORE -> SR1 interface */
2314static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2315 {
2316 .pa_start = OMAP34XX_SR1_BASE,
2317 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2318 .flags = ADDR_TYPE_RT,
2319 },
2320 { }
2321};
2322
2323static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2324 .master = &omap3xxx_l4_core_hwmod,
2325 .slave = &omap34xx_sr1_hwmod,
2326 .clk = "sr_l4_ick",
2327 .addr = omap3_sr1_addr_space,
2328 .user = OCP_USER_MPU,
2329};
2330
2331static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2332 .master = &omap3xxx_l4_core_hwmod,
2333 .slave = &omap36xx_sr1_hwmod,
2334 .clk = "sr_l4_ick",
2335 .addr = omap3_sr1_addr_space,
2336 .user = OCP_USER_MPU,
2337};
2338
2339/* L4 CORE -> SR1 interface */
2340static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2341 {
2342 .pa_start = OMAP34XX_SR2_BASE,
2343 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2344 .flags = ADDR_TYPE_RT,
2345 },
2346 { }
2347};
2348
2349static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2350 .master = &omap3xxx_l4_core_hwmod,
2351 .slave = &omap34xx_sr2_hwmod,
2352 .clk = "sr_l4_ick",
2353 .addr = omap3_sr2_addr_space,
2354 .user = OCP_USER_MPU,
2355};
2356
2357static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2358 .master = &omap3xxx_l4_core_hwmod,
2359 .slave = &omap36xx_sr2_hwmod,
2360 .clk = "sr_l4_ick",
2361 .addr = omap3_sr2_addr_space,
2362 .user = OCP_USER_MPU,
2363};
2364
2365static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2366 {
2367 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2368 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2369 .flags = ADDR_TYPE_RT
2370 },
2371 { }
2372};
2373
2374/* l4_core -> usbhsotg */
2375static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2376 .master = &omap3xxx_l4_core_hwmod,
2377 .slave = &omap3xxx_usbhsotg_hwmod,
2378 .clk = "l4_ick",
2379 .addr = omap3xxx_usbhsotg_addrs,
2380 .user = OCP_USER_MPU,
2381};
2382
2383static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2384 {
2385 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2386 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2387 .flags = ADDR_TYPE_RT
2388 },
2389 { }
2390};
2391
2392/* l4_core -> usbhsotg */
2393static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2394 .master = &omap3xxx_l4_core_hwmod,
2395 .slave = &am35xx_usbhsotg_hwmod,
2396 .clk = "l4_ick",
2397 .addr = am35xx_usbhsotg_addrs,
2398 .user = OCP_USER_MPU,
2399};
2400
2401/* L4_WKUP -> L4_SEC interface */
2402static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2403 .master = &omap3xxx_l4_wkup_hwmod,
2404 .slave = &omap3xxx_l4_sec_hwmod,
2405 .user = OCP_USER_MPU | OCP_USER_SDMA,
2406};
2407
2408/* IVA2 <- L3 interface */
2409static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2410 .master = &omap3xxx_l3_main_hwmod,
2411 .slave = &omap3xxx_iva_hwmod,
2412 .clk = "core_l3_ick",
2413 .user = OCP_USER_MPU | OCP_USER_SDMA,
2414};
2415
2416static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2417 {
2418 .pa_start = 0x48318000,
2419 .pa_end = 0x48318000 + SZ_1K - 1,
2420 .flags = ADDR_TYPE_RT
2421 },
2422 { }
2423};
2424
2425/* l4_wkup -> timer1 */
2426static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2427 .master = &omap3xxx_l4_wkup_hwmod,
2428 .slave = &omap3xxx_timer1_hwmod,
2429 .clk = "gpt1_ick",
2430 .addr = omap3xxx_timer1_addrs,
2431 .user = OCP_USER_MPU | OCP_USER_SDMA,
2432};
2433
2434static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2435 {
2436 .pa_start = 0x49032000,
2437 .pa_end = 0x49032000 + SZ_1K - 1,
2438 .flags = ADDR_TYPE_RT
2439 },
2440 { }
2441};
2442
2443/* l4_per -> timer2 */
2444static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2445 .master = &omap3xxx_l4_per_hwmod,
2446 .slave = &omap3xxx_timer2_hwmod,
2447 .clk = "gpt2_ick",
2448 .addr = omap3xxx_timer2_addrs,
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2450};
2451
2452static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2453 {
2454 .pa_start = 0x49034000,
2455 .pa_end = 0x49034000 + SZ_1K - 1,
2456 .flags = ADDR_TYPE_RT
2457 },
2458 { }
2459};
2460
2461/* l4_per -> timer3 */
2462static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2463 .master = &omap3xxx_l4_per_hwmod,
2464 .slave = &omap3xxx_timer3_hwmod,
2465 .clk = "gpt3_ick",
2466 .addr = omap3xxx_timer3_addrs,
2467 .user = OCP_USER_MPU | OCP_USER_SDMA,
2468};
2469
2470static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2471 {
2472 .pa_start = 0x49036000,
2473 .pa_end = 0x49036000 + SZ_1K - 1,
2474 .flags = ADDR_TYPE_RT
2475 },
2476 { }
2477};
2478
2479/* l4_per -> timer4 */
2480static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2481 .master = &omap3xxx_l4_per_hwmod,
2482 .slave = &omap3xxx_timer4_hwmod,
2483 .clk = "gpt4_ick",
2484 .addr = omap3xxx_timer4_addrs,
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2489 {
2490 .pa_start = 0x49038000,
2491 .pa_end = 0x49038000 + SZ_1K - 1,
2492 .flags = ADDR_TYPE_RT
2493 },
2494 { }
2495};
2496
2497/* l4_per -> timer5 */
2498static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2499 .master = &omap3xxx_l4_per_hwmod,
2500 .slave = &omap3xxx_timer5_hwmod,
2501 .clk = "gpt5_ick",
2502 .addr = omap3xxx_timer5_addrs,
2503 .user = OCP_USER_MPU | OCP_USER_SDMA,
2504};
2505
2506static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2507 {
2508 .pa_start = 0x4903A000,
2509 .pa_end = 0x4903A000 + SZ_1K - 1,
2510 .flags = ADDR_TYPE_RT
2511 },
2512 { }
2513};
2514
2515/* l4_per -> timer6 */
2516static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2517 .master = &omap3xxx_l4_per_hwmod,
2518 .slave = &omap3xxx_timer6_hwmod,
2519 .clk = "gpt6_ick",
2520 .addr = omap3xxx_timer6_addrs,
2521 .user = OCP_USER_MPU | OCP_USER_SDMA,
2522};
2523
2524static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2525 {
2526 .pa_start = 0x4903C000,
2527 .pa_end = 0x4903C000 + SZ_1K - 1,
2528 .flags = ADDR_TYPE_RT
2529 },
2530 { }
2531};
2532
2533/* l4_per -> timer7 */
2534static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2535 .master = &omap3xxx_l4_per_hwmod,
2536 .slave = &omap3xxx_timer7_hwmod,
2537 .clk = "gpt7_ick",
2538 .addr = omap3xxx_timer7_addrs,
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540};
2541
2542static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2543 {
2544 .pa_start = 0x4903E000,
2545 .pa_end = 0x4903E000 + SZ_1K - 1,
2546 .flags = ADDR_TYPE_RT
2547 },
2548 { }
2549};
2550
2551/* l4_per -> timer8 */
2552static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2553 .master = &omap3xxx_l4_per_hwmod,
2554 .slave = &omap3xxx_timer8_hwmod,
2555 .clk = "gpt8_ick",
2556 .addr = omap3xxx_timer8_addrs,
2557 .user = OCP_USER_MPU | OCP_USER_SDMA,
2558};
2559
2560static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2561 {
2562 .pa_start = 0x49040000,
2563 .pa_end = 0x49040000 + SZ_1K - 1,
2564 .flags = ADDR_TYPE_RT
2565 },
2566 { }
2567};
2568
2569/* l4_per -> timer9 */
2570static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2571 .master = &omap3xxx_l4_per_hwmod,
2572 .slave = &omap3xxx_timer9_hwmod,
2573 .clk = "gpt9_ick",
2574 .addr = omap3xxx_timer9_addrs,
2575 .user = OCP_USER_MPU | OCP_USER_SDMA,
2576};
2577
2578/* l4_core -> timer10 */
2579static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2580 .master = &omap3xxx_l4_core_hwmod,
2581 .slave = &omap3xxx_timer10_hwmod,
2582 .clk = "gpt10_ick",
2583 .addr = omap2_timer10_addrs,
2584 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585};
2586
2587/* l4_core -> timer11 */
2588static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2589 .master = &omap3xxx_l4_core_hwmod,
2590 .slave = &omap3xxx_timer11_hwmod,
2591 .clk = "gpt11_ick",
2592 .addr = omap2_timer11_addrs,
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2594};
2595
2596static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2597 {
2598 .pa_start = 0x48304000,
2599 .pa_end = 0x48304000 + SZ_1K - 1,
2600 .flags = ADDR_TYPE_RT
2601 },
2602 { }
2603};
2604
2605/* l4_core -> timer12 */
2606static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2607 .master = &omap3xxx_l4_sec_hwmod,
2608 .slave = &omap3xxx_timer12_hwmod,
2609 .clk = "gpt12_ick",
2610 .addr = omap3xxx_timer12_addrs,
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612};
2613
2614/* l4_wkup -> wd_timer2 */
2615static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2616 {
2617 .pa_start = 0x48314000,
2618 .pa_end = 0x4831407f,
2619 .flags = ADDR_TYPE_RT
2620 },
2621 { }
2622};
2623
2624static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2625 .master = &omap3xxx_l4_wkup_hwmod,
2626 .slave = &omap3xxx_wd_timer2_hwmod,
2627 .clk = "wdt2_ick",
2628 .addr = omap3xxx_wd_timer2_addrs,
2629 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630};
2631
2632/* l4_core -> dss */
2633static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2634 .master = &omap3xxx_l4_core_hwmod,
2635 .slave = &omap3430es1_dss_core_hwmod,
2636 .clk = "dss_ick",
2637 .addr = omap2_dss_addrs,
2638 .fw = {
2639 .omap2 = {
2640 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2641 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2642 .flags = OMAP_FIREWALL_L4,
2643 }
2644 },
2645 .user = OCP_USER_MPU | OCP_USER_SDMA,
2646};
2647
2648static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2649 .master = &omap3xxx_l4_core_hwmod,
2650 .slave = &omap3xxx_dss_core_hwmod,
2651 .clk = "dss_ick",
2652 .addr = omap2_dss_addrs,
2653 .fw = {
2654 .omap2 = {
2655 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2656 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2657 .flags = OMAP_FIREWALL_L4,
2658 }
2659 },
2660 .user = OCP_USER_MPU | OCP_USER_SDMA,
2661};
2662
2663/* l4_core -> dss_dispc */
2664static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2665 .master = &omap3xxx_l4_core_hwmod,
2666 .slave = &omap3xxx_dss_dispc_hwmod,
2667 .clk = "dss_ick",
2668 .addr = omap2_dss_dispc_addrs,
2669 .fw = {
2670 .omap2 = {
2671 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2672 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2673 .flags = OMAP_FIREWALL_L4,
2674 }
2675 },
2676 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677};
2678
2679static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2680 {
2681 .pa_start = 0x4804FC00,
2682 .pa_end = 0x4804FFFF,
2683 .flags = ADDR_TYPE_RT
2684 },
2685 { }
2686};
2687
2688/* l4_core -> dss_dsi1 */
2689static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2690 .master = &omap3xxx_l4_core_hwmod,
2691 .slave = &omap3xxx_dss_dsi1_hwmod,
2692 .clk = "dss_ick",
2693 .addr = omap3xxx_dss_dsi1_addrs,
2694 .fw = {
2695 .omap2 = {
2696 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2697 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2698 .flags = OMAP_FIREWALL_L4,
2699 }
2700 },
2701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2702};
2703
2704/* l4_core -> dss_rfbi */
2705static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2706 .master = &omap3xxx_l4_core_hwmod,
2707 .slave = &omap3xxx_dss_rfbi_hwmod,
2708 .clk = "dss_ick",
2709 .addr = omap2_dss_rfbi_addrs,
2710 .fw = {
2711 .omap2 = {
2712 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2713 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2714 .flags = OMAP_FIREWALL_L4,
2715 }
2716 },
2717 .user = OCP_USER_MPU | OCP_USER_SDMA,
2718};
2719
2720/* l4_core -> dss_venc */
2721static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2722 .master = &omap3xxx_l4_core_hwmod,
2723 .slave = &omap3xxx_dss_venc_hwmod,
2724 .clk = "dss_ick",
2725 .addr = omap2_dss_venc_addrs,
2726 .fw = {
2727 .omap2 = {
2728 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2729 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2730 .flags = OMAP_FIREWALL_L4,
2731 }
2732 },
2733 .flags = OCPIF_SWSUP_IDLE,
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735};
2736
2737/* l4_wkup -> gpio1 */
2738static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2739 {
2740 .pa_start = 0x48310000,
2741 .pa_end = 0x483101ff,
2742 .flags = ADDR_TYPE_RT
2743 },
2744 { }
2745};
2746
2747static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2748 .master = &omap3xxx_l4_wkup_hwmod,
2749 .slave = &omap3xxx_gpio1_hwmod,
2750 .addr = omap3xxx_gpio1_addrs,
2751 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752};
2753
2754/* l4_per -> gpio2 */
2755static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2756 {
2757 .pa_start = 0x49050000,
2758 .pa_end = 0x490501ff,
2759 .flags = ADDR_TYPE_RT
2760 },
2761 { }
2762};
2763
2764static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2765 .master = &omap3xxx_l4_per_hwmod,
2766 .slave = &omap3xxx_gpio2_hwmod,
2767 .addr = omap3xxx_gpio2_addrs,
2768 .user = OCP_USER_MPU | OCP_USER_SDMA,
2769};
2770
2771/* l4_per -> gpio3 */
2772static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2773 {
2774 .pa_start = 0x49052000,
2775 .pa_end = 0x490521ff,
2776 .flags = ADDR_TYPE_RT
2777 },
2778 { }
2779};
2780
2781static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2782 .master = &omap3xxx_l4_per_hwmod,
2783 .slave = &omap3xxx_gpio3_hwmod,
2784 .addr = omap3xxx_gpio3_addrs,
2785 .user = OCP_USER_MPU | OCP_USER_SDMA,
2786};
2787
2788/* l4_per -> gpio4 */
2789static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2790 {
2791 .pa_start = 0x49054000,
2792 .pa_end = 0x490541ff,
2793 .flags = ADDR_TYPE_RT
2794 },
2795 { }
2796};
2797
2798static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2799 .master = &omap3xxx_l4_per_hwmod,
2800 .slave = &omap3xxx_gpio4_hwmod,
2801 .addr = omap3xxx_gpio4_addrs,
2802 .user = OCP_USER_MPU | OCP_USER_SDMA,
2803};
2804
2805/* l4_per -> gpio5 */
2806static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2807 {
2808 .pa_start = 0x49056000,
2809 .pa_end = 0x490561ff,
2810 .flags = ADDR_TYPE_RT
2811 },
2812 { }
2813};
2814
2815static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2816 .master = &omap3xxx_l4_per_hwmod,
2817 .slave = &omap3xxx_gpio5_hwmod,
2818 .addr = omap3xxx_gpio5_addrs,
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2820};
2821
2822/* l4_per -> gpio6 */
2823static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2824 {
2825 .pa_start = 0x49058000,
2826 .pa_end = 0x490581ff,
2827 .flags = ADDR_TYPE_RT
2828 },
2829 { }
2830};
2831
2832static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2833 .master = &omap3xxx_l4_per_hwmod,
2834 .slave = &omap3xxx_gpio6_hwmod,
2835 .addr = omap3xxx_gpio6_addrs,
2836 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837};
2838
2839/* dma_system -> L3 */
2840static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2841 .master = &omap3xxx_dma_system_hwmod,
2842 .slave = &omap3xxx_l3_main_hwmod,
2843 .clk = "core_l3_ick",
2844 .user = OCP_USER_MPU | OCP_USER_SDMA,
2845};
2846
2847static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2848 {
2849 .pa_start = 0x48056000,
2850 .pa_end = 0x48056fff,
2851 .flags = ADDR_TYPE_RT
2852 },
2853 { }
2854};
2855
2856/* l4_cfg -> dma_system */
2857static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2858 .master = &omap3xxx_l4_core_hwmod,
2859 .slave = &omap3xxx_dma_system_hwmod,
2860 .clk = "core_l4_ick",
2861 .addr = omap3xxx_dma_system_addrs,
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2863};
2864
2865static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2866 {
2867 .name = "mpu",
2868 .pa_start = 0x48074000,
2869 .pa_end = 0x480740ff,
2870 .flags = ADDR_TYPE_RT
2871 },
2872 { }
2873};
2874
2875/* l4_core -> mcbsp1 */
2876static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2877 .master = &omap3xxx_l4_core_hwmod,
2878 .slave = &omap3xxx_mcbsp1_hwmod,
2879 .clk = "mcbsp1_ick",
2880 .addr = omap3xxx_mcbsp1_addrs,
2881 .user = OCP_USER_MPU | OCP_USER_SDMA,
2882};
2883
2884static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2885 {
2886 .name = "mpu",
2887 .pa_start = 0x49022000,
2888 .pa_end = 0x490220ff,
2889 .flags = ADDR_TYPE_RT
2890 },
2891 { }
2892};
2893
2894/* l4_per -> mcbsp2 */
2895static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2896 .master = &omap3xxx_l4_per_hwmod,
2897 .slave = &omap3xxx_mcbsp2_hwmod,
2898 .clk = "mcbsp2_ick",
2899 .addr = omap3xxx_mcbsp2_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2901};
2902
2903static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2904 {
2905 .name = "mpu",
2906 .pa_start = 0x49024000,
2907 .pa_end = 0x490240ff,
2908 .flags = ADDR_TYPE_RT
2909 },
2910 { }
2911};
2912
2913/* l4_per -> mcbsp3 */
2914static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2915 .master = &omap3xxx_l4_per_hwmod,
2916 .slave = &omap3xxx_mcbsp3_hwmod,
2917 .clk = "mcbsp3_ick",
2918 .addr = omap3xxx_mcbsp3_addrs,
2919 .user = OCP_USER_MPU | OCP_USER_SDMA,
2920};
2921
2922static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2923 {
2924 .name = "mpu",
2925 .pa_start = 0x49026000,
2926 .pa_end = 0x490260ff,
2927 .flags = ADDR_TYPE_RT
2928 },
2929 { }
2930};
2931
2932/* l4_per -> mcbsp4 */
2933static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2934 .master = &omap3xxx_l4_per_hwmod,
2935 .slave = &omap3xxx_mcbsp4_hwmod,
2936 .clk = "mcbsp4_ick",
2937 .addr = omap3xxx_mcbsp4_addrs,
2938 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939};
2940
2941static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2942 {
2943 .name = "mpu",
2944 .pa_start = 0x48096000,
2945 .pa_end = 0x480960ff,
2946 .flags = ADDR_TYPE_RT
2947 },
2948 { }
2949};
2950
2951/* l4_core -> mcbsp5 */
2952static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2953 .master = &omap3xxx_l4_core_hwmod,
2954 .slave = &omap3xxx_mcbsp5_hwmod,
2955 .clk = "mcbsp5_ick",
2956 .addr = omap3xxx_mcbsp5_addrs,
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2958};
2959
2960static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2961 {
2962 .name = "sidetone",
2963 .pa_start = 0x49028000,
2964 .pa_end = 0x490280ff,
2965 .flags = ADDR_TYPE_RT
2966 },
2967 { }
2968};
2969
2970/* l4_per -> mcbsp2_sidetone */
2971static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2972 .master = &omap3xxx_l4_per_hwmod,
2973 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2974 .clk = "mcbsp2_ick",
2975 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2976 .user = OCP_USER_MPU,
2977};
2978
2979static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2980 {
2981 .name = "sidetone",
2982 .pa_start = 0x4902A000,
2983 .pa_end = 0x4902A0ff,
2984 .flags = ADDR_TYPE_RT
2985 },
2986 { }
2987};
2988
2989/* l4_per -> mcbsp3_sidetone */
2990static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2991 .master = &omap3xxx_l4_per_hwmod,
2992 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2993 .clk = "mcbsp3_ick",
2994 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2995 .user = OCP_USER_MPU,
2996};
2997
2998static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2999 {
3000 .pa_start = 0x48094000,
3001 .pa_end = 0x480941ff,
3002 .flags = ADDR_TYPE_RT,
3003 },
3004 { }
3005};
3006
3007/* l4_core -> mailbox */
3008static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3009 .master = &omap3xxx_l4_core_hwmod,
3010 .slave = &omap3xxx_mailbox_hwmod,
3011 .addr = omap3xxx_mailbox_addrs,
3012 .user = OCP_USER_MPU | OCP_USER_SDMA,
3013};
3014
3015/* l4 core -> mcspi1 interface */
3016static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3017 .master = &omap3xxx_l4_core_hwmod,
3018 .slave = &omap34xx_mcspi1,
3019 .clk = "mcspi1_ick",
3020 .addr = omap2_mcspi1_addr_space,
3021 .user = OCP_USER_MPU | OCP_USER_SDMA,
3022};
3023
3024/* l4 core -> mcspi2 interface */
3025static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3026 .master = &omap3xxx_l4_core_hwmod,
3027 .slave = &omap34xx_mcspi2,
3028 .clk = "mcspi2_ick",
3029 .addr = omap2_mcspi2_addr_space,
3030 .user = OCP_USER_MPU | OCP_USER_SDMA,
3031};
3032
3033/* l4 core -> mcspi3 interface */
3034static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3035 .master = &omap3xxx_l4_core_hwmod,
3036 .slave = &omap34xx_mcspi3,
3037 .clk = "mcspi3_ick",
3038 .addr = omap2430_mcspi3_addr_space,
3039 .user = OCP_USER_MPU | OCP_USER_SDMA,
3040};
3041
3042/* l4 core -> mcspi4 interface */
3043static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3044 {
3045 .pa_start = 0x480ba000,
3046 .pa_end = 0x480ba0ff,
3047 .flags = ADDR_TYPE_RT,
3048 },
3049 { }
3050};
3051
3052static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3053 .master = &omap3xxx_l4_core_hwmod,
3054 .slave = &omap34xx_mcspi4,
3055 .clk = "mcspi4_ick",
3056 .addr = omap34xx_mcspi4_addr_space,
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3058};
3059
3060static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3061 .master = &omap3xxx_usb_host_hs_hwmod,
3062 .slave = &omap3xxx_l3_main_hwmod,
3063 .clk = "core_l3_ick",
3064 .user = OCP_USER_MPU,
3065};
3066
3067static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3068 {
3069 .name = "uhh",
3070 .pa_start = 0x48064000,
3071 .pa_end = 0x480643ff,
3072 .flags = ADDR_TYPE_RT
3073 },
3074 {
3075 .name = "ohci",
3076 .pa_start = 0x48064400,
3077 .pa_end = 0x480647ff,
3078 },
3079 {
3080 .name = "ehci",
3081 .pa_start = 0x48064800,
3082 .pa_end = 0x48064cff,
3083 },
3084 {}
3085};
3086
3087static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3088 .master = &omap3xxx_l4_core_hwmod,
3089 .slave = &omap3xxx_usb_host_hs_hwmod,
3090 .clk = "usbhost_ick",
3091 .addr = omap3xxx_usb_host_hs_addrs,
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3093};
3094
3504static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3095static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3505 { 3096 {
3506 .name = "tll", 3097 .name = "tll",
@@ -3519,183 +3110,187 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3519 .user = OCP_USER_MPU | OCP_USER_SDMA, 3110 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520}; 3111};
3521 3112
3522static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = { 3113/* l4_core -> hdq1w interface */
3523 &omap3xxx_l4_core__usb_tll_hs, 3114static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3115 .master = &omap3xxx_l4_core_hwmod,
3116 .slave = &omap3xxx_hdq1w_hwmod,
3117 .clk = "hdq_ick",
3118 .addr = omap2_hdq1w_addr_space,
3119 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3524}; 3121};
3525 3122
3526static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 3123/* l4_wkup -> 32ksync_counter */
3527 .name = "usb_tll_hs", 3124static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3528 .class = &omap3xxx_usb_tll_hs_hwmod_class, 3125 {
3529 .clkdm_name = "l3_init_clkdm", 3126 .pa_start = 0x48320000,
3530 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 3127 .pa_end = 0x4832001f,
3531 .main_clk = "usbtll_fck", 3128 .flags = ADDR_TYPE_RT
3532 .prcm = {
3533 .omap2 = {
3534 .module_offs = CORE_MOD,
3535 .prcm_reg_id = 3,
3536 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3537 .idlest_reg_id = 3,
3538 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
3539 },
3540 }, 3129 },
3541 .slaves = omap3xxx_usb_tll_hs_slaves, 3130 { }
3542 .slaves_cnt = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves), 3131};
3543};
3544
3545static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3546 &omap3xxx_l3_main_hwmod,
3547 &omap3xxx_l4_core_hwmod,
3548 &omap3xxx_l4_per_hwmod,
3549 &omap3xxx_l4_wkup_hwmod,
3550 &omap3xxx_mmc3_hwmod,
3551 &omap3xxx_mpu_hwmod,
3552
3553 &omap3xxx_timer1_hwmod,
3554 &omap3xxx_timer2_hwmod,
3555 &omap3xxx_timer3_hwmod,
3556 &omap3xxx_timer4_hwmod,
3557 &omap3xxx_timer5_hwmod,
3558 &omap3xxx_timer6_hwmod,
3559 &omap3xxx_timer7_hwmod,
3560 &omap3xxx_timer8_hwmod,
3561 &omap3xxx_timer9_hwmod,
3562 &omap3xxx_timer10_hwmod,
3563 &omap3xxx_timer11_hwmod,
3564
3565 &omap3xxx_wd_timer2_hwmod,
3566 &omap3xxx_uart1_hwmod,
3567 &omap3xxx_uart2_hwmod,
3568 &omap3xxx_uart3_hwmod,
3569
3570 /* i2c class */
3571 &omap3xxx_i2c1_hwmod,
3572 &omap3xxx_i2c2_hwmod,
3573 &omap3xxx_i2c3_hwmod,
3574
3575 /* gpio class */
3576 &omap3xxx_gpio1_hwmod,
3577 &omap3xxx_gpio2_hwmod,
3578 &omap3xxx_gpio3_hwmod,
3579 &omap3xxx_gpio4_hwmod,
3580 &omap3xxx_gpio5_hwmod,
3581 &omap3xxx_gpio6_hwmod,
3582
3583 /* dma_system class*/
3584 &omap3xxx_dma_system_hwmod,
3585
3586 /* mcbsp class */
3587 &omap3xxx_mcbsp1_hwmod,
3588 &omap3xxx_mcbsp2_hwmod,
3589 &omap3xxx_mcbsp3_hwmod,
3590 &omap3xxx_mcbsp4_hwmod,
3591 &omap3xxx_mcbsp5_hwmod,
3592 &omap3xxx_mcbsp2_sidetone_hwmod,
3593 &omap3xxx_mcbsp3_sidetone_hwmod,
3594
3595
3596 /* mcspi class */
3597 &omap34xx_mcspi1,
3598 &omap34xx_mcspi2,
3599 &omap34xx_mcspi3,
3600 &omap34xx_mcspi4,
3601 3132
3133static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3134 .master = &omap3xxx_l4_wkup_hwmod,
3135 .slave = &omap3xxx_counter_32k_hwmod,
3136 .clk = "omap_32ksync_ick",
3137 .addr = omap3xxx_counter_32k_addrs,
3138 .user = OCP_USER_MPU | OCP_USER_SDMA,
3139};
3140
3141static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3142 &omap3xxx_l3_main__l4_core,
3143 &omap3xxx_l3_main__l4_per,
3144 &omap3xxx_mpu__l3_main,
3145 &omap3xxx_l4_core__l4_wkup,
3146 &omap3xxx_l4_core__mmc3,
3147 &omap3_l4_core__uart1,
3148 &omap3_l4_core__uart2,
3149 &omap3_l4_per__uart3,
3150 &omap3_l4_core__i2c1,
3151 &omap3_l4_core__i2c2,
3152 &omap3_l4_core__i2c3,
3153 &omap3xxx_l4_wkup__l4_sec,
3154 &omap3xxx_l4_wkup__timer1,
3155 &omap3xxx_l4_per__timer2,
3156 &omap3xxx_l4_per__timer3,
3157 &omap3xxx_l4_per__timer4,
3158 &omap3xxx_l4_per__timer5,
3159 &omap3xxx_l4_per__timer6,
3160 &omap3xxx_l4_per__timer7,
3161 &omap3xxx_l4_per__timer8,
3162 &omap3xxx_l4_per__timer9,
3163 &omap3xxx_l4_core__timer10,
3164 &omap3xxx_l4_core__timer11,
3165 &omap3xxx_l4_wkup__wd_timer2,
3166 &omap3xxx_l4_wkup__gpio1,
3167 &omap3xxx_l4_per__gpio2,
3168 &omap3xxx_l4_per__gpio3,
3169 &omap3xxx_l4_per__gpio4,
3170 &omap3xxx_l4_per__gpio5,
3171 &omap3xxx_l4_per__gpio6,
3172 &omap3xxx_dma_system__l3,
3173 &omap3xxx_l4_core__dma_system,
3174 &omap3xxx_l4_core__mcbsp1,
3175 &omap3xxx_l4_per__mcbsp2,
3176 &omap3xxx_l4_per__mcbsp3,
3177 &omap3xxx_l4_per__mcbsp4,
3178 &omap3xxx_l4_core__mcbsp5,
3179 &omap3xxx_l4_per__mcbsp2_sidetone,
3180 &omap3xxx_l4_per__mcbsp3_sidetone,
3181 &omap34xx_l4_core__mcspi1,
3182 &omap34xx_l4_core__mcspi2,
3183 &omap34xx_l4_core__mcspi3,
3184 &omap34xx_l4_core__mcspi4,
3185 &omap3xxx_l4_wkup__counter_32k,
3602 NULL, 3186 NULL,
3603}; 3187};
3604 3188
3605/* GP-only hwmods */ 3189/* GP-only hwmod links */
3606static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = { 3190static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3607 &omap3xxx_timer12_hwmod, 3191 &omap3xxx_l4_sec__timer12,
3608 NULL 3192 NULL
3609}; 3193};
3610 3194
3611/* 3430ES1-only hwmods */ 3195/* 3430ES1-only hwmod links */
3612static __initdata struct omap_hwmod *omap3430es1_hwmods[] = { 3196static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3613 &omap3430es1_dss_core_hwmod, 3197 &omap3430es1_dss__l3,
3198 &omap3430es1_l4_core__dss,
3614 NULL 3199 NULL
3615}; 3200};
3616 3201
3617/* 3430ES2+-only hwmods */ 3202/* 3430ES2+-only hwmod links */
3618static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = { 3203static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3619 &omap3xxx_dss_core_hwmod, 3204 &omap3xxx_dss__l3,
3620 &omap3xxx_usbhsotg_hwmod, 3205 &omap3xxx_l4_core__dss,
3621 &omap3xxx_usb_host_hs_hwmod, 3206 &omap3xxx_usbhsotg__l3,
3622 &omap3xxx_usb_tll_hs_hwmod, 3207 &omap3xxx_l4_core__usbhsotg,
3208 &omap3xxx_usb_host_hs__l3_main_2,
3209 &omap3xxx_l4_core__usb_host_hs,
3210 &omap3xxx_l4_core__usb_tll_hs,
3623 NULL 3211 NULL
3624}; 3212};
3625 3213
3626/* <= 3430ES3-only hwmods */ 3214/* <= 3430ES3-only hwmod links */
3627static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = { 3215static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3628 &omap3xxx_pre_es3_mmc1_hwmod, 3216 &omap3xxx_l4_core__pre_es3_mmc1,
3629 &omap3xxx_pre_es3_mmc2_hwmod, 3217 &omap3xxx_l4_core__pre_es3_mmc2,
3630 NULL 3218 NULL
3631}; 3219};
3632 3220
3633/* 3430ES3+-only hwmods */ 3221/* 3430ES3+-only hwmod links */
3634static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = { 3222static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3635 &omap3xxx_es3plus_mmc1_hwmod, 3223 &omap3xxx_l4_core__es3plus_mmc1,
3636 &omap3xxx_es3plus_mmc2_hwmod, 3224 &omap3xxx_l4_core__es3plus_mmc2,
3637 NULL 3225 NULL
3638}; 3226};
3639 3227
3640/* 34xx-only hwmods (all ES revisions) */ 3228/* 34xx-only hwmod links (all ES revisions) */
3641static __initdata struct omap_hwmod *omap34xx_hwmods[] = { 3229static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3642 &omap3xxx_iva_hwmod, 3230 &omap3xxx_l3__iva,
3643 &omap34xx_sr1_hwmod, 3231 &omap34xx_l4_core__sr1,
3644 &omap34xx_sr2_hwmod, 3232 &omap34xx_l4_core__sr2,
3645 &omap3xxx_mailbox_hwmod, 3233 &omap3xxx_l4_core__mailbox,
3234 &omap3xxx_l4_core__hdq1w,
3646 NULL 3235 NULL
3647}; 3236};
3648 3237
3649/* 36xx-only hwmods (all ES revisions) */ 3238/* 36xx-only hwmod links (all ES revisions) */
3650static __initdata struct omap_hwmod *omap36xx_hwmods[] = { 3239static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3651 &omap3xxx_iva_hwmod, 3240 &omap3xxx_l3__iva,
3652 &omap3xxx_uart4_hwmod, 3241 &omap36xx_l4_per__uart4,
3653 &omap3xxx_dss_core_hwmod, 3242 &omap3xxx_dss__l3,
3654 &omap36xx_sr1_hwmod, 3243 &omap3xxx_l4_core__dss,
3655 &omap36xx_sr2_hwmod, 3244 &omap36xx_l4_core__sr1,
3656 &omap3xxx_usbhsotg_hwmod, 3245 &omap36xx_l4_core__sr2,
3657 &omap3xxx_mailbox_hwmod, 3246 &omap3xxx_usbhsotg__l3,
3658 &omap3xxx_usb_host_hs_hwmod, 3247 &omap3xxx_l4_core__usbhsotg,
3659 &omap3xxx_usb_tll_hs_hwmod, 3248 &omap3xxx_l4_core__mailbox,
3660 &omap3xxx_es3plus_mmc1_hwmod, 3249 &omap3xxx_usb_host_hs__l3_main_2,
3661 &omap3xxx_es3plus_mmc2_hwmod, 3250 &omap3xxx_l4_core__usb_host_hs,
3251 &omap3xxx_l4_core__usb_tll_hs,
3252 &omap3xxx_l4_core__es3plus_mmc1,
3253 &omap3xxx_l4_core__es3plus_mmc2,
3254 &omap3xxx_l4_core__hdq1w,
3662 NULL 3255 NULL
3663}; 3256};
3664 3257
3665static __initdata struct omap_hwmod *am35xx_hwmods[] = { 3258static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3666 &omap3xxx_dss_core_hwmod, /* XXX ??? */ 3259 &omap3xxx_dss__l3,
3667 &am35xx_usbhsotg_hwmod, 3260 &omap3xxx_l4_core__dss,
3668 &am35xx_uart4_hwmod, 3261 &am35xx_usbhsotg__l3,
3669 &omap3xxx_usb_host_hs_hwmod, 3262 &am35xx_l4_core__usbhsotg,
3670 &omap3xxx_usb_tll_hs_hwmod, 3263 &am35xx_l4_core__uart4,
3671 &omap3xxx_es3plus_mmc1_hwmod, 3264 &omap3xxx_usb_host_hs__l3_main_2,
3672 &omap3xxx_es3plus_mmc2_hwmod, 3265 &omap3xxx_l4_core__usb_host_hs,
3266 &omap3xxx_l4_core__usb_tll_hs,
3267 &omap3xxx_l4_core__es3plus_mmc1,
3268 &omap3xxx_l4_core__es3plus_mmc2,
3673 NULL 3269 NULL
3674}; 3270};
3675 3271
3676static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = { 3272static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3677 /* dss class */ 3273 &omap3xxx_l4_core__dss_dispc,
3678 &omap3xxx_dss_dispc_hwmod, 3274 &omap3xxx_l4_core__dss_dsi1,
3679 &omap3xxx_dss_dsi1_hwmod, 3275 &omap3xxx_l4_core__dss_rfbi,
3680 &omap3xxx_dss_rfbi_hwmod, 3276 &omap3xxx_l4_core__dss_venc,
3681 &omap3xxx_dss_venc_hwmod,
3682 NULL 3277 NULL
3683}; 3278};
3684 3279
3685int __init omap3xxx_hwmod_init(void) 3280int __init omap3xxx_hwmod_init(void)
3686{ 3281{
3687 int r; 3282 int r;
3688 struct omap_hwmod **h = NULL; 3283 struct omap_hwmod_ocp_if **h = NULL;
3689 unsigned int rev; 3284 unsigned int rev;
3690 3285
3691 /* Register hwmods common to all OMAP3 */ 3286 /* Register hwmod links common to all OMAP3 */
3692 r = omap_hwmod_register(omap3xxx_hwmods); 3287 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3693 if (r < 0) 3288 if (r < 0)
3694 return r; 3289 return r;
3695 3290
3696 /* Register GP-only hwmods. */ 3291 /* Register GP-only hwmod links. */
3697 if (omap_type() == OMAP2_DEVICE_TYPE_GP) { 3292 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3698 r = omap_hwmod_register(omap3xxx_gp_hwmods); 3293 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3699 if (r < 0) 3294 if (r < 0)
3700 return r; 3295 return r;
3701 } 3296 }
@@ -3703,43 +3298,43 @@ int __init omap3xxx_hwmod_init(void)
3703 rev = omap_rev(); 3298 rev = omap_rev();
3704 3299
3705 /* 3300 /*
3706 * Register hwmods common to individual OMAP3 families, all 3301 * Register hwmod links common to individual OMAP3 families, all
3707 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3302 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3708 * All possible revisions should be included in this conditional. 3303 * All possible revisions should be included in this conditional.
3709 */ 3304 */
3710 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3305 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3711 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3306 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3712 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3307 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3713 h = omap34xx_hwmods; 3308 h = omap34xx_hwmod_ocp_ifs;
3714 } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) { 3309 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3715 h = am35xx_hwmods; 3310 h = am35xx_hwmod_ocp_ifs;
3716 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3311 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3717 rev == OMAP3630_REV_ES1_2) { 3312 rev == OMAP3630_REV_ES1_2) {
3718 h = omap36xx_hwmods; 3313 h = omap36xx_hwmod_ocp_ifs;
3719 } else { 3314 } else {
3720 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3315 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3721 return -EINVAL; 3316 return -EINVAL;
3722 }; 3317 };
3723 3318
3724 r = omap_hwmod_register(h); 3319 r = omap_hwmod_register_links(h);
3725 if (r < 0) 3320 if (r < 0)
3726 return r; 3321 return r;
3727 3322
3728 /* 3323 /*
3729 * Register hwmods specific to certain ES levels of a 3324 * Register hwmod links specific to certain ES levels of a
3730 * particular family of silicon (e.g., 34xx ES1.0) 3325 * particular family of silicon (e.g., 34xx ES1.0)
3731 */ 3326 */
3732 h = NULL; 3327 h = NULL;
3733 if (rev == OMAP3430_REV_ES1_0) { 3328 if (rev == OMAP3430_REV_ES1_0) {
3734 h = omap3430es1_hwmods; 3329 h = omap3430es1_hwmod_ocp_ifs;
3735 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3330 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3736 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3331 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3737 rev == OMAP3430_REV_ES3_1_2) { 3332 rev == OMAP3430_REV_ES3_1_2) {
3738 h = omap3430es2plus_hwmods; 3333 h = omap3430es2plus_hwmod_ocp_ifs;
3739 }; 3334 };
3740 3335
3741 if (h) { 3336 if (h) {
3742 r = omap_hwmod_register(h); 3337 r = omap_hwmod_register_links(h);
3743 if (r < 0) 3338 if (r < 0)
3744 return r; 3339 return r;
3745 } 3340 }
@@ -3747,29 +3342,29 @@ int __init omap3xxx_hwmod_init(void)
3747 h = NULL; 3342 h = NULL;
3748 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3343 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3749 rev == OMAP3430_REV_ES2_1) { 3344 rev == OMAP3430_REV_ES2_1) {
3750 h = omap3430_pre_es3_hwmods; 3345 h = omap3430_pre_es3_hwmod_ocp_ifs;
3751 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3346 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3752 rev == OMAP3430_REV_ES3_1_2) { 3347 rev == OMAP3430_REV_ES3_1_2) {
3753 h = omap3430_es3plus_hwmods; 3348 h = omap3430_es3plus_hwmod_ocp_ifs;
3754 }; 3349 };
3755 3350
3756 if (h) 3351 if (h)
3757 r = omap_hwmod_register(h); 3352 r = omap_hwmod_register_links(h);
3758 if (r < 0) 3353 if (r < 0)
3759 return r; 3354 return r;
3760 3355
3761 /* 3356 /*
3762 * DSS code presumes that dss_core hwmod is handled first, 3357 * DSS code presumes that dss_core hwmod is handled first,
3763 * _before_ any other DSS related hwmods so register common 3358 * _before_ any other DSS related hwmods so register common
3764 * DSS hwmods last to ensure that dss_core is already registered. 3359 * DSS hwmod links last to ensure that dss_core is already
3765 * Otherwise some change things may happen, for ex. if dispc 3360 * registered. Otherwise some change things may happen, for
3766 * is handled before dss_core and DSS is enabled in bootloader 3361 * ex. if dispc is handled before dss_core and DSS is enabled
3767 * DIPSC will be reset with outputs enabled which sometimes leads 3362 * in bootloader DISPC will be reset with outputs enabled
3768 * to unrecoverable L3 error. 3363 * which sometimes leads to unrecoverable L3 error. XXX The
3769 * XXX The long-term fix to this is to ensure modules are set up 3364 * long-term fix to this is to ensure hwmods are set up in
3770 * in dependency order in the hwmod core code. 3365 * dependency order in the hwmod core code.
3771 */ 3366 */
3772 r = omap_hwmod_register(omap3xxx_dss_hwmods); 3367 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3773 3368
3774 return r; 3369 return r;
3775} 3370}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 13:51:20 -0500