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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-01-08 16:29:09 -0500
committerKevin Hilman <khilman@ti.com>2011-12-08 14:29:01 -0500
commit5e94c6e33e7c4726ef09f46c267e9ca232c5148a (patch)
treeea13686167925b0a3f9e67ae02817cbb6986e0fc /arch/arm/mach-omap2/omap4-sar-layout.h
parent0f3cf2ec81aeb4747624954bae2cc8decc48e12f (diff)
ARM: OMAP4: PM: Add L2X0 cache lowpower support
When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0 necessary maintenance operations and context restoration in the low power code. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-sar-layout.h')
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index aa14a8dd2505..fe5b545ad443 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -23,6 +23,10 @@
23#define SCU_OFFSET0 0xd00 23#define SCU_OFFSET0 0xd00
24#define SCU_OFFSET1 0xd04 24#define SCU_OFFSET1 0xd04
25#define OMAP_TYPE_OFFSET 0xd10 25#define OMAP_TYPE_OFFSET 0xd10
26#define L2X0_SAVE_OFFSET0 0xd14
27#define L2X0_SAVE_OFFSET1 0xd18
28#define L2X0_AUXCTRL_OFFSET 0xd1c
29#define L2X0_PREFETCH_CTRL_OFFSET 0xd20
26 30
27/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ 31/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
28#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 32#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04