diff options
author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-02-06 07:51:53 -0500 |
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committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-03-19 03:27:01 -0400 |
commit | 13fcef9431660ebdfbd6f2a0a6ee9809bf695804 (patch) | |
tree | d987255989f673fc02ebf0eb32832efa00fef9dc /arch/arm/mach-omap2/omap4-sar-layout.h | |
parent | da0e02a1e4a6348505cfe0cbb0d3a2717a2b5476 (diff) |
ARM: OMAP5: Update SAR memory layout for WakeupGen
On OMAP5 es2 WakeupGen SAR register layout offset have changed.
Update the layout accordingly.
Reported-by: Menon, Nishanth <nm@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-sar-layout.h')
-rw-r--r-- | arch/arm/mach-omap2/omap4-sar-layout.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h index e170fe803b04..937417523b8e 100644 --- a/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/arch/arm/mach-omap2/omap4-sar-layout.h | |||
@@ -48,13 +48,13 @@ | |||
48 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 | 48 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 |
49 | 49 | ||
50 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ | 50 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ |
51 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) | 51 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) |
52 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) | 52 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) |
53 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) | 53 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) |
54 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) | 54 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) |
55 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) | 55 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) |
56 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) | 56 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) |
57 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) | 57 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) |
58 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) | 58 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) |
59 | 59 | ||
60 | #endif | 60 | #endif |