diff options
| author | Afzal Mohammed <afzal@ti.com> | 2013-10-09 03:12:33 -0400 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2013-10-22 10:28:12 -0400 |
| commit | 6246cd06d81f0310d09f3cc66349d5a943cc4b02 (patch) | |
| tree | 1d7be2532a5c669de77a48372e1fdbbaf8f3afaf /arch/arm/mach-omap2/omap-wakeupgen.c | |
| parent | 8ff875e7f93e900e7a7e78f1c9c05a22b33c27cf (diff) | |
ARM: OMAP2+: wakeupgen: AM43x adaptation
AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep
default values as earlier, if am43x is detected, update interrupts and
banks accordingly.
Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen
is done only for the single existing cpu, existing code assumes that
there are two cpu's.
If bitmask is cleared in wakeupgen for the nonexistent second cpu,
an imprecise abort happens as soon as Kernel switches to user space.
It was rootcaused by Sekhar Nori <nsekhar@ti.com>.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap-wakeupgen.c')
| -rw-r--r-- | arch/arm/mach-omap2/omap-wakeupgen.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 813c61558a5f..3664562f9148 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c | |||
| @@ -33,8 +33,12 @@ | |||
| 33 | #include "omap4-sar-layout.h" | 33 | #include "omap4-sar-layout.h" |
| 34 | #include "common.h" | 34 | #include "common.h" |
| 35 | 35 | ||
| 36 | #define MAX_NR_REG_BANKS 5 | 36 | #define AM43XX_NR_REG_BANKS 7 |
| 37 | #define MAX_IRQS 160 | 37 | #define AM43XX_IRQS 224 |
| 38 | #define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS | ||
| 39 | #define MAX_IRQS AM43XX_IRQS | ||
| 40 | #define DEFAULT_NR_REG_BANKS 5 | ||
| 41 | #define DEFAULT_IRQS 160 | ||
| 38 | #define WKG_MASK_ALL 0x00000000 | 42 | #define WKG_MASK_ALL 0x00000000 |
| 39 | #define WKG_UNMASK_ALL 0xffffffff | 43 | #define WKG_UNMASK_ALL 0xffffffff |
| 40 | #define CPU_ENA_OFFSET 0x400 | 44 | #define CPU_ENA_OFFSET 0x400 |
| @@ -47,8 +51,8 @@ static void __iomem *wakeupgen_base; | |||
| 47 | static void __iomem *sar_base; | 51 | static void __iomem *sar_base; |
| 48 | static DEFINE_RAW_SPINLOCK(wakeupgen_lock); | 52 | static DEFINE_RAW_SPINLOCK(wakeupgen_lock); |
| 49 | static unsigned int irq_target_cpu[MAX_IRQS]; | 53 | static unsigned int irq_target_cpu[MAX_IRQS]; |
| 50 | static unsigned int irq_banks = MAX_NR_REG_BANKS; | 54 | static unsigned int irq_banks = DEFAULT_NR_REG_BANKS; |
| 51 | static unsigned int max_irqs = MAX_IRQS; | 55 | static unsigned int max_irqs = DEFAULT_IRQS; |
| 52 | static unsigned int omap_secure_apis; | 56 | static unsigned int omap_secure_apis; |
| 53 | 57 | ||
| 54 | /* | 58 | /* |
| @@ -418,12 +422,16 @@ int __init omap_wakeupgen_init(void) | |||
| 418 | irq_banks = OMAP4_NR_BANKS; | 422 | irq_banks = OMAP4_NR_BANKS; |
| 419 | max_irqs = OMAP4_NR_IRQS; | 423 | max_irqs = OMAP4_NR_IRQS; |
| 420 | omap_secure_apis = 1; | 424 | omap_secure_apis = 1; |
| 425 | } else if (soc_is_am43xx()) { | ||
| 426 | irq_banks = AM43XX_NR_REG_BANKS; | ||
| 427 | max_irqs = AM43XX_IRQS; | ||
| 421 | } | 428 | } |
| 422 | 429 | ||
| 423 | /* Clear all IRQ bitmasks at wakeupGen level */ | 430 | /* Clear all IRQ bitmasks at wakeupGen level */ |
| 424 | for (i = 0; i < irq_banks; i++) { | 431 | for (i = 0; i < irq_banks; i++) { |
| 425 | wakeupgen_writel(0, i, CPU0_ID); | 432 | wakeupgen_writel(0, i, CPU0_ID); |
| 426 | wakeupgen_writel(0, i, CPU1_ID); | 433 | if (!soc_is_am43xx()) |
| 434 | wakeupgen_writel(0, i, CPU1_ID); | ||
| 427 | } | 435 | } |
| 428 | 436 | ||
| 429 | /* | 437 | /* |