diff options
author | Juha Yrjola <juha.yrjola@solidboot.com> | 2006-12-06 20:13:46 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2007-09-20 12:59:16 -0400 |
commit | 33c9907535cef6cb5de1269540c04664c393d09c (patch) | |
tree | 6ed91debf2685a87c726964ea56f40d2209de5dc /arch/arm/mach-omap2/memory.c | |
parent | 81cfe79b9c577139a873483654640eb3f6e78c39 (diff) |
ARM: OMAP2: Place SMS and SDRC into smart idle mode
Place SMS and SDRC into smart idle mode
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/memory.c')
-rw-r--r-- | arch/arm/mach-omap2/memory.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 85cbc2a2e663..f173aa8d896f 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c | |||
@@ -30,6 +30,38 @@ | |||
30 | #include "prcm-regs.h" | 30 | #include "prcm-regs.h" |
31 | #include "memory.h" | 31 | #include "memory.h" |
32 | 32 | ||
33 | #define SMS_BASE 0x68008000 | ||
34 | #define SMS_SYSCONFIG 0x010 | ||
35 | |||
36 | #define SDRC_BASE 0x68009000 | ||
37 | #define SDRC_SYSCONFIG 0x010 | ||
38 | #define SDRC_SYSSTATUS 0x014 | ||
39 | |||
40 | static const u32 sms_base = IO_ADDRESS(SMS_BASE); | ||
41 | static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE); | ||
42 | |||
43 | |||
44 | static inline void sms_write_reg(int idx, u32 val) | ||
45 | { | ||
46 | __raw_writel(val, sms_base + idx); | ||
47 | } | ||
48 | |||
49 | static inline u32 sms_read_reg(int idx) | ||
50 | { | ||
51 | return __raw_readl(sms_base + idx); | ||
52 | } | ||
53 | |||
54 | static inline void sdrc_write_reg(int idx, u32 val) | ||
55 | { | ||
56 | __raw_writel(val, sdrc_base + idx); | ||
57 | } | ||
58 | |||
59 | static inline u32 sdrc_read_reg(int idx) | ||
60 | { | ||
61 | return __raw_readl(sdrc_base + idx); | ||
62 | } | ||
63 | |||
64 | |||
33 | static struct memory_timings mem_timings; | 65 | static struct memory_timings mem_timings; |
34 | 66 | ||
35 | u32 omap2_memory_get_slow_dll_ctrl(void) | 67 | u32 omap2_memory_get_slow_dll_ctrl(void) |
@@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | |||
99 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ | 131 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ |
100 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); | 132 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
101 | } | 133 | } |
134 | |||
135 | void __init omap2_init_memory(void) | ||
136 | { | ||
137 | u32 l; | ||
138 | |||
139 | l = sms_read_reg(SMS_SYSCONFIG); | ||
140 | l &= ~(0x3 << 3); | ||
141 | l |= (0x2 << 3); | ||
142 | sms_write_reg(SMS_SYSCONFIG, l); | ||
143 | |||
144 | l = sdrc_read_reg(SDRC_SYSCONFIG); | ||
145 | l &= ~(0x3 << 3); | ||
146 | l |= (0x2 << 3); | ||
147 | sdrc_write_reg(SDRC_SYSCONFIG, l); | ||
148 | |||
149 | } | ||