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authorTakashi Iwai <tiwai@suse.de>2009-09-10 09:32:40 -0400
committerTakashi Iwai <tiwai@suse.de>2009-09-10 09:32:40 -0400
commite0b3032bcdf1419d97de636d5fb1c9469da75776 (patch)
tree30252bef7afdad1f789b215c99909104a1d5cfa1 /arch/arm/mach-omap2/mcbsp.c
parent45fae5c78d873b10c66dfc04db6701e05c493791 (diff)
parentcdc65fbe18aef15e92d2ebb410a189fbf956fb06 (diff)
Merge branch 'topic/asoc' into for-linus
* topic/asoc: (226 commits) ASoC: au1x: PSC-AC97 bugfixes ASoC: Fix WM835x Out4 capture enumeration ASoC: Remove unuused hw_read_t ASoC: fix pxa2xx-ac97.c breakage ASoC: Fully specify DC servo bits to update in wm_hubs ASoC: Debugged improper setting of PLL fields in WM8580 driver ASoC: new board driver to connect bfin-5xx with ad1836 codec ASoC: OMAP: Add functionality to set CLKR and FSR sources in McBSP DAI ASoC: davinci: i2c device creation moved into board files ASoC: Don't reconfigure WM8350 FLL if not needed ASoC: Fix s3c-i2s-v2 build ASoC: Make platform data optional for TLV320AIC3x ASoC: Add S3C24xx dependencies for Simtec machines ASoC: SDP3430: Fix TWL GPIO6 pin mux request ASoC: S3C platform: Fix s3c2410_dma_started() called at improper time ARM: OMAP: McBSP: Merge two functions into omap_mcbsp_start/_stop ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI OMAP: McBSP: Use textual values in DMA operating mode sysfs files ARM: OMAP: DMA: Add support for DMA channel self linking on OMAP1510 ASoC: Select core DMA when building for S3C64xx ...
Diffstat (limited to 'arch/arm/mach-omap2/mcbsp.c')
-rw-r--r--arch/arm/mach-omap2/mcbsp.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 99b6e1546311..0447d26d454b 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -128,6 +128,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
128 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 128 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
129 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 129 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
130 .ops = &omap2_mcbsp_ops, 130 .ops = &omap2_mcbsp_ops,
131 .buffer_size = 0x6F,
131 }, 132 },
132 { 133 {
133 .phys_base = OMAP34XX_MCBSP2_BASE, 134 .phys_base = OMAP34XX_MCBSP2_BASE,
@@ -136,6 +137,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
136 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 137 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
137 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 138 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
138 .ops = &omap2_mcbsp_ops, 139 .ops = &omap2_mcbsp_ops,
140 .buffer_size = 0x3FF,
139 }, 141 },
140 { 142 {
141 .phys_base = OMAP34XX_MCBSP3_BASE, 143 .phys_base = OMAP34XX_MCBSP3_BASE,
@@ -144,6 +146,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
144 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 146 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
145 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 147 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
146 .ops = &omap2_mcbsp_ops, 148 .ops = &omap2_mcbsp_ops,
149 .buffer_size = 0x6F,
147 }, 150 },
148 { 151 {
149 .phys_base = OMAP34XX_MCBSP4_BASE, 152 .phys_base = OMAP34XX_MCBSP4_BASE,
@@ -152,6 +155,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
152 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 155 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
153 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 156 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
154 .ops = &omap2_mcbsp_ops, 157 .ops = &omap2_mcbsp_ops,
158 .buffer_size = 0x6F,
155 }, 159 },
156 { 160 {
157 .phys_base = OMAP34XX_MCBSP5_BASE, 161 .phys_base = OMAP34XX_MCBSP5_BASE,
@@ -160,6 +164,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
160 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 164 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
161 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 165 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
162 .ops = &omap2_mcbsp_ops, 166 .ops = &omap2_mcbsp_ops,
167 .buffer_size = 0x6F,
163 }, 168 },
164}; 169};
165#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) 170#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)