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authorHiroshi DOYU <Hiroshi.DOYU@nokia.com>2009-09-24 19:23:09 -0400
committerTony Lindgren <tony@atomide.com>2009-09-24 19:23:09 -0400
commit1ffe627dcfce820b316ee520c58fca54550a18ee (patch)
treef4a7b11226b0d54b4ddfd0bcd909167a29f1d1b7 /arch/arm/mach-omap2/mailbox.c
parent41a03c539c6e3cc772fc15a827ea2aa040c9848d (diff)
omap: mailbox: Execute softreset at startup
The softreset at startup is introduced as TRM describes and also some register bit definitions are added instead of magic number. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/mailbox.c')
-rw-r--r--arch/arm/mach-omap2/mailbox.c30
1 files changed, 25 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 6f71f3730c97..5bf9a2fdb682 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -30,6 +30,14 @@
30#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u))) 30#define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u)))
31#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1)) 31#define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1))
32 32
33/* SYSCONFIG: register bit definition */
34#define AUTOIDLE (1 << 0)
35#define SOFTRESET (1 << 1)
36#define SMARTIDLE (2 << 3)
37
38/* SYSSTATUS: register bit definition */
39#define RESETDONE (1 << 0)
40
33#define MBOX_REG_SIZE 0x120 41#define MBOX_REG_SIZE 0x120
34#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) 42#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
35 43
@@ -69,21 +77,33 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
69/* Mailbox H/W preparations */ 77/* Mailbox H/W preparations */
70static int omap2_mbox_startup(struct omap_mbox *mbox) 78static int omap2_mbox_startup(struct omap_mbox *mbox)
71{ 79{
72 unsigned int l; 80 u32 l;
81 unsigned long timeout;
73 82
74 mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); 83 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
75 if (IS_ERR(mbox_ick_handle)) { 84 if (IS_ERR(mbox_ick_handle)) {
76 printk("Could not get mailboxes_ick\n"); 85 pr_err("Can't get mailboxes_ick\n");
77 return -ENODEV; 86 return -ENODEV;
78 } 87 }
79 clk_enable(mbox_ick_handle); 88 clk_enable(mbox_ick_handle);
80 89
90 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
91 timeout = jiffies + msecs_to_jiffies(20);
92 do {
93 l = mbox_read_reg(MAILBOX_SYSSTATUS);
94 if (l & RESETDONE)
95 break;
96 } while (time_after(jiffies, timeout));
97
98 if (!(l & RESETDONE)) {
99 pr_err("Can't take mmu out of reset\n");
100 return -ENODEV;
101 }
102
81 l = mbox_read_reg(MAILBOX_REVISION); 103 l = mbox_read_reg(MAILBOX_REVISION);
82 pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); 104 pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
83 105
84 /* set smart-idle & autoidle */ 106 l = SMARTIDLE | AUTOIDLE;
85 l = mbox_read_reg(MAILBOX_SYSCONFIG);
86 l |= 0x00000011;
87 mbox_write_reg(l, MAILBOX_SYSCONFIG); 107 mbox_write_reg(l, MAILBOX_SYSCONFIG);
88 108
89 omap2_mbox_enable_irq(mbox, IRQ_RX); 109 omap2_mbox_enable_irq(mbox, IRQ_RX);