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authorJuha Yrjola <juha.yrjola@solidboot.com>2006-12-06 20:13:50 -0500
committerTony Lindgren <tony@atomide.com>2007-09-20 12:59:19 -0400
commit375e12abceac4e8e20ea54ff6a9e7be58729ac70 (patch)
tree11bb804bc7dc1f9e9837a1853ac7958ab2b5a054 /arch/arm/mach-omap2/irq.c
parent33c9907535cef6cb5de1269540c04664c393d09c (diff)
ARM: OMAP: Optimize INTC register accesses and enable autoidling
Use virtual addresses directly instead of physical addresses to avoid having to recalculate the virtual address with every register access. Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/irq.c')
-rw-r--r--arch/arm/mach-omap2/irq.c19
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index a39d30680300..f064f725e724 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -37,7 +37,7 @@ static struct omap_irq_bank {
37} __attribute__ ((aligned(4))) irq_banks[] = { 37} __attribute__ ((aligned(4))) irq_banks[] = {
38 { 38 {
39 /* MPU INTC */ 39 /* MPU INTC */
40 .base_reg = OMAP24XX_IC_BASE, 40 .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE),
41 .nr_irqs = 96, 41 .nr_irqs = 96,
42 }, { 42 }, {
43 /* XXX: DSP INTC */ 43 /* XXX: DSP INTC */
@@ -47,7 +47,7 @@ static struct omap_irq_bank {
47/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 47/* XXX: FIQ and additional INTC support (only MPU at the moment) */
48static void omap_ack_irq(unsigned int irq) 48static void omap_ack_irq(unsigned int irq)
49{ 49{
50 omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); 50 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
51} 51}
52 52
53static void omap_mask_irq(unsigned int irq) 53static void omap_mask_irq(unsigned int irq)
@@ -60,7 +60,7 @@ static void omap_mask_irq(unsigned int irq)
60 irq %= 32; 60 irq %= 32;
61 } 61 }
62 62
63 omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); 63 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
64} 64}
65 65
66static void omap_unmask_irq(unsigned int irq) 66static void omap_unmask_irq(unsigned int irq)
@@ -73,7 +73,7 @@ static void omap_unmask_irq(unsigned int irq)
73 irq %= 32; 73 irq %= 32;
74 } 74 }
75 75
76 omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); 76 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
77} 77}
78 78
79static void omap_mask_ack_irq(unsigned int irq) 79static void omap_mask_ack_irq(unsigned int irq)
@@ -93,17 +93,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
93{ 93{
94 unsigned long tmp; 94 unsigned long tmp;
95 95
96 tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff; 96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx " 97 printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
98 "(revision %ld.%ld) with %d interrupts\n", 98 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
100 100
101 tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG); 101 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
102 tmp |= 1 << 1; /* soft reset */ 102 tmp |= 1 << 1; /* soft reset */
103 omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG); 103 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
104 104
105 while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) 105 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
106 /* Wait for reset to complete */; 106 /* Wait for reset to complete */;
107
108 /* Enable autoidle */
109 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
107} 110}
108 111
109void __init omap_init_irq(void) 112void __init omap_init_irq(void)