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authorPaul Walmsley <paul@pwsan.com>2009-06-19 21:08:25 -0400
committerpaul <paul@twilight.(none)>2009-06-19 21:09:30 -0400
commit2f135eaf182761bb9a5cbd5138a447b0ad2a1fef (patch)
treeceac7506d9d004dc0f6b2aaf56fd395fe411c1d7 /arch/arm/mach-omap2/io.c
parent6adb8f388ef2f23d4a81e1e42d15f22d62749a06 (diff)
OMAP3 clock: initialize SDRC timings at kernel start
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/io.c')
-rw-r--r--arch/arm/mach-omap2/io.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 32afd9448216..3a86b0f66031 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,6 +21,7 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
24 25
25#include <asm/tlb.h> 26#include <asm/tlb.h>
26 27
@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
241 omapfb_reserve_sdram(); 242 omapfb_reserve_sdram();
242} 243}
243 244
245/*
246 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
247 *
248 * Sets the CORE DPLL3 M2 divider to the same value that it's at
249 * currently. This has the effect of setting the SDRC SDRAM AC timing
250 * registers to the values currently defined by the kernel. Currently
251 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
252 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
253 * or passes along the return value of clk_set_rate().
254 */
255static int __init _omap2_init_reprogram_sdrc(void)
256{
257 struct clk *dpll3_m2_ck;
258 int v = -EINVAL;
259 long rate;
260
261 if (!cpu_is_omap34xx())
262 return 0;
263
264 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
265 if (!dpll3_m2_ck)
266 return -EINVAL;
267
268 rate = clk_get_rate(dpll3_m2_ck);
269 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
270 v = clk_set_rate(dpll3_m2_ck, rate);
271 if (v)
272 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
273
274 clk_put(dpll3_m2_ck);
275
276 return v;
277}
278
244void __init omap2_init_common_hw(struct omap_sdrc_params *sp) 279void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
245{ 280{
246 omap2_mux_init(); 281 omap2_mux_init();
@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
249 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); 284 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
250 omap2_clk_init(); 285 omap2_clk_init();
251 omap2_sdrc_init(sp); 286 omap2_sdrc_init(sp);
287 _omap2_init_reprogram_sdrc();
252#endif 288#endif
253 gpmc_init(); 289 gpmc_init();
254} 290}