diff options
author | Magnus Damm <magnus.damm@gmail.com> | 2010-11-15 19:07:19 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-12-07 04:20:26 -0500 |
commit | e745a6676c76280f9721adeec79b08a0f2dfcc21 (patch) | |
tree | 0a4655324aa851afbd183a2b93aeb09d4183c569 /arch/arm/mach-omap2/include/mach | |
parent | c91a2bd70a617a638e157a7e99d4b21ee0e7b1cf (diff) |
ARM: 6481/1: Use shared GIC entry macros on OMAP
Common GIC entry macro for omap
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/include/mach')
-rw-r--r-- | arch/arm/mach-omap2/include/mach/entry-macro.S | 92 |
1 files changed, 31 insertions, 61 deletions
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 06e64e1fc28a..2e358df3fe19 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
@@ -105,6 +105,35 @@ omap_irq_base: .word 0 | |||
105 | 9999: | 105 | 9999: |
106 | .endm | 106 | .endm |
107 | 107 | ||
108 | #ifdef CONFIG_SMP | ||
109 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
110 | * register) is preserved from the macro above. | ||
111 | * If there is an IPI, we immediately signal end of interrupt | ||
112 | * on the controller, since this requires the original irqstat | ||
113 | * value which we won't easily be able to recreate later. | ||
114 | */ | ||
115 | |||
116 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
117 | bic \irqnr, \irqstat, #0x1c00 | ||
118 | cmp \irqnr, #16 | ||
119 | it cc | ||
120 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
121 | it cs | ||
122 | cmpcs \irqnr, \irqnr | ||
123 | .endm | ||
124 | |||
125 | /* As above, this assumes that irqstat and base are preserved */ | ||
126 | |||
127 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
128 | bic \irqnr, \irqstat, #0x1c00 | ||
129 | mov \tmp, #0 | ||
130 | cmp \irqnr, #29 | ||
131 | itt eq | ||
132 | moveq \tmp, #1 | ||
133 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
134 | cmp \tmp, #0 | ||
135 | .endm | ||
136 | #endif /* CONFIG_SMP */ | ||
108 | 137 | ||
109 | #else /* MULTI_OMAP2 */ | 138 | #else /* MULTI_OMAP2 */ |
110 | 139 | ||
@@ -141,74 +170,15 @@ omap_irq_base: .word 0 | |||
141 | 170 | ||
142 | 171 | ||
143 | #ifdef CONFIG_ARCH_OMAP4 | 172 | #ifdef CONFIG_ARCH_OMAP4 |
173 | #include <asm/hardware/entry-macro-gic.S> | ||
144 | 174 | ||
145 | .macro get_irqnr_preamble, base, tmp | 175 | .macro get_irqnr_preamble, base, tmp |
146 | ldr \base, =OMAP4_IRQ_BASE | 176 | ldr \base, =OMAP4_IRQ_BASE |
147 | .endm | 177 | .endm |
148 | 178 | ||
149 | /* | ||
150 | * The interrupt numbering scheme is defined in the | ||
151 | * interrupt controller spec. To wit: | ||
152 | * | ||
153 | * Interrupts 0-15 are IPI | ||
154 | * 16-28 are reserved | ||
155 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
156 | * 32-1020 are global | ||
157 | * 1021-1022 are reserved | ||
158 | * 1023 is "spurious" (no interrupt) | ||
159 | * | ||
160 | * For now, we ignore all local interrupts so only return an | ||
161 | * interrupt if it's between 30 and 1020. The test_for_ipi | ||
162 | * routine below will pick up on IPIs. | ||
163 | * A simple read from the controller will tell us the number | ||
164 | * of the highest priority enabled interrupt. | ||
165 | * We then just need to check whether it is in the | ||
166 | * valid range for an IRQ (30-1020 inclusive). | ||
167 | */ | ||
168 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
169 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
170 | |||
171 | ldr \tmp, =1021 | ||
172 | |||
173 | bic \irqnr, \irqstat, #0x1c00 | ||
174 | |||
175 | cmp \irqnr, #29 | ||
176 | cmpcc \irqnr, \irqnr | ||
177 | cmpne \irqnr, \tmp | ||
178 | cmpcs \irqnr, \irqnr | ||
179 | .endm | ||
180 | #endif | 179 | #endif |
181 | #endif /* MULTI_OMAP2 */ | ||
182 | |||
183 | #ifdef CONFIG_SMP | ||
184 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
185 | * register) is preserved from the macro above. | ||
186 | * If there is an IPI, we immediately signal end of interrupt | ||
187 | * on the controller, since this requires the original irqstat | ||
188 | * value which we won't easily be able to recreate later. | ||
189 | */ | ||
190 | 180 | ||
191 | .macro test_for_ipi, irqnr, irqstat, base, tmp | 181 | #endif /* MULTI_OMAP2 */ |
192 | bic \irqnr, \irqstat, #0x1c00 | ||
193 | cmp \irqnr, #16 | ||
194 | it cc | ||
195 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
196 | it cs | ||
197 | cmpcs \irqnr, \irqnr | ||
198 | .endm | ||
199 | |||
200 | /* As above, this assumes that irqstat and base are preserved */ | ||
201 | |||
202 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
203 | bic \irqnr, \irqstat, #0x1c00 | ||
204 | mov \tmp, #0 | ||
205 | cmp \irqnr, #29 | ||
206 | itt eq | ||
207 | moveq \tmp, #1 | ||
208 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
209 | cmp \tmp, #0 | ||
210 | .endm | ||
211 | #endif /* CONFIG_SMP */ | ||
212 | 182 | ||
213 | .macro irq_prio_table | 183 | .macro irq_prio_table |
214 | .endm | 184 | .endm |