diff options
author | Tony Lindgren <tony@atomide.com> | 2010-09-27 16:17:13 -0400 |
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committer | Tony Lindgren <tony@atomide.com> | 2010-09-27 16:17:13 -0400 |
commit | 91f6c90c8df1818a66d177e105d602c3da820919 (patch) | |
tree | 5cb1b01823dd676a07596f6153d2fc124c4691cb /arch/arm/mach-omap2/hsmmc.c | |
parent | 6e457bb05c348e196f67005876992ceb5eb0430a (diff) | |
parent | a3fed9bc181666df6ecfe9ce34a29d48803f2310 (diff) |
Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for-linus
Diffstat (limited to 'arch/arm/mach-omap2/hsmmc.c')
-rw-r--r-- | arch/arm/mach-omap2/hsmmc.c | 67 |
1 files changed, 36 insertions, 31 deletions
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index 87ce6ffccefc..eb92b8107d2c 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c | |||
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, | |||
135 | * | 135 | * |
136 | * FIXME handle VMMC1A as needed ... | 136 | * FIXME handle VMMC1A as needed ... |
137 | */ | 137 | */ |
138 | reg = omap_ctrl_readl(control_pbias_offset); | 138 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
139 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | | 139 | reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | |
140 | OMAP4_USBC1_ICUSB_PWRDNZ); | 140 | OMAP4_MMC1_PWRDNZ_MASK | |
141 | omap_ctrl_writel(reg, control_pbias_offset); | 141 | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); |
142 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
142 | } | 143 | } |
143 | 144 | ||
144 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | 145 | static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, |
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, | |||
147 | u32 reg; | 148 | u32 reg; |
148 | 149 | ||
149 | if (power_on) { | 150 | if (power_on) { |
150 | reg = omap_ctrl_readl(control_pbias_offset); | 151 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
151 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; | 152 | reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; |
152 | if ((1 << vdd) <= MMC_VDD_165_195) | 153 | if ((1 << vdd) <= MMC_VDD_165_195) |
153 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; | 154 | reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
154 | else | 155 | else |
155 | reg |= OMAP4_MMC1_PBIASLITE_VMODE; | 156 | reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; |
156 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | | 157 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | |
157 | OMAP4_USBC1_ICUSB_PWRDNZ); | 158 | OMAP4_MMC1_PWRDNZ_MASK | |
158 | omap_ctrl_writel(reg, control_pbias_offset); | 159 | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); |
160 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
159 | /* 4 microsec delay for comparator to generate an error*/ | 161 | /* 4 microsec delay for comparator to generate an error*/ |
160 | udelay(4); | 162 | udelay(4); |
161 | reg = omap_ctrl_readl(control_pbias_offset); | 163 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
162 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { | 164 | if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { |
163 | pr_err("Pbias Voltage is not same as LDO\n"); | 165 | pr_err("Pbias Voltage is not same as LDO\n"); |
164 | /* Caution : On VMODE_ERROR Power Down MMC IO */ | 166 | /* Caution : On VMODE_ERROR Power Down MMC IO */ |
165 | reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); | 167 | reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | |
166 | omap_ctrl_writel(reg, control_pbias_offset); | 168 | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); |
169 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
167 | } | 170 | } |
168 | } else { | 171 | } else { |
169 | reg = omap_ctrl_readl(control_pbias_offset); | 172 | reg = omap4_ctrl_pad_readl(control_pbias_offset); |
170 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | | 173 | reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | |
171 | OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | | 174 | OMAP4_MMC1_PWRDNZ_MASK | |
172 | OMAP4_USBC1_ICUSB_PWRDNZ); | 175 | OMAP4_MMC1_PBIASLITE_VMODE_MASK | |
173 | omap_ctrl_writel(reg, control_pbias_offset); | 176 | OMAP4_USBC1_ICUSB_PWRDNZ_MASK); |
177 | omap4_ctrl_pad_writel(reg, control_pbias_offset); | ||
174 | } | 178 | } |
175 | } | 179 | } |
176 | 180 | ||
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) | |||
218 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; | 222 | control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; |
219 | } | 223 | } |
220 | } else { | 224 | } else { |
221 | control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; | 225 | control_pbias_offset = |
222 | control_mmc1 = OMAP44XX_CONTROL_MMC1; | 226 | OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; |
223 | reg = omap_ctrl_readl(control_mmc1); | 227 | control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; |
224 | reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | | 228 | reg = omap4_ctrl_pad_readl(control_mmc1); |
225 | OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); | 229 | reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | |
226 | reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | | 230 | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); |
227 | OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); | 231 | reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | |
228 | reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | | 232 | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); |
229 | OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | | 233 | reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| |
230 | OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); | 234 | OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | |
231 | omap_ctrl_writel(reg, control_mmc1); | 235 | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); |
236 | omap4_ctrl_pad_writel(reg, control_mmc1); | ||
232 | } | 237 | } |
233 | 238 | ||
234 | for (c = controllers; c->mmc; c++) { | 239 | for (c = controllers; c->mmc; c++) { |