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authorAfzal Mohammed <afzal@ti.com>2012-05-28 08:21:37 -0400
committerAfzal Mohammed <afzal@ti.com>2012-11-09 07:37:11 -0500
commit559d94b00c4dca74b060bae1feeb81cac38628a6 (patch)
treeb5294c16ac82c6ecac29b288f29555da20e690e4 /arch/arm/mach-omap2/gpmc.h
parenta1bfdc6020c2ac52fbadca11cc99c7c63b310d37 (diff)
ARM: OMAP2+: gpmc: handle additional timings
Configure busturnaround, cycle2cycledelay, waitmonitoringtime, clkactivationtime in gpmc_cs_set_timings(). This is done so that boards can configure these parameters of gpmc in Kernel instead of relying on bootloader. Also configure bool type timings like extradelay. This needed change to the existing users that were configuring clk activation time and extra delay by directly writing to registers. Thanks to Tony for making me aware of users of clk activation and being kind enough to test the modified one. Signed-off-by: Afzal Mohammed <afzal@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc.h')
-rw-r--r--arch/arm/mach-omap2/gpmc.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 79f4dfc2adb3..e08a51a7a76a 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -74,6 +74,17 @@
74#define GPMC_IRQ_COUNT_EVENT 0x02 74#define GPMC_IRQ_COUNT_EVENT 0x02
75 75
76 76
77/* bool type time settings */
78struct gpmc_bool_timings {
79 bool cycle2cyclediffcsen;
80 bool cycle2cyclesamecsen;
81 bool we_extra_delay;
82 bool oe_extra_delay;
83 bool adv_extra_delay;
84 bool cs_extra_delay;
85 bool time_para_granularity;
86};
87
77/* 88/*
78 * Note that all values in this struct are in nanoseconds except sync_clk 89 * Note that all values in this struct are in nanoseconds except sync_clk
79 * (which is in picoseconds), while the register values are in gpmc_fck cycles. 90 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
@@ -106,9 +117,17 @@ struct gpmc_timings {
106 u16 rd_cycle; /* Total read cycle time */ 117 u16 rd_cycle; /* Total read cycle time */
107 u16 wr_cycle; /* Total write cycle time */ 118 u16 wr_cycle; /* Total write cycle time */
108 119
120 u16 bus_turnaround;
121 u16 cycle2cycle_delay;
122
123 u16 wait_monitoring;
124 u16 clk_activation;
125
109 /* The following are only on OMAP3430 */ 126 /* The following are only on OMAP3430 */
110 u16 wr_access; /* WRACCESSTIME */ 127 u16 wr_access; /* WRACCESSTIME */
111 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 128 u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
129
130 struct gpmc_bool_timings bool_timings;
112}; 131};
113 132
114extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 133extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);